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/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dmscc_sgpio.txt1 Microsemi Corporation (MSCC) Serial GPIO driver
3 The MSCC serial GPIO extends the number or GPIO's on the system by
6 effective GPIO count can be extended by up to 128 GPIO's per
10 - compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
11 - clock: Reference clock used to generate clock divider setting. See
12 mscc,sgpio-frequency property.
13 - reg : Physical base address and length of the controller's registers.
14 - #gpio-cells : Should be two. The first cell is the pin number and the
16 - bit 0 specifies polarity (0 for normal, 1 for inverted)
17 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
68 TYPE_ND, /* Normal-drive */
69 TYPE_HD, /* High-drive */
70 TYPE_HS, /* High-speed */
146 [FUNC_GPIO] = "gpio",
164 [FUNC_SGPIO] = "sgpio",
240 LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
241 LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
242 LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed SGPIO controller
10 - Andrew Jeffery <andrew@aj.id.au>
13 This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
14 AST2600 have two sgpio master one with 128 pins another one with 80 pins,
15 AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
16 GPIO pins can be programmed to support the following options
[all …]
H A Dnuvoton,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton SGPIO controller
10 - Jim LIU <JJLIU0@nuvoton.com>
13 This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC and detailed
15 Nuvoton NPCM7xx SGPIO module is combines a serial to parallel IC (HC595)
19 NPCM7xx/NPCM8xx have two sgpio modules. Each module can support up
21 GPIO pins can be programmed to support the following options
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,jr2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
14 stdout-path = "serial0:115200n8";
17 gpio-leds {
18 compatible = "gpio-leds";
22 gpios = <&sgpio 44 1>; /* p12.1 */
23 default-state = "off";
28 gpios = <&sgpio 12 1>; /* p12.0 */
29 default-state = "off";
[all …]
H A Djr2_pcb110.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
11 compatible = "mscc,jr2-pcb110", "mscc,jr2";
19 stdout-path = "serial0:115200n8";
22 gpio-leds {
23 compatible = "gpio-leds";
27 gpios = <&gpio 12 0>;
28 default-state = "on";
33 gpios = <&gpio 13 0>;
[all …]
H A Djr2_pcb111.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,jr2-pcb111", "mscc,jr2";
19 stdout-path = "serial0:115200n8";
22 gpio-leds {
23 compatible = "gpio-leds";
27 gpios = <&gpio 12 0>;
28 default-state = "on";
33 gpios = <&gpio 13 0>;
34 default-state = "off";
[all …]
H A Docelot_pcb123.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
14 stdout-path = "serial0:115200n8";
17 gpio-leds {
18 compatible = "gpio-leds";
22 gpios = <&sgpio 43 1>; /* p11.1 */
23 default-state = "on";
28 gpios = <&sgpio 11 1>; /* p11.0 */
29 default-state = "off";
[all …]
H A Dluton_pcb090.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,luton-pcb090", "mscc,luton";
19 stdout-path = "serial0:115200n8";
22 gpio-leds {
23 compatible = "gpio-leds";
27 gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
28 default-state = "on";
33 gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
34 default-state = "off";
[all …]
H A Dserval2_pcb112.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,serval2-pcb110", "mscc,jr2";
19 stdout-path = "serial0:115200n8";
22 gpio-leds {
23 compatible = "gpio-leds";
27 gpios = <&gpio 12 0>;
28 default-state = "on";
33 gpios = <&gpio 13 0>;
34 default-state = "off";
[all …]
H A Dserval_pcb105.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,serval-pcb105", "mscc,serval";
19 stdout-path = "serial0:115200n8";
22 gpio-leds {
23 compatible = "gpio-leds";
27 gpios = <&sgpio 43 1>; /* p11.1 */
28 default-state = "on";
33 gpios = <&sgpio 11 1>; /* p11.0 */
34 default-state = "off";
[all …]
H A Dserval_pcb106.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,serval-pcb106", "mscc,serval";
19 stdout-path = "serial0:115200n8";
22 gpio-leds {
23 compatible = "gpio-leds";
27 gpios = <&sgpio 43 1>; /* p11.1 */
28 default-state = "on";
33 gpios = <&sgpio 11 1>; /* p11.0 */
34 default-state = "off";
[all …]
H A Dservalt_pcb116.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,servalt-pcb116", "mscc,servalt";
19 stdout-path = "serial0:115200n8";
22 gpio-leds {
23 compatible = "gpio-leds";
27 gpios = <&sgpio 70 0>; /* p6.2 */
28 default-state = "on";
33 gpios = <&sgpio 102 0>; /* p6.3 */
34 default-state = "off";
[all …]
H A Dmscc,serval.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
H A Dmscc,servalt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
[all …]
H A Dluton_pcb091.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "mscc,luton-pcb091", "mscc,luton";
19 stdout-path = "serial0:115200n8";
22 gpio-leds {
23 compatible = "gpio-leds";
27 gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
28 default-state = "on";
33 gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
34 default-state = "on";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
18 The switch family is a multi-port networking switch that supports many
20 external GPIO expanders.
25 - mscc,vsc7512
30 "#address-cells":
33 "#size-cells":
[all …]
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/gpio/phosphor-gpio-monitor/
H A Dmulti-gpios-sys-init3 # shellcheck source=meta-facebook/recipes-fb/obmc_functions/files/fb-common-functions
4 source /usr/libexec/fb-common-functions
5 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/power-cmd
6 source /usr/libexec/phosphor-state-manager/power-cmd
12 if [ "$(get_gpio "power-host-good")" -eq 1 ] && [ "$valid_sgpio" -eq 0 ]; then
13 systemctl start obmc-led-group-start@power_on.service
15 systemctl start obmc-led-group-stop@power_on.service
20 if [ "$(get_gpio post-end-n)" -eq 0 ]; then
21 busctl set-property xyz.openbmc_project.State.Host0 /xyz/openbmc_project/state/host0 \
25 busctl set-property xyz.openbmc_project.Software.BMC.Updater \
[all …]
/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb134_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
12 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
17 compatible = "gpio-leds";
53 default-state = "off";
58 default-state = "off";
63 default-state = "off";
68 default-state = "off";
[all …]
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
28 #size-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
33 sending an SGPIO pattern.
35 calxeda,post-clocks:
39 sending an SGPIO pattern.
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dmscc_sgpio.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi SoCs serial gpio driver
12 #include <asm/gpio.h>
44 #define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
46 #define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
47 #define MSCC_F_CFG_SIO_PORT_WIDTH(p, x) __F(p->props->port_width, x)
48 #define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
49 #define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x) __F(p->props->clk_freq, x)
50 #define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
51 #define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
23 gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
[all …]

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