1e39c6783SLars Povlsen// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2e39c6783SLars Povlsen/* 3e39c6783SLars Povlsen * Copyright (c) 2018 Microsemi Corporation 4e39c6783SLars Povlsen */ 5e39c6783SLars Povlsen 6e39c6783SLars Povlsen/dts-v1/; 7e39c6783SLars Povlsen#include "mscc,luton.dtsi" 8e39c6783SLars Povlsen 9e39c6783SLars Povlsen/ { 10e39c6783SLars Povlsen model = "Luton26 PCB090 Reference Board"; 11e39c6783SLars Povlsen compatible = "mscc,luton-pcb090", "mscc,luton"; 12e39c6783SLars Povlsen 13e39c6783SLars Povlsen aliases { 14e39c6783SLars Povlsen serial0 = &uart0; 15e39c6783SLars Povlsen spi0 = &spi0; 16e39c6783SLars Povlsen }; 17e39c6783SLars Povlsen 18e39c6783SLars Povlsen chosen { 19e39c6783SLars Povlsen stdout-path = "serial0:115200n8"; 20e39c6783SLars Povlsen }; 21738f2b14SLars Povlsen 22738f2b14SLars Povlsen gpio-leds { 23738f2b14SLars Povlsen compatible = "gpio-leds"; 24738f2b14SLars Povlsen 25738f2b14SLars Povlsen status_green { 26738f2b14SLars Povlsen label = "pcb090:green:status"; 27738f2b14SLars Povlsen gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */ 28738f2b14SLars Povlsen default-state = "on"; 29738f2b14SLars Povlsen }; 30738f2b14SLars Povlsen 31738f2b14SLars Povlsen status_red { 32738f2b14SLars Povlsen label = "pcb090:red:status"; 33738f2b14SLars Povlsen gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */ 34738f2b14SLars Povlsen default-state = "off"; 35738f2b14SLars Povlsen }; 36738f2b14SLars Povlsen }; 37738f2b14SLars Povlsen}; 38738f2b14SLars Povlsen 39738f2b14SLars Povlsen&sgpio { 40738f2b14SLars Povlsen status = "okay"; 41738f2b14SLars Povlsen gpio-ranges = <&sgpio 0 0 96>; 42e39c6783SLars Povlsen}; 43e39c6783SLars Povlsen 44e39c6783SLars Povlsen&uart0 { 45e39c6783SLars Povlsen status = "okay"; 46e39c6783SLars Povlsen}; 47e39c6783SLars Povlsen 48e39c6783SLars Povlsen&spi0 { 49e39c6783SLars Povlsen status = "okay"; 50e39c6783SLars Povlsen spi-flash@0 { 51e39c6783SLars Povlsen compatible = "spi-flash"; 52e39c6783SLars Povlsen spi-max-frequency = <18000000>; /* input clock */ 53e39c6783SLars Povlsen reg = <0>; /* CS0 */ 54e39c6783SLars Povlsen spi-cs-high; 55e39c6783SLars Povlsen }; 56e39c6783SLars Povlsen}; 57e39c6783SLars Povlsen 58*ee7b65f2SHoratiu Vultur&mdio0 { 59*ee7b65f2SHoratiu Vultur status = "okay"; 60*ee7b65f2SHoratiu Vultur}; 61*ee7b65f2SHoratiu Vultur 62*ee7b65f2SHoratiu Vultur&port0 { 63*ee7b65f2SHoratiu Vultur phy-handle = <&phy0>; 64*ee7b65f2SHoratiu Vultur}; 65*ee7b65f2SHoratiu Vultur 66*ee7b65f2SHoratiu Vultur&port1 { 67*ee7b65f2SHoratiu Vultur phy-handle = <&phy1>; 68*ee7b65f2SHoratiu Vultur}; 69*ee7b65f2SHoratiu Vultur 70*ee7b65f2SHoratiu Vultur&port2 { 71*ee7b65f2SHoratiu Vultur phy-handle = <&phy2>; 72*ee7b65f2SHoratiu Vultur}; 73*ee7b65f2SHoratiu Vultur 74*ee7b65f2SHoratiu Vultur&port3 { 75*ee7b65f2SHoratiu Vultur phy-handle = <&phy3>; 76*ee7b65f2SHoratiu Vultur}; 77*ee7b65f2SHoratiu Vultur 78*ee7b65f2SHoratiu Vultur&port4 { 79*ee7b65f2SHoratiu Vultur phy-handle = <&phy4>; 80*ee7b65f2SHoratiu Vultur}; 81*ee7b65f2SHoratiu Vultur 82*ee7b65f2SHoratiu Vultur&port5 { 83*ee7b65f2SHoratiu Vultur phy-handle = <&phy5>; 84*ee7b65f2SHoratiu Vultur}; 85*ee7b65f2SHoratiu Vultur 86*ee7b65f2SHoratiu Vultur&port6 { 87*ee7b65f2SHoratiu Vultur phy-handle = <&phy6>; 88*ee7b65f2SHoratiu Vultur}; 89*ee7b65f2SHoratiu Vultur 90*ee7b65f2SHoratiu Vultur&port7 { 91*ee7b65f2SHoratiu Vultur phy-handle = <&phy7>; 92*ee7b65f2SHoratiu Vultur}; 93*ee7b65f2SHoratiu Vultur 94*ee7b65f2SHoratiu Vultur&port8 { 95*ee7b65f2SHoratiu Vultur phy-handle = <&phy8>; 96*ee7b65f2SHoratiu Vultur}; 97*ee7b65f2SHoratiu Vultur 98*ee7b65f2SHoratiu Vultur&port9 { 99*ee7b65f2SHoratiu Vultur phy-handle = <&phy9>; 100*ee7b65f2SHoratiu Vultur}; 101*ee7b65f2SHoratiu Vultur 102*ee7b65f2SHoratiu Vultur&port10 { 103*ee7b65f2SHoratiu Vultur phy-handle = <&phy10>; 104*ee7b65f2SHoratiu Vultur}; 105*ee7b65f2SHoratiu Vultur 106*ee7b65f2SHoratiu Vultur&port11 { 107*ee7b65f2SHoratiu Vultur phy-handle = <&phy11>; 108*ee7b65f2SHoratiu Vultur}; 109