1*e3428309STomer Maimon# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*e3428309STomer Maimon%YAML 1.2
3*e3428309STomer Maimon---
4*e3428309STomer Maimon$id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml#
5*e3428309STomer Maimon$schema: http://devicetree.org/meta-schemas/core.yaml#
6*e3428309STomer Maimon
7*e3428309STomer Maimontitle: Nuvoton SGPIO controller
8*e3428309STomer Maimon
9*e3428309STomer Maimonmaintainers:
10*e3428309STomer Maimon  - Jim LIU <JJLIU0@nuvoton.com>
11*e3428309STomer Maimon
12*e3428309STomer Maimondescription: |
13*e3428309STomer Maimon  This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC and detailed
14*e3428309STomer Maimon  information is in the NPCM7XX/8XX SERIAL I/O EXPANSION INTERFACE section.
15*e3428309STomer Maimon  Nuvoton NPCM7xx SGPIO module is combines a serial to parallel IC (HC595)
16*e3428309STomer Maimon  and a parallel to serial IC (HC165).
17*e3428309STomer Maimon  Clock is a division of the APB3 clock.
18*e3428309STomer Maimon  This interface has 4 pins (D_out , D_in, S_CLK, LDSH).
19*e3428309STomer Maimon  NPCM7xx/NPCM8xx have two sgpio modules. Each module can support up
20*e3428309STomer Maimon  to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO.
21*e3428309STomer Maimon  GPIO pins can be programmed to support the following options
22*e3428309STomer Maimon  - Support interrupt option for each input port and various interrupt
23*e3428309STomer Maimon    sensitivity options (level-high, level-low, edge-high, edge-low)
24*e3428309STomer Maimon  - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines.
25*e3428309STomer Maimon    nuvoton,input-ngpios GPIO lines is only for GPI.
26*e3428309STomer Maimon    nuvoton,output-ngpios GPIO lines is only for GPO.
27*e3428309STomer Maimon
28*e3428309STomer Maimonproperties:
29*e3428309STomer Maimon  compatible:
30*e3428309STomer Maimon    enum:
31*e3428309STomer Maimon      - nuvoton,npcm750-sgpio
32*e3428309STomer Maimon      - nuvoton,npcm845-sgpio
33*e3428309STomer Maimon
34*e3428309STomer Maimon  reg:
35*e3428309STomer Maimon    maxItems: 1
36*e3428309STomer Maimon
37*e3428309STomer Maimon  gpio-controller: true
38*e3428309STomer Maimon
39*e3428309STomer Maimon  '#gpio-cells':
40*e3428309STomer Maimon    const: 2
41*e3428309STomer Maimon
42*e3428309STomer Maimon  interrupts:
43*e3428309STomer Maimon    maxItems: 1
44*e3428309STomer Maimon
45*e3428309STomer Maimon  clocks:
46*e3428309STomer Maimon    maxItems: 1
47*e3428309STomer Maimon
48*e3428309STomer Maimon  nuvoton,input-ngpios:
49*e3428309STomer Maimon    $ref: /schemas/types.yaml#/definitions/uint32
50*e3428309STomer Maimon    description:
51*e3428309STomer Maimon      The numbers of GPIO's exposed. GPIO lines are only for GPI.
52*e3428309STomer Maimon    minimum: 0
53*e3428309STomer Maimon    maximum: 64
54*e3428309STomer Maimon
55*e3428309STomer Maimon  nuvoton,output-ngpios:
56*e3428309STomer Maimon    $ref: /schemas/types.yaml#/definitions/uint32
57*e3428309STomer Maimon    description:
58*e3428309STomer Maimon      The numbers of GPIO's exposed. GPIO lines are only for GPO.
59*e3428309STomer Maimon    minimum: 0
60*e3428309STomer Maimon    maximum: 64
61*e3428309STomer Maimon
62*e3428309STomer Maimonrequired:
63*e3428309STomer Maimon  - compatible
64*e3428309STomer Maimon  - reg
65*e3428309STomer Maimon  - gpio-controller
66*e3428309STomer Maimon  - '#gpio-cells'
67*e3428309STomer Maimon  - interrupts
68*e3428309STomer Maimon  - nuvoton,input-ngpios
69*e3428309STomer Maimon  - nuvoton,output-ngpios
70*e3428309STomer Maimon  - clocks
71*e3428309STomer Maimon
72*e3428309STomer MaimonadditionalProperties: false
73*e3428309STomer Maimon
74*e3428309STomer Maimonexamples:
75*e3428309STomer Maimon  - |
76*e3428309STomer Maimon    #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
77*e3428309STomer Maimon    #include <dt-bindings/interrupt-controller/arm-gic.h>
78*e3428309STomer Maimon    gpio8: gpio@101000 {
79*e3428309STomer Maimon        compatible = "nuvoton,npcm750-sgpio";
80*e3428309STomer Maimon        reg = <0x101000 0x200>;
81*e3428309STomer Maimon        clocks = <&clk NPCM7XX_CLK_APB3>;
82*e3428309STomer Maimon        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
83*e3428309STomer Maimon        gpio-controller;
84*e3428309STomer Maimon        #gpio-cells = <2>;
85*e3428309STomer Maimon        nuvoton,input-ngpios = <64>;
86*e3428309STomer Maimon        nuvoton,output-ngpios = <64>;
87*e3428309STomer Maimon    };
88