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/openbmc/linux/drivers/clk/imx/
H A Dclk-imx35.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
15 #include "clk.h"
33 unsigned char arm, ahb, sel; member
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
[all …]
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
22 #include "clk.h"
154 return -ENOENT; in ldb_di_sel_by_clock_id()
165 return -ENOENT; in ldb_di_sel_by_clock_id()
175 int parent, child, sel; in of_assigned_ldb_sels() local
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clk.h>
32 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
33 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
34 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
35 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
36 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
37 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
38 {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
39 {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <asm/kona-common/clk.h>
18 #include "clk-core.h"
29 struct clk *c; in clk_get_and_enable()
40 return -EINVAL; in clk_get_and_enable()
73 return -ETIMEDOUT; in wait_bit()
77 static int peri_clk_enable(struct clk *c, int enable) in peri_clk_enable()
82 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
84 void *base = (void *)c->ccu_clk_mgr_base; in peri_clk_enable()
[all …]
H A Dclk-bcm235xx.c1 // SPDX-License-Identifier: GPL-2.0+
8 * bcm235xx-specific clock tables
16 #include <asm/kona-common/clk.h>
17 #include "clk-core.h"
25 .clk = { \
43 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
44 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
45 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
47 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
48 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <asm/kona-common/clk.h>
18 #include "clk-core.h"
29 struct clk *c; in clk_get_and_enable()
40 return -EINVAL; in clk_get_and_enable()
73 return -ETIMEDOUT; in wait_bit()
77 static int peri_clk_enable(struct clk *c, int enable) in peri_clk_enable()
82 struct peri_clk_data *cd = peri_clk->data; in peri_clk_enable()
83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable()
84 void *base = (void *)c->ccu_clk_mgr_base; in peri_clk_enable()
[all …]
H A Dclk-bcm281xx.c1 // SPDX-License-Identifier: GPL-2.0+
8 * bcm281xx-specific clock tables
16 #include <asm/kona-common/clk.h>
17 #include "clk-core.h"
25 .clk = { \
43 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
44 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
45 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
47 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
48 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-cbus-gpio.c4 * Copyright (C) 2004-2010 Nokia Corporation
40 struct gpio_desc *clk; member
42 struct gpio_desc *sel; member
46 * cbus_send_bit - sends one bit over the bus
52 gpiod_set_value(host->dat, bit ? 1 : 0); in cbus_send_bit()
53 gpiod_set_value(host->clk, 1); in cbus_send_bit()
54 gpiod_set_value(host->clk, 0); in cbus_send_bit()
58 * cbus_send_data - sends @len amount of data over the bus
67 for (i = len; i > 0; i--) in cbus_send_data()
68 cbus_send_bit(host, data & (1 << (i - 1))); in cbus_send_data()
[all …]
/openbmc/qemu/hw/misc/
H A Dnpcm7xx_clk.c21 #include "hw/qdev-clock.h"
23 #include "qemu/error-report.h"
38 #define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex-A9 Cores */
81 * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
111 #define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
114 #define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
117 #define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
124 uint32_t con = s->clk->regs[s->reg]; in npcm7xx_clk_update_pll()
129 freq = clock_get_hz(s->clock_in); in npcm7xx_clk_update_pll()
136 clock_update_hz(s->clock_out, freq); in npcm7xx_clk_update_pll()
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dclk-krait.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
13 #include <asm/krait-l2-accessors.h>
15 #include "clk-krait.h"
23 static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) in __krait_mux_set_sel() argument
30 regval = krait_get_l2_indirect_reg(mux->offset); in __krait_mux_set_sel()
33 if (mux->disable_sec_src_gating) { in __krait_mux_set_sel()
35 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel()
38 regval &= ~(mux->mask << mux->shift); in __krait_mux_set_sel()
39 regval |= (sel & mux->mask) << mux->shift; in __krait_mux_set_sel()
[all …]
/openbmc/linux/drivers/clk/tegra/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
13 #include "clk.h"
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
[all …]
/openbmc/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-afe-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt8186-afe-gpio.c -- Mediatek 8186 afe gpio ctrl
11 #include "mt8186-afe-common.h"
12 #include "mt8186-afe-gpio.h"
113 return -EINVAL; in mt8186_afe_gpio_select()
119 return -EIO; in mt8186_afe_gpio_select()
140 dev_dbg(dev, "%s(), MOSI CLK ON select fail!\n", __func__); in mt8186_afe_gpio_adda_dl()
158 dev_dbg(dev, "%s(), MOSI CLK ON select fail!\n", __func__); in mt8186_afe_gpio_adda_dl()
173 dev_dbg(dev, "%s(), MISO CLK ON select fail!\n", __func__); in mt8186_afe_gpio_adda_ul()
191 dev_dbg(dev, "%s(), MISO CLK OFF select fail!\n", __func__); in mt8186_afe_gpio_adda_ul()
[all …]
/openbmc/qemu/include/hw/misc/
H A Dnpcm7xx_clk.h29 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
31 /* Maximum amount of clock inputs in a SEL module. */
34 /* PLLs in CLK module. */
43 /* SEL/MUX in CLK module. */
57 /* Dividers in CLK module. */
86 * struct NPCM7xxClockPLLState - A PLL module in CLK module.
88 * @clk: The CLK module that owns this module.
97 NPCM7xxCLKState *clk; member
105 * struct NPCM7xxClockSELState - A SEL module in CLK module.
107 * @clk: The CLK module that owns this module.
[all …]
/openbmc/linux/sound/soc/sh/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
33 struct clk *clkin[CLKINMAX];
34 struct clk *clkout[CLKOUTMAX];
35 struct clk *null_clk;
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dov6650.c1 // SPDX-License-Identifier: GPL-2.0-only
15 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
25 #include <linux/clk.h>
29 #include <linux/v4l2-mediabus.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-device.h>
36 #define REG_GAIN 0x00 /* range 00 - 3F */
51 /* [5:0]: Internal Clock Pre-Scaler */
165 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
167 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
[all …]
H A Dmt9m001.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-event.h>
21 #include <media/v4l2-subdev.h>
83 /* Order important - see above */
92 /* exposure/auto-exposure cluster */
99 struct clk *clk; member
181 dev_dbg(&client->dev, "%s\n", __func__); in mt9m001_init()
[all …]
H A Dmt9p031.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com>
12 #include <linux/clk.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-fwnode.h>
31 #include <media/v4l2-subdev.h>
33 #include "aptina-pll.h"
129 struct clk *clk; member
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
380 u8 sel; member
406 const struct stm32mp1_clk_sel *sel; member
424 .sel = (s), \
434 .sel = _UNKNOWN_SEL, \
444 .sel = (s), \
[all …]
/openbmc/linux/include/linux/mfd/
H A Dimx25-tsadc.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 struct clk;
11 struct clk *clk; member
54 _MX25_ADCQ_ITEM((item) - 8, (x)) : _MX25_ADCQ_ITEM((item), (x)))
103 /* ADCQ_CFG (TICR, TCC0-7,GCC0-7) */
107 #define MX25_ADCQ_CFG_NOS(x) (((x) - 1) << 16)
118 #define MX25_ADCQ_CFG_REFP(sel) ((sel) << 7) argument
124 #define MX25_ADCQ_CFG_IN(sel) ((sel) << 4) argument
133 #define MX25_ADCQ_CFG_REFN(sel) ((sel) << 2) argument
/openbmc/linux/drivers/media/platform/qcom/camss/
H A Dcamss-vfe.c1 // SPDX-License-Identifier: GPL-2.0
3 * camss-vfe.c
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
10 #include <linux/clk.h>
20 #include <media/media-entity.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-subdev.h>
24 #include "camss-vfe.h"
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.c18 * This is "two-way" interface, acting as the SHIM layer between driver
20 * to do some preprocessing, then reach PHY. On the PHY->driver direction,
35 struct brcms_info *wl; /* pointer to os-specific private state */
47 physhim->wlc_hw = wlc_hw; in wlc_phy_shim_attach()
48 physhim->wlc = wlc; in wlc_phy_shim_attach()
49 physhim->wl = wl; in wlc_phy_shim_attach()
64 brcms_init_timer(physhim->wl, fn, arg, name); in wlapi_init_timer()
85 brcms_intrson(physhim->wl); in wlapi_intrson()
90 return brcms_intrsoff(physhim->wl); in wlapi_intrsoff()
95 brcms_intrsrestore(physhim->wl, macintmask); in wlapi_intrsrestore()
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci_am654.c1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
8 #include <linux/clk.h>
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-cbus-gpio.txt1 Device tree bindings for i2c-cbus-gpio driver
4 - compatible = "i2c-cbus-gpio";
5 - gpios: clk, dat, sel
6 - #address-cells = <1>;
7 - #size-cells = <0>;
10 - child nodes conforming to i2c bus binding
15 compatible = "i2c-cbus-gpio";
16 gpios = <&gpio 66 0 /* clk */
18 &gpio 64 0 /* sel */
20 #address-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
[all …]
/openbmc/linux/drivers/regulator/
H A Dti-abb-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2012-2013 Texas Instruments, Inc.
12 #include <linux/clk.h>
27 * FAST_OPP: sets ABB LDO to Forward Body-Bias
28 * SLOW_OPP: sets ABB LDO to Reverse Body-Bias
35 * struct ti_abb_info - ABB information per voltage setting
48 * struct ti_abb_reg - Register description for ABB block
51 * @sr2_wtcnt_value_mask: setup register- sr2_wtcnt_value mask
52 * @fbb_sel_mask: setup register- FBB sel mask
53 * @rbb_sel_mask: setup register- RBB sel mask
[all …]

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