11f01091fSAkinobu Mita // SPDX-License-Identifier: GPL-2.0
2f8ce7c35SAkinobu Mita /*
3f8ce7c35SAkinobu Mita * Driver for MT9M001 CMOS Image Sensor from Micron
4f8ce7c35SAkinobu Mita *
5f8ce7c35SAkinobu Mita * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6f8ce7c35SAkinobu Mita */
7f8ce7c35SAkinobu Mita
88fcfc491SAkinobu Mita #include <linux/clk.h>
98fcfc491SAkinobu Mita #include <linux/delay.h>
108fcfc491SAkinobu Mita #include <linux/gpio/consumer.h>
11f8ce7c35SAkinobu Mita #include <linux/i2c.h>
12f8ce7c35SAkinobu Mita #include <linux/log2.h>
13f8ce7c35SAkinobu Mita #include <linux/module.h>
148fcfc491SAkinobu Mita #include <linux/pm_runtime.h>
159f4f37b0SAkinobu Mita #include <linux/slab.h>
169f4f37b0SAkinobu Mita #include <linux/videodev2.h>
17f8ce7c35SAkinobu Mita
18f8ce7c35SAkinobu Mita #include <media/v4l2-ctrls.h>
1974021329SAkinobu Mita #include <media/v4l2-device.h>
20dd15f070SAkinobu Mita #include <media/v4l2-event.h>
219f4f37b0SAkinobu Mita #include <media/v4l2-subdev.h>
22f8ce7c35SAkinobu Mita
23f8ce7c35SAkinobu Mita /*
24f8ce7c35SAkinobu Mita * mt9m001 i2c address 0x5d
25f8ce7c35SAkinobu Mita */
26f8ce7c35SAkinobu Mita
27f8ce7c35SAkinobu Mita /* mt9m001 selected register addresses */
28f8ce7c35SAkinobu Mita #define MT9M001_CHIP_VERSION 0x00
29f8ce7c35SAkinobu Mita #define MT9M001_ROW_START 0x01
30f8ce7c35SAkinobu Mita #define MT9M001_COLUMN_START 0x02
31f8ce7c35SAkinobu Mita #define MT9M001_WINDOW_HEIGHT 0x03
32f8ce7c35SAkinobu Mita #define MT9M001_WINDOW_WIDTH 0x04
33f8ce7c35SAkinobu Mita #define MT9M001_HORIZONTAL_BLANKING 0x05
34f8ce7c35SAkinobu Mita #define MT9M001_VERTICAL_BLANKING 0x06
35f8ce7c35SAkinobu Mita #define MT9M001_OUTPUT_CONTROL 0x07
36f8ce7c35SAkinobu Mita #define MT9M001_SHUTTER_WIDTH 0x09
37f8ce7c35SAkinobu Mita #define MT9M001_FRAME_RESTART 0x0b
38f8ce7c35SAkinobu Mita #define MT9M001_SHUTTER_DELAY 0x0c
39f8ce7c35SAkinobu Mita #define MT9M001_RESET 0x0d
40f8ce7c35SAkinobu Mita #define MT9M001_READ_OPTIONS1 0x1e
41f8ce7c35SAkinobu Mita #define MT9M001_READ_OPTIONS2 0x20
42f8ce7c35SAkinobu Mita #define MT9M001_GLOBAL_GAIN 0x35
43f8ce7c35SAkinobu Mita #define MT9M001_CHIP_ENABLE 0xF1
44f8ce7c35SAkinobu Mita
45f8ce7c35SAkinobu Mita #define MT9M001_MAX_WIDTH 1280
46f8ce7c35SAkinobu Mita #define MT9M001_MAX_HEIGHT 1024
47f8ce7c35SAkinobu Mita #define MT9M001_MIN_WIDTH 48
48f8ce7c35SAkinobu Mita #define MT9M001_MIN_HEIGHT 32
49f8ce7c35SAkinobu Mita #define MT9M001_COLUMN_SKIP 20
50f8ce7c35SAkinobu Mita #define MT9M001_ROW_SKIP 12
51a5826484SAkinobu Mita #define MT9M001_DEFAULT_HBLANK 9
52a5826484SAkinobu Mita #define MT9M001_DEFAULT_VBLANK 25
53f8ce7c35SAkinobu Mita
54f8ce7c35SAkinobu Mita /* MT9M001 has only one fixed colorspace per pixelcode */
55f8ce7c35SAkinobu Mita struct mt9m001_datafmt {
56f8ce7c35SAkinobu Mita u32 code;
57f8ce7c35SAkinobu Mita enum v4l2_colorspace colorspace;
58f8ce7c35SAkinobu Mita };
59f8ce7c35SAkinobu Mita
60f8ce7c35SAkinobu Mita /* Find a data format by a pixel code in an array */
mt9m001_find_datafmt(u32 code,const struct mt9m001_datafmt * fmt,int n)61f8ce7c35SAkinobu Mita static const struct mt9m001_datafmt *mt9m001_find_datafmt(
62f8ce7c35SAkinobu Mita u32 code, const struct mt9m001_datafmt *fmt,
63f8ce7c35SAkinobu Mita int n)
64f8ce7c35SAkinobu Mita {
65f8ce7c35SAkinobu Mita int i;
66f8ce7c35SAkinobu Mita for (i = 0; i < n; i++)
67f8ce7c35SAkinobu Mita if (fmt[i].code == code)
68f8ce7c35SAkinobu Mita return fmt + i;
69f8ce7c35SAkinobu Mita
70f8ce7c35SAkinobu Mita return NULL;
71f8ce7c35SAkinobu Mita }
72f8ce7c35SAkinobu Mita
73f8ce7c35SAkinobu Mita static const struct mt9m001_datafmt mt9m001_colour_fmts[] = {
74f8ce7c35SAkinobu Mita /*
75f8ce7c35SAkinobu Mita * Order important: first natively supported,
76f8ce7c35SAkinobu Mita * second supported with a GPIO extender
77f8ce7c35SAkinobu Mita */
78f8ce7c35SAkinobu Mita {MEDIA_BUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
79f8ce7c35SAkinobu Mita {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
80f8ce7c35SAkinobu Mita };
81f8ce7c35SAkinobu Mita
82f8ce7c35SAkinobu Mita static const struct mt9m001_datafmt mt9m001_monochrome_fmts[] = {
83f8ce7c35SAkinobu Mita /* Order important - see above */
84f8ce7c35SAkinobu Mita {MEDIA_BUS_FMT_Y10_1X10, V4L2_COLORSPACE_JPEG},
85f8ce7c35SAkinobu Mita {MEDIA_BUS_FMT_Y8_1X8, V4L2_COLORSPACE_JPEG},
86f8ce7c35SAkinobu Mita };
87f8ce7c35SAkinobu Mita
88f8ce7c35SAkinobu Mita struct mt9m001 {
89f8ce7c35SAkinobu Mita struct v4l2_subdev subdev;
90f8ce7c35SAkinobu Mita struct v4l2_ctrl_handler hdl;
91f8ce7c35SAkinobu Mita struct {
92f8ce7c35SAkinobu Mita /* exposure/auto-exposure cluster */
93f8ce7c35SAkinobu Mita struct v4l2_ctrl *autoexposure;
94f8ce7c35SAkinobu Mita struct v4l2_ctrl *exposure;
95f8ce7c35SAkinobu Mita };
968fcfc491SAkinobu Mita bool streaming;
978fcfc491SAkinobu Mita struct mutex mutex;
98f8ce7c35SAkinobu Mita struct v4l2_rect rect; /* Sensor window */
998fcfc491SAkinobu Mita struct clk *clk;
1008fcfc491SAkinobu Mita struct gpio_desc *standby_gpio;
1018fcfc491SAkinobu Mita struct gpio_desc *reset_gpio;
102f8ce7c35SAkinobu Mita const struct mt9m001_datafmt *fmt;
103f8ce7c35SAkinobu Mita const struct mt9m001_datafmt *fmts;
104f8ce7c35SAkinobu Mita int num_fmts;
105f8ce7c35SAkinobu Mita unsigned int total_h;
106f8ce7c35SAkinobu Mita unsigned short y_skip_top; /* Lines to skip at the top */
10712d85c3eSAkinobu Mita struct media_pad pad;
108f8ce7c35SAkinobu Mita };
109f8ce7c35SAkinobu Mita
to_mt9m001(const struct i2c_client * client)110f8ce7c35SAkinobu Mita static struct mt9m001 *to_mt9m001(const struct i2c_client *client)
111f8ce7c35SAkinobu Mita {
112f8ce7c35SAkinobu Mita return container_of(i2c_get_clientdata(client), struct mt9m001, subdev);
113f8ce7c35SAkinobu Mita }
114f8ce7c35SAkinobu Mita
reg_read(struct i2c_client * client,const u8 reg)115f8ce7c35SAkinobu Mita static int reg_read(struct i2c_client *client, const u8 reg)
116f8ce7c35SAkinobu Mita {
117f8ce7c35SAkinobu Mita return i2c_smbus_read_word_swapped(client, reg);
118f8ce7c35SAkinobu Mita }
119f8ce7c35SAkinobu Mita
reg_write(struct i2c_client * client,const u8 reg,const u16 data)120f8ce7c35SAkinobu Mita static int reg_write(struct i2c_client *client, const u8 reg,
121f8ce7c35SAkinobu Mita const u16 data)
122f8ce7c35SAkinobu Mita {
123f8ce7c35SAkinobu Mita return i2c_smbus_write_word_swapped(client, reg, data);
124f8ce7c35SAkinobu Mita }
125f8ce7c35SAkinobu Mita
reg_set(struct i2c_client * client,const u8 reg,const u16 data)126f8ce7c35SAkinobu Mita static int reg_set(struct i2c_client *client, const u8 reg,
127f8ce7c35SAkinobu Mita const u16 data)
128f8ce7c35SAkinobu Mita {
129f8ce7c35SAkinobu Mita int ret;
130f8ce7c35SAkinobu Mita
131f8ce7c35SAkinobu Mita ret = reg_read(client, reg);
132f8ce7c35SAkinobu Mita if (ret < 0)
133f8ce7c35SAkinobu Mita return ret;
134f8ce7c35SAkinobu Mita return reg_write(client, reg, ret | data);
135f8ce7c35SAkinobu Mita }
136f8ce7c35SAkinobu Mita
reg_clear(struct i2c_client * client,const u8 reg,const u16 data)137f8ce7c35SAkinobu Mita static int reg_clear(struct i2c_client *client, const u8 reg,
138f8ce7c35SAkinobu Mita const u16 data)
139f8ce7c35SAkinobu Mita {
140f8ce7c35SAkinobu Mita int ret;
141f8ce7c35SAkinobu Mita
142f8ce7c35SAkinobu Mita ret = reg_read(client, reg);
143f8ce7c35SAkinobu Mita if (ret < 0)
144f8ce7c35SAkinobu Mita return ret;
145f8ce7c35SAkinobu Mita return reg_write(client, reg, ret & ~data);
146f8ce7c35SAkinobu Mita }
147f8ce7c35SAkinobu Mita
148a5826484SAkinobu Mita struct mt9m001_reg {
149a5826484SAkinobu Mita u8 reg;
150a5826484SAkinobu Mita u16 data;
151a5826484SAkinobu Mita };
152a5826484SAkinobu Mita
multi_reg_write(struct i2c_client * client,const struct mt9m001_reg * regs,int num)153a5826484SAkinobu Mita static int multi_reg_write(struct i2c_client *client,
154a5826484SAkinobu Mita const struct mt9m001_reg *regs, int num)
155a5826484SAkinobu Mita {
156a5826484SAkinobu Mita int i;
157a5826484SAkinobu Mita
158a5826484SAkinobu Mita for (i = 0; i < num; i++) {
159a5826484SAkinobu Mita int ret = reg_write(client, regs[i].reg, regs[i].data);
160a5826484SAkinobu Mita
161a5826484SAkinobu Mita if (ret)
162a5826484SAkinobu Mita return ret;
163a5826484SAkinobu Mita }
164a5826484SAkinobu Mita
165a5826484SAkinobu Mita return 0;
166a5826484SAkinobu Mita }
167a5826484SAkinobu Mita
mt9m001_init(struct i2c_client * client)168f8ce7c35SAkinobu Mita static int mt9m001_init(struct i2c_client *client)
169f8ce7c35SAkinobu Mita {
17036909b55SColin Ian King static const struct mt9m001_reg init_regs[] = {
171a5826484SAkinobu Mita /*
172a5826484SAkinobu Mita * Issue a soft reset. This returns all registers to their
173a5826484SAkinobu Mita * default values.
174a5826484SAkinobu Mita */
175a5826484SAkinobu Mita { MT9M001_RESET, 1 },
176a5826484SAkinobu Mita { MT9M001_RESET, 0 },
177a5826484SAkinobu Mita /* Disable chip, synchronous option update */
178a5826484SAkinobu Mita { MT9M001_OUTPUT_CONTROL, 0 }
179a5826484SAkinobu Mita };
180f8ce7c35SAkinobu Mita
181f8ce7c35SAkinobu Mita dev_dbg(&client->dev, "%s\n", __func__);
182f8ce7c35SAkinobu Mita
183a5826484SAkinobu Mita return multi_reg_write(client, init_regs, ARRAY_SIZE(init_regs));
184a5826484SAkinobu Mita }
185a5826484SAkinobu Mita
mt9m001_apply_selection(struct v4l2_subdev * sd)1868fcfc491SAkinobu Mita static int mt9m001_apply_selection(struct v4l2_subdev *sd)
187a5826484SAkinobu Mita {
188a5826484SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
189a5826484SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
190a5826484SAkinobu Mita const struct mt9m001_reg regs[] = {
191a5826484SAkinobu Mita /* Blanking and start values - default... */
192a5826484SAkinobu Mita { MT9M001_HORIZONTAL_BLANKING, MT9M001_DEFAULT_HBLANK },
193a5826484SAkinobu Mita { MT9M001_VERTICAL_BLANKING, MT9M001_DEFAULT_VBLANK },
194f8ce7c35SAkinobu Mita /*
195a5826484SAkinobu Mita * The caller provides a supported format, as verified per
196a5826484SAkinobu Mita * call to .set_fmt(FORMAT_TRY).
197f8ce7c35SAkinobu Mita */
1988fcfc491SAkinobu Mita { MT9M001_COLUMN_START, mt9m001->rect.left },
1998fcfc491SAkinobu Mita { MT9M001_ROW_START, mt9m001->rect.top },
2008fcfc491SAkinobu Mita { MT9M001_WINDOW_WIDTH, mt9m001->rect.width - 1 },
201a5826484SAkinobu Mita { MT9M001_WINDOW_HEIGHT,
2028fcfc491SAkinobu Mita mt9m001->rect.height + mt9m001->y_skip_top - 1 },
203a5826484SAkinobu Mita };
204f8ce7c35SAkinobu Mita
205a5826484SAkinobu Mita return multi_reg_write(client, regs, ARRAY_SIZE(regs));
206f8ce7c35SAkinobu Mita }
207f8ce7c35SAkinobu Mita
mt9m001_s_stream(struct v4l2_subdev * sd,int enable)208f8ce7c35SAkinobu Mita static int mt9m001_s_stream(struct v4l2_subdev *sd, int enable)
209f8ce7c35SAkinobu Mita {
210f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
2118fcfc491SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
2128fcfc491SAkinobu Mita int ret = 0;
213f8ce7c35SAkinobu Mita
2148fcfc491SAkinobu Mita mutex_lock(&mt9m001->mutex);
2158fcfc491SAkinobu Mita
2168fcfc491SAkinobu Mita if (mt9m001->streaming == enable)
2178fcfc491SAkinobu Mita goto done;
2188fcfc491SAkinobu Mita
2198fcfc491SAkinobu Mita if (enable) {
220e7c018a9SMauro Carvalho Chehab ret = pm_runtime_resume_and_get(&client->dev);
2218fcfc491SAkinobu Mita if (ret < 0)
222e7c018a9SMauro Carvalho Chehab goto unlock;
2238fcfc491SAkinobu Mita
2248fcfc491SAkinobu Mita ret = mt9m001_apply_selection(sd);
2258fcfc491SAkinobu Mita if (ret)
2268fcfc491SAkinobu Mita goto put_unlock;
2278fcfc491SAkinobu Mita
2288fcfc491SAkinobu Mita ret = __v4l2_ctrl_handler_setup(&mt9m001->hdl);
2298fcfc491SAkinobu Mita if (ret)
2308fcfc491SAkinobu Mita goto put_unlock;
2318fcfc491SAkinobu Mita
2328fcfc491SAkinobu Mita /* Switch to master "normal" mode */
2338fcfc491SAkinobu Mita ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 2);
2348fcfc491SAkinobu Mita if (ret < 0)
2358fcfc491SAkinobu Mita goto put_unlock;
2368fcfc491SAkinobu Mita } else {
2378fcfc491SAkinobu Mita /* Switch to master stop sensor readout */
2388fcfc491SAkinobu Mita reg_write(client, MT9M001_OUTPUT_CONTROL, 0);
2398fcfc491SAkinobu Mita pm_runtime_put(&client->dev);
2408fcfc491SAkinobu Mita }
2418fcfc491SAkinobu Mita
2428fcfc491SAkinobu Mita mt9m001->streaming = enable;
2438fcfc491SAkinobu Mita done:
2448fcfc491SAkinobu Mita mutex_unlock(&mt9m001->mutex);
2458fcfc491SAkinobu Mita
246f8ce7c35SAkinobu Mita return 0;
2478fcfc491SAkinobu Mita
2488fcfc491SAkinobu Mita put_unlock:
2498fcfc491SAkinobu Mita pm_runtime_put(&client->dev);
250e7c018a9SMauro Carvalho Chehab unlock:
2518fcfc491SAkinobu Mita mutex_unlock(&mt9m001->mutex);
2528fcfc491SAkinobu Mita
2538fcfc491SAkinobu Mita return ret;
254f8ce7c35SAkinobu Mita }
255f8ce7c35SAkinobu Mita
mt9m001_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)256f8ce7c35SAkinobu Mita static int mt9m001_set_selection(struct v4l2_subdev *sd,
2570d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
258f8ce7c35SAkinobu Mita struct v4l2_subdev_selection *sel)
259f8ce7c35SAkinobu Mita {
260f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
261f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
262f8ce7c35SAkinobu Mita struct v4l2_rect rect = sel->r;
263f8ce7c35SAkinobu Mita
264f8ce7c35SAkinobu Mita if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
265f8ce7c35SAkinobu Mita sel->target != V4L2_SEL_TGT_CROP)
266f8ce7c35SAkinobu Mita return -EINVAL;
267f8ce7c35SAkinobu Mita
268f8ce7c35SAkinobu Mita if (mt9m001->fmts == mt9m001_colour_fmts)
269f8ce7c35SAkinobu Mita /*
270f8ce7c35SAkinobu Mita * Bayer format - even number of rows for simplicity,
271f8ce7c35SAkinobu Mita * but let the user play with the top row.
272f8ce7c35SAkinobu Mita */
273f8ce7c35SAkinobu Mita rect.height = ALIGN(rect.height, 2);
274f8ce7c35SAkinobu Mita
275f8ce7c35SAkinobu Mita /* Datasheet requirement: see register description */
276f8ce7c35SAkinobu Mita rect.width = ALIGN(rect.width, 2);
277f8ce7c35SAkinobu Mita rect.left = ALIGN(rect.left, 2);
278f8ce7c35SAkinobu Mita
27974021329SAkinobu Mita rect.width = clamp_t(u32, rect.width, MT9M001_MIN_WIDTH,
28074021329SAkinobu Mita MT9M001_MAX_WIDTH);
28174021329SAkinobu Mita rect.left = clamp_t(u32, rect.left, MT9M001_COLUMN_SKIP,
28274021329SAkinobu Mita MT9M001_COLUMN_SKIP + MT9M001_MAX_WIDTH - rect.width);
283f8ce7c35SAkinobu Mita
28474021329SAkinobu Mita rect.height = clamp_t(u32, rect.height, MT9M001_MIN_HEIGHT,
28574021329SAkinobu Mita MT9M001_MAX_HEIGHT);
28674021329SAkinobu Mita rect.top = clamp_t(u32, rect.top, MT9M001_ROW_SKIP,
28774021329SAkinobu Mita MT9M001_ROW_SKIP + MT9M001_MAX_HEIGHT - rect.height);
288f8ce7c35SAkinobu Mita
289a5826484SAkinobu Mita mt9m001->total_h = rect.height + mt9m001->y_skip_top +
290a5826484SAkinobu Mita MT9M001_DEFAULT_VBLANK;
291f8ce7c35SAkinobu Mita
292f8ce7c35SAkinobu Mita mt9m001->rect = rect;
293f8ce7c35SAkinobu Mita
2948fcfc491SAkinobu Mita return 0;
295f8ce7c35SAkinobu Mita }
296f8ce7c35SAkinobu Mita
mt9m001_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)297f8ce7c35SAkinobu Mita static int mt9m001_get_selection(struct v4l2_subdev *sd,
2980d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
299f8ce7c35SAkinobu Mita struct v4l2_subdev_selection *sel)
300f8ce7c35SAkinobu Mita {
301f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
302f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
303f8ce7c35SAkinobu Mita
304f8ce7c35SAkinobu Mita if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
305f8ce7c35SAkinobu Mita return -EINVAL;
306f8ce7c35SAkinobu Mita
307f8ce7c35SAkinobu Mita switch (sel->target) {
308f8ce7c35SAkinobu Mita case V4L2_SEL_TGT_CROP_BOUNDS:
309f8ce7c35SAkinobu Mita sel->r.left = MT9M001_COLUMN_SKIP;
310f8ce7c35SAkinobu Mita sel->r.top = MT9M001_ROW_SKIP;
311f8ce7c35SAkinobu Mita sel->r.width = MT9M001_MAX_WIDTH;
312f8ce7c35SAkinobu Mita sel->r.height = MT9M001_MAX_HEIGHT;
313f8ce7c35SAkinobu Mita return 0;
314f8ce7c35SAkinobu Mita case V4L2_SEL_TGT_CROP:
315f8ce7c35SAkinobu Mita sel->r = mt9m001->rect;
316f8ce7c35SAkinobu Mita return 0;
317f8ce7c35SAkinobu Mita default:
318f8ce7c35SAkinobu Mita return -EINVAL;
319f8ce7c35SAkinobu Mita }
320f8ce7c35SAkinobu Mita }
321f8ce7c35SAkinobu Mita
mt9m001_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)322f8ce7c35SAkinobu Mita static int mt9m001_get_fmt(struct v4l2_subdev *sd,
3230d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
324f8ce7c35SAkinobu Mita struct v4l2_subdev_format *format)
325f8ce7c35SAkinobu Mita {
326f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
327f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
328f8ce7c35SAkinobu Mita struct v4l2_mbus_framefmt *mf = &format->format;
329f8ce7c35SAkinobu Mita
330f8ce7c35SAkinobu Mita if (format->pad)
331f8ce7c35SAkinobu Mita return -EINVAL;
332f8ce7c35SAkinobu Mita
33371f247daSAkinobu Mita if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
3340d346d2aSTomi Valkeinen mf = v4l2_subdev_get_try_format(sd, sd_state, 0);
33571f247daSAkinobu Mita format->format = *mf;
33671f247daSAkinobu Mita return 0;
33771f247daSAkinobu Mita }
33871f247daSAkinobu Mita
339f8ce7c35SAkinobu Mita mf->width = mt9m001->rect.width;
340f8ce7c35SAkinobu Mita mf->height = mt9m001->rect.height;
341f8ce7c35SAkinobu Mita mf->code = mt9m001->fmt->code;
342f8ce7c35SAkinobu Mita mf->colorspace = mt9m001->fmt->colorspace;
343f8ce7c35SAkinobu Mita mf->field = V4L2_FIELD_NONE;
344772f63c0SAkinobu Mita mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
345772f63c0SAkinobu Mita mf->quantization = V4L2_QUANTIZATION_DEFAULT;
346772f63c0SAkinobu Mita mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
347f8ce7c35SAkinobu Mita
348f8ce7c35SAkinobu Mita return 0;
349f8ce7c35SAkinobu Mita }
350f8ce7c35SAkinobu Mita
mt9m001_s_fmt(struct v4l2_subdev * sd,const struct mt9m001_datafmt * fmt,struct v4l2_mbus_framefmt * mf)351f8ce7c35SAkinobu Mita static int mt9m001_s_fmt(struct v4l2_subdev *sd,
352f8ce7c35SAkinobu Mita const struct mt9m001_datafmt *fmt,
353f8ce7c35SAkinobu Mita struct v4l2_mbus_framefmt *mf)
354f8ce7c35SAkinobu Mita {
355f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
356f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
357f8ce7c35SAkinobu Mita struct v4l2_subdev_selection sel = {
358f8ce7c35SAkinobu Mita .which = V4L2_SUBDEV_FORMAT_ACTIVE,
359f8ce7c35SAkinobu Mita .target = V4L2_SEL_TGT_CROP,
360f8ce7c35SAkinobu Mita .r.left = mt9m001->rect.left,
361f8ce7c35SAkinobu Mita .r.top = mt9m001->rect.top,
362f8ce7c35SAkinobu Mita .r.width = mf->width,
363f8ce7c35SAkinobu Mita .r.height = mf->height,
364f8ce7c35SAkinobu Mita };
365f8ce7c35SAkinobu Mita int ret;
366f8ce7c35SAkinobu Mita
367f8ce7c35SAkinobu Mita /* No support for scaling so far, just crop. TODO: use skipping */
368f8ce7c35SAkinobu Mita ret = mt9m001_set_selection(sd, NULL, &sel);
369f8ce7c35SAkinobu Mita if (!ret) {
370f8ce7c35SAkinobu Mita mf->width = mt9m001->rect.width;
371f8ce7c35SAkinobu Mita mf->height = mt9m001->rect.height;
372f8ce7c35SAkinobu Mita mt9m001->fmt = fmt;
373f8ce7c35SAkinobu Mita mf->colorspace = fmt->colorspace;
374f8ce7c35SAkinobu Mita }
375f8ce7c35SAkinobu Mita
376f8ce7c35SAkinobu Mita return ret;
377f8ce7c35SAkinobu Mita }
378f8ce7c35SAkinobu Mita
mt9m001_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)379f8ce7c35SAkinobu Mita static int mt9m001_set_fmt(struct v4l2_subdev *sd,
3800d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
381f8ce7c35SAkinobu Mita struct v4l2_subdev_format *format)
382f8ce7c35SAkinobu Mita {
383f8ce7c35SAkinobu Mita struct v4l2_mbus_framefmt *mf = &format->format;
384f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
385f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
386f8ce7c35SAkinobu Mita const struct mt9m001_datafmt *fmt;
387f8ce7c35SAkinobu Mita
388f8ce7c35SAkinobu Mita if (format->pad)
389f8ce7c35SAkinobu Mita return -EINVAL;
390f8ce7c35SAkinobu Mita
391f8ce7c35SAkinobu Mita v4l_bound_align_image(&mf->width, MT9M001_MIN_WIDTH,
392f8ce7c35SAkinobu Mita MT9M001_MAX_WIDTH, 1,
393f8ce7c35SAkinobu Mita &mf->height, MT9M001_MIN_HEIGHT + mt9m001->y_skip_top,
394f8ce7c35SAkinobu Mita MT9M001_MAX_HEIGHT + mt9m001->y_skip_top, 0, 0);
395f8ce7c35SAkinobu Mita
396f8ce7c35SAkinobu Mita if (mt9m001->fmts == mt9m001_colour_fmts)
397f8ce7c35SAkinobu Mita mf->height = ALIGN(mf->height - 1, 2);
398f8ce7c35SAkinobu Mita
399f8ce7c35SAkinobu Mita fmt = mt9m001_find_datafmt(mf->code, mt9m001->fmts,
400f8ce7c35SAkinobu Mita mt9m001->num_fmts);
401f8ce7c35SAkinobu Mita if (!fmt) {
402f8ce7c35SAkinobu Mita fmt = mt9m001->fmt;
403f8ce7c35SAkinobu Mita mf->code = fmt->code;
404f8ce7c35SAkinobu Mita }
405f8ce7c35SAkinobu Mita
406f8ce7c35SAkinobu Mita mf->colorspace = fmt->colorspace;
407772f63c0SAkinobu Mita mf->field = V4L2_FIELD_NONE;
408772f63c0SAkinobu Mita mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
409772f63c0SAkinobu Mita mf->quantization = V4L2_QUANTIZATION_DEFAULT;
410772f63c0SAkinobu Mita mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
411f8ce7c35SAkinobu Mita
412f8ce7c35SAkinobu Mita if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
413f8ce7c35SAkinobu Mita return mt9m001_s_fmt(sd, fmt, mf);
4140d346d2aSTomi Valkeinen sd_state->pads->try_fmt = *mf;
415f8ce7c35SAkinobu Mita return 0;
416f8ce7c35SAkinobu Mita }
417f8ce7c35SAkinobu Mita
418f8ce7c35SAkinobu Mita #ifdef CONFIG_VIDEO_ADV_DEBUG
mt9m001_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)419f8ce7c35SAkinobu Mita static int mt9m001_g_register(struct v4l2_subdev *sd,
420f8ce7c35SAkinobu Mita struct v4l2_dbg_register *reg)
421f8ce7c35SAkinobu Mita {
422f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
423f8ce7c35SAkinobu Mita
424f8ce7c35SAkinobu Mita if (reg->reg > 0xff)
425f8ce7c35SAkinobu Mita return -EINVAL;
426f8ce7c35SAkinobu Mita
427f8ce7c35SAkinobu Mita reg->size = 2;
428f8ce7c35SAkinobu Mita reg->val = reg_read(client, reg->reg);
429f8ce7c35SAkinobu Mita
430f8ce7c35SAkinobu Mita if (reg->val > 0xffff)
431f8ce7c35SAkinobu Mita return -EIO;
432f8ce7c35SAkinobu Mita
433f8ce7c35SAkinobu Mita return 0;
434f8ce7c35SAkinobu Mita }
435f8ce7c35SAkinobu Mita
mt9m001_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)436f8ce7c35SAkinobu Mita static int mt9m001_s_register(struct v4l2_subdev *sd,
437f8ce7c35SAkinobu Mita const struct v4l2_dbg_register *reg)
438f8ce7c35SAkinobu Mita {
439f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
440f8ce7c35SAkinobu Mita
441f8ce7c35SAkinobu Mita if (reg->reg > 0xff)
442f8ce7c35SAkinobu Mita return -EINVAL;
443f8ce7c35SAkinobu Mita
444f8ce7c35SAkinobu Mita if (reg_write(client, reg->reg, reg->val) < 0)
445f8ce7c35SAkinobu Mita return -EIO;
446f8ce7c35SAkinobu Mita
447f8ce7c35SAkinobu Mita return 0;
448f8ce7c35SAkinobu Mita }
449f8ce7c35SAkinobu Mita #endif
450f8ce7c35SAkinobu Mita
mt9m001_power_on(struct device * dev)4518fcfc491SAkinobu Mita static int mt9m001_power_on(struct device *dev)
452f8ce7c35SAkinobu Mita {
4538fcfc491SAkinobu Mita struct i2c_client *client = to_i2c_client(dev);
4548fcfc491SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
4558fcfc491SAkinobu Mita int ret;
4568fcfc491SAkinobu Mita
4578fcfc491SAkinobu Mita ret = clk_prepare_enable(mt9m001->clk);
4588fcfc491SAkinobu Mita if (ret)
4598fcfc491SAkinobu Mita return ret;
4608fcfc491SAkinobu Mita
4618fcfc491SAkinobu Mita if (mt9m001->standby_gpio) {
4628fcfc491SAkinobu Mita gpiod_set_value_cansleep(mt9m001->standby_gpio, 0);
4638fcfc491SAkinobu Mita usleep_range(1000, 2000);
4648fcfc491SAkinobu Mita }
4658fcfc491SAkinobu Mita
4668fcfc491SAkinobu Mita if (mt9m001->reset_gpio) {
4678fcfc491SAkinobu Mita gpiod_set_value_cansleep(mt9m001->reset_gpio, 1);
4688fcfc491SAkinobu Mita usleep_range(1000, 2000);
4698fcfc491SAkinobu Mita gpiod_set_value_cansleep(mt9m001->reset_gpio, 0);
4708fcfc491SAkinobu Mita usleep_range(1000, 2000);
4718fcfc491SAkinobu Mita }
4728fcfc491SAkinobu Mita
4738fcfc491SAkinobu Mita return 0;
4748fcfc491SAkinobu Mita }
4758fcfc491SAkinobu Mita
mt9m001_power_off(struct device * dev)4768fcfc491SAkinobu Mita static int mt9m001_power_off(struct device *dev)
4778fcfc491SAkinobu Mita {
4788fcfc491SAkinobu Mita struct i2c_client *client = to_i2c_client(dev);
479f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
480f8ce7c35SAkinobu Mita
4818fcfc491SAkinobu Mita gpiod_set_value_cansleep(mt9m001->standby_gpio, 1);
4828fcfc491SAkinobu Mita clk_disable_unprepare(mt9m001->clk);
4838fcfc491SAkinobu Mita
4848fcfc491SAkinobu Mita return 0;
485f8ce7c35SAkinobu Mita }
486f8ce7c35SAkinobu Mita
mt9m001_g_volatile_ctrl(struct v4l2_ctrl * ctrl)487f8ce7c35SAkinobu Mita static int mt9m001_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
488f8ce7c35SAkinobu Mita {
489f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = container_of(ctrl->handler,
490f8ce7c35SAkinobu Mita struct mt9m001, hdl);
491f8ce7c35SAkinobu Mita s32 min, max;
492f8ce7c35SAkinobu Mita
493f8ce7c35SAkinobu Mita switch (ctrl->id) {
494f8ce7c35SAkinobu Mita case V4L2_CID_EXPOSURE_AUTO:
495f8ce7c35SAkinobu Mita min = mt9m001->exposure->minimum;
496f8ce7c35SAkinobu Mita max = mt9m001->exposure->maximum;
497f8ce7c35SAkinobu Mita mt9m001->exposure->val =
498f8ce7c35SAkinobu Mita (524 + (mt9m001->total_h - 1) * (max - min)) / 1048 + min;
499f8ce7c35SAkinobu Mita break;
500f8ce7c35SAkinobu Mita }
501f8ce7c35SAkinobu Mita return 0;
502f8ce7c35SAkinobu Mita }
503f8ce7c35SAkinobu Mita
mt9m001_s_ctrl(struct v4l2_ctrl * ctrl)504f8ce7c35SAkinobu Mita static int mt9m001_s_ctrl(struct v4l2_ctrl *ctrl)
505f8ce7c35SAkinobu Mita {
506f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = container_of(ctrl->handler,
507f8ce7c35SAkinobu Mita struct mt9m001, hdl);
508f8ce7c35SAkinobu Mita struct v4l2_subdev *sd = &mt9m001->subdev;
509f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
510f8ce7c35SAkinobu Mita struct v4l2_ctrl *exp = mt9m001->exposure;
511f8ce7c35SAkinobu Mita int data;
5128fcfc491SAkinobu Mita int ret;
5138fcfc491SAkinobu Mita
5148fcfc491SAkinobu Mita if (!pm_runtime_get_if_in_use(&client->dev))
5158fcfc491SAkinobu Mita return 0;
516f8ce7c35SAkinobu Mita
517f8ce7c35SAkinobu Mita switch (ctrl->id) {
518f8ce7c35SAkinobu Mita case V4L2_CID_VFLIP:
519f8ce7c35SAkinobu Mita if (ctrl->val)
5208fcfc491SAkinobu Mita ret = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000);
521f8ce7c35SAkinobu Mita else
5228fcfc491SAkinobu Mita ret = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000);
5238fcfc491SAkinobu Mita break;
524f8ce7c35SAkinobu Mita
525f8ce7c35SAkinobu Mita case V4L2_CID_GAIN:
526f8ce7c35SAkinobu Mita /* See Datasheet Table 7, Gain settings. */
527f8ce7c35SAkinobu Mita if (ctrl->val <= ctrl->default_value) {
528f8ce7c35SAkinobu Mita /* Pack it into 0..1 step 0.125, register values 0..8 */
529f8ce7c35SAkinobu Mita unsigned long range = ctrl->default_value - ctrl->minimum;
530f8ce7c35SAkinobu Mita data = ((ctrl->val - (s32)ctrl->minimum) * 8 + range / 2) / range;
531f8ce7c35SAkinobu Mita
532f8ce7c35SAkinobu Mita dev_dbg(&client->dev, "Setting gain %d\n", data);
5338fcfc491SAkinobu Mita ret = reg_write(client, MT9M001_GLOBAL_GAIN, data);
534f8ce7c35SAkinobu Mita } else {
535f8ce7c35SAkinobu Mita /* Pack it into 1.125..15 variable step, register values 9..67 */
536f8ce7c35SAkinobu Mita /* We assume qctrl->maximum - qctrl->default_value - 1 > 0 */
537f8ce7c35SAkinobu Mita unsigned long range = ctrl->maximum - ctrl->default_value - 1;
538f8ce7c35SAkinobu Mita unsigned long gain = ((ctrl->val - (s32)ctrl->default_value - 1) *
539f8ce7c35SAkinobu Mita 111 + range / 2) / range + 9;
540f8ce7c35SAkinobu Mita
541f8ce7c35SAkinobu Mita if (gain <= 32)
542f8ce7c35SAkinobu Mita data = gain;
543f8ce7c35SAkinobu Mita else if (gain <= 64)
544f8ce7c35SAkinobu Mita data = ((gain - 32) * 16 + 16) / 32 + 80;
545f8ce7c35SAkinobu Mita else
546f8ce7c35SAkinobu Mita data = ((gain - 64) * 7 + 28) / 56 + 96;
547f8ce7c35SAkinobu Mita
548f8ce7c35SAkinobu Mita dev_dbg(&client->dev, "Setting gain from %d to %d\n",
549f8ce7c35SAkinobu Mita reg_read(client, MT9M001_GLOBAL_GAIN), data);
5508fcfc491SAkinobu Mita ret = reg_write(client, MT9M001_GLOBAL_GAIN, data);
551f8ce7c35SAkinobu Mita }
5528fcfc491SAkinobu Mita break;
553f8ce7c35SAkinobu Mita
554f8ce7c35SAkinobu Mita case V4L2_CID_EXPOSURE_AUTO:
555f8ce7c35SAkinobu Mita if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
556f8ce7c35SAkinobu Mita unsigned long range = exp->maximum - exp->minimum;
557f8ce7c35SAkinobu Mita unsigned long shutter = ((exp->val - (s32)exp->minimum) * 1048 +
558f8ce7c35SAkinobu Mita range / 2) / range + 1;
559f8ce7c35SAkinobu Mita
560f8ce7c35SAkinobu Mita dev_dbg(&client->dev,
561f8ce7c35SAkinobu Mita "Setting shutter width from %d to %lu\n",
562f8ce7c35SAkinobu Mita reg_read(client, MT9M001_SHUTTER_WIDTH), shutter);
5638fcfc491SAkinobu Mita ret = reg_write(client, MT9M001_SHUTTER_WIDTH, shutter);
564f8ce7c35SAkinobu Mita } else {
565f8ce7c35SAkinobu Mita mt9m001->total_h = mt9m001->rect.height +
5668fcfc491SAkinobu Mita mt9m001->y_skip_top + MT9M001_DEFAULT_VBLANK;
5678fcfc491SAkinobu Mita ret = reg_write(client, MT9M001_SHUTTER_WIDTH,
5688fcfc491SAkinobu Mita mt9m001->total_h);
569f8ce7c35SAkinobu Mita }
5708fcfc491SAkinobu Mita break;
5718fcfc491SAkinobu Mita default:
5728fcfc491SAkinobu Mita ret = -EINVAL;
5738fcfc491SAkinobu Mita break;
574f8ce7c35SAkinobu Mita }
5758fcfc491SAkinobu Mita
5768fcfc491SAkinobu Mita pm_runtime_put(&client->dev);
5778fcfc491SAkinobu Mita
5788fcfc491SAkinobu Mita return ret;
579f8ce7c35SAkinobu Mita }
580f8ce7c35SAkinobu Mita
581f8ce7c35SAkinobu Mita /*
582f8ce7c35SAkinobu Mita * Interface active, can use i2c. If it fails, it can indeed mean, that
583f8ce7c35SAkinobu Mita * this wasn't our capture interface, so, we wait for the right one
584f8ce7c35SAkinobu Mita */
mt9m001_video_probe(struct i2c_client * client)58574021329SAkinobu Mita static int mt9m001_video_probe(struct i2c_client *client)
586f8ce7c35SAkinobu Mita {
587f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
588f8ce7c35SAkinobu Mita s32 data;
589f8ce7c35SAkinobu Mita int ret;
590f8ce7c35SAkinobu Mita
591f8ce7c35SAkinobu Mita /* Enable the chip */
592f8ce7c35SAkinobu Mita data = reg_write(client, MT9M001_CHIP_ENABLE, 1);
593f8ce7c35SAkinobu Mita dev_dbg(&client->dev, "write: %d\n", data);
594f8ce7c35SAkinobu Mita
595f8ce7c35SAkinobu Mita /* Read out the chip version register */
596f8ce7c35SAkinobu Mita data = reg_read(client, MT9M001_CHIP_VERSION);
597f8ce7c35SAkinobu Mita
598f8ce7c35SAkinobu Mita /* must be 0x8411 or 0x8421 for colour sensor and 8431 for bw */
599f8ce7c35SAkinobu Mita switch (data) {
600f8ce7c35SAkinobu Mita case 0x8411:
601f8ce7c35SAkinobu Mita case 0x8421:
602f8ce7c35SAkinobu Mita mt9m001->fmts = mt9m001_colour_fmts;
60374021329SAkinobu Mita mt9m001->num_fmts = ARRAY_SIZE(mt9m001_colour_fmts);
604f8ce7c35SAkinobu Mita break;
605f8ce7c35SAkinobu Mita case 0x8431:
606f8ce7c35SAkinobu Mita mt9m001->fmts = mt9m001_monochrome_fmts;
60774021329SAkinobu Mita mt9m001->num_fmts = ARRAY_SIZE(mt9m001_monochrome_fmts);
608f8ce7c35SAkinobu Mita break;
609f8ce7c35SAkinobu Mita default:
610f8ce7c35SAkinobu Mita dev_err(&client->dev,
611f8ce7c35SAkinobu Mita "No MT9M001 chip detected, register read %x\n", data);
612f8ce7c35SAkinobu Mita ret = -ENODEV;
613f8ce7c35SAkinobu Mita goto done;
614f8ce7c35SAkinobu Mita }
615f8ce7c35SAkinobu Mita
616f8ce7c35SAkinobu Mita mt9m001->fmt = &mt9m001->fmts[0];
617f8ce7c35SAkinobu Mita
618f8ce7c35SAkinobu Mita dev_info(&client->dev, "Detected a MT9M001 chip ID %x (%s)\n", data,
619f8ce7c35SAkinobu Mita data == 0x8431 ? "C12STM" : "C12ST");
620f8ce7c35SAkinobu Mita
621f8ce7c35SAkinobu Mita ret = mt9m001_init(client);
622f8ce7c35SAkinobu Mita if (ret < 0) {
623f8ce7c35SAkinobu Mita dev_err(&client->dev, "Failed to initialise the camera\n");
624f8ce7c35SAkinobu Mita goto done;
625f8ce7c35SAkinobu Mita }
626f8ce7c35SAkinobu Mita
627f8ce7c35SAkinobu Mita /* mt9m001_init() has reset the chip, returning registers to defaults */
628f8ce7c35SAkinobu Mita ret = v4l2_ctrl_handler_setup(&mt9m001->hdl);
629f8ce7c35SAkinobu Mita
630f8ce7c35SAkinobu Mita done:
631f8ce7c35SAkinobu Mita return ret;
632f8ce7c35SAkinobu Mita }
633f8ce7c35SAkinobu Mita
mt9m001_g_skip_top_lines(struct v4l2_subdev * sd,u32 * lines)634f8ce7c35SAkinobu Mita static int mt9m001_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines)
635f8ce7c35SAkinobu Mita {
636f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
637f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
638f8ce7c35SAkinobu Mita
639f8ce7c35SAkinobu Mita *lines = mt9m001->y_skip_top;
640f8ce7c35SAkinobu Mita
641f8ce7c35SAkinobu Mita return 0;
642f8ce7c35SAkinobu Mita }
643f8ce7c35SAkinobu Mita
644f8ce7c35SAkinobu Mita static const struct v4l2_ctrl_ops mt9m001_ctrl_ops = {
645f8ce7c35SAkinobu Mita .g_volatile_ctrl = mt9m001_g_volatile_ctrl,
646f8ce7c35SAkinobu Mita .s_ctrl = mt9m001_s_ctrl,
647f8ce7c35SAkinobu Mita };
648f8ce7c35SAkinobu Mita
649f8ce7c35SAkinobu Mita static const struct v4l2_subdev_core_ops mt9m001_subdev_core_ops = {
650dd15f070SAkinobu Mita .log_status = v4l2_ctrl_subdev_log_status,
651dd15f070SAkinobu Mita .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
652dd15f070SAkinobu Mita .unsubscribe_event = v4l2_event_subdev_unsubscribe,
653f8ce7c35SAkinobu Mita #ifdef CONFIG_VIDEO_ADV_DEBUG
654f8ce7c35SAkinobu Mita .g_register = mt9m001_g_register,
655f8ce7c35SAkinobu Mita .s_register = mt9m001_s_register,
656f8ce7c35SAkinobu Mita #endif
657f8ce7c35SAkinobu Mita };
658f8ce7c35SAkinobu Mita
mt9m001_init_cfg(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)65971f247daSAkinobu Mita static int mt9m001_init_cfg(struct v4l2_subdev *sd,
6600d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state)
66171f247daSAkinobu Mita {
66271f247daSAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
66371f247daSAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
66471f247daSAkinobu Mita struct v4l2_mbus_framefmt *try_fmt =
6650d346d2aSTomi Valkeinen v4l2_subdev_get_try_format(sd, sd_state, 0);
66671f247daSAkinobu Mita
66771f247daSAkinobu Mita try_fmt->width = MT9M001_MAX_WIDTH;
66871f247daSAkinobu Mita try_fmt->height = MT9M001_MAX_HEIGHT;
66971f247daSAkinobu Mita try_fmt->code = mt9m001->fmts[0].code;
67071f247daSAkinobu Mita try_fmt->colorspace = mt9m001->fmts[0].colorspace;
67171f247daSAkinobu Mita try_fmt->field = V4L2_FIELD_NONE;
67271f247daSAkinobu Mita try_fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
67371f247daSAkinobu Mita try_fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
67471f247daSAkinobu Mita try_fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
67571f247daSAkinobu Mita
67671f247daSAkinobu Mita return 0;
67771f247daSAkinobu Mita }
67871f247daSAkinobu Mita
mt9m001_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)679f8ce7c35SAkinobu Mita static int mt9m001_enum_mbus_code(struct v4l2_subdev *sd,
6800d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
681f8ce7c35SAkinobu Mita struct v4l2_subdev_mbus_code_enum *code)
682f8ce7c35SAkinobu Mita {
683f8ce7c35SAkinobu Mita struct i2c_client *client = v4l2_get_subdevdata(sd);
684f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
685f8ce7c35SAkinobu Mita
686f8ce7c35SAkinobu Mita if (code->pad || code->index >= mt9m001->num_fmts)
687f8ce7c35SAkinobu Mita return -EINVAL;
688f8ce7c35SAkinobu Mita
689f8ce7c35SAkinobu Mita code->code = mt9m001->fmts[code->index].code;
690f8ce7c35SAkinobu Mita return 0;
691f8ce7c35SAkinobu Mita }
692f8ce7c35SAkinobu Mita
mt9m001_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)6930c3da525SJacopo Mondi static int mt9m001_get_mbus_config(struct v4l2_subdev *sd,
6940c3da525SJacopo Mondi unsigned int pad,
695f8ce7c35SAkinobu Mita struct v4l2_mbus_config *cfg)
696f8ce7c35SAkinobu Mita {
697f8ce7c35SAkinobu Mita /* MT9M001 has all capture_format parameters fixed */
698f8ce7c35SAkinobu Mita cfg->type = V4L2_MBUS_PARALLEL;
6996a7bdd89SLaurent Pinchart cfg->bus.parallel.flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
7006a7bdd89SLaurent Pinchart V4L2_MBUS_HSYNC_ACTIVE_HIGH |
7016a7bdd89SLaurent Pinchart V4L2_MBUS_VSYNC_ACTIVE_HIGH |
7026a7bdd89SLaurent Pinchart V4L2_MBUS_DATA_ACTIVE_HIGH |
7036a7bdd89SLaurent Pinchart V4L2_MBUS_MASTER;
704f8ce7c35SAkinobu Mita
705f8ce7c35SAkinobu Mita return 0;
706f8ce7c35SAkinobu Mita }
707f8ce7c35SAkinobu Mita
708f8ce7c35SAkinobu Mita static const struct v4l2_subdev_video_ops mt9m001_subdev_video_ops = {
709f8ce7c35SAkinobu Mita .s_stream = mt9m001_s_stream,
710f8ce7c35SAkinobu Mita };
711f8ce7c35SAkinobu Mita
712f8ce7c35SAkinobu Mita static const struct v4l2_subdev_sensor_ops mt9m001_subdev_sensor_ops = {
713f8ce7c35SAkinobu Mita .g_skip_top_lines = mt9m001_g_skip_top_lines,
714f8ce7c35SAkinobu Mita };
715f8ce7c35SAkinobu Mita
716f8ce7c35SAkinobu Mita static const struct v4l2_subdev_pad_ops mt9m001_subdev_pad_ops = {
71771f247daSAkinobu Mita .init_cfg = mt9m001_init_cfg,
718f8ce7c35SAkinobu Mita .enum_mbus_code = mt9m001_enum_mbus_code,
719f8ce7c35SAkinobu Mita .get_selection = mt9m001_get_selection,
720f8ce7c35SAkinobu Mita .set_selection = mt9m001_set_selection,
721f8ce7c35SAkinobu Mita .get_fmt = mt9m001_get_fmt,
722f8ce7c35SAkinobu Mita .set_fmt = mt9m001_set_fmt,
7230c3da525SJacopo Mondi .get_mbus_config = mt9m001_get_mbus_config,
724f8ce7c35SAkinobu Mita };
725f8ce7c35SAkinobu Mita
726f8ce7c35SAkinobu Mita static const struct v4l2_subdev_ops mt9m001_subdev_ops = {
727f8ce7c35SAkinobu Mita .core = &mt9m001_subdev_core_ops,
728f8ce7c35SAkinobu Mita .video = &mt9m001_subdev_video_ops,
729f8ce7c35SAkinobu Mita .sensor = &mt9m001_subdev_sensor_ops,
730f8ce7c35SAkinobu Mita .pad = &mt9m001_subdev_pad_ops,
731f8ce7c35SAkinobu Mita };
732f8ce7c35SAkinobu Mita
mt9m001_probe(struct i2c_client * client)733e6714993SKieran Bingham static int mt9m001_probe(struct i2c_client *client)
734f8ce7c35SAkinobu Mita {
735f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001;
73641341dd9SWolfram Sang struct i2c_adapter *adapter = client->adapter;
737f8ce7c35SAkinobu Mita int ret;
738f8ce7c35SAkinobu Mita
739f8ce7c35SAkinobu Mita if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
740f8ce7c35SAkinobu Mita dev_warn(&adapter->dev,
741f8ce7c35SAkinobu Mita "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
742f8ce7c35SAkinobu Mita return -EIO;
743f8ce7c35SAkinobu Mita }
744f8ce7c35SAkinobu Mita
74574021329SAkinobu Mita mt9m001 = devm_kzalloc(&client->dev, sizeof(*mt9m001), GFP_KERNEL);
746f8ce7c35SAkinobu Mita if (!mt9m001)
747f8ce7c35SAkinobu Mita return -ENOMEM;
748f8ce7c35SAkinobu Mita
7498fcfc491SAkinobu Mita mt9m001->clk = devm_clk_get(&client->dev, NULL);
7508fcfc491SAkinobu Mita if (IS_ERR(mt9m001->clk))
7518fcfc491SAkinobu Mita return PTR_ERR(mt9m001->clk);
7528fcfc491SAkinobu Mita
7538fcfc491SAkinobu Mita mt9m001->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
7548fcfc491SAkinobu Mita GPIOD_OUT_LOW);
7558fcfc491SAkinobu Mita if (IS_ERR(mt9m001->standby_gpio))
7568fcfc491SAkinobu Mita return PTR_ERR(mt9m001->standby_gpio);
7578fcfc491SAkinobu Mita
7588fcfc491SAkinobu Mita mt9m001->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
7598fcfc491SAkinobu Mita GPIOD_OUT_LOW);
7608fcfc491SAkinobu Mita if (IS_ERR(mt9m001->reset_gpio))
7618fcfc491SAkinobu Mita return PTR_ERR(mt9m001->reset_gpio);
7628fcfc491SAkinobu Mita
763f8ce7c35SAkinobu Mita v4l2_i2c_subdev_init(&mt9m001->subdev, client, &mt9m001_subdev_ops);
764dd15f070SAkinobu Mita mt9m001->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
765dd15f070SAkinobu Mita V4L2_SUBDEV_FL_HAS_EVENTS;
766f8ce7c35SAkinobu Mita v4l2_ctrl_handler_init(&mt9m001->hdl, 4);
767f8ce7c35SAkinobu Mita v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
768f8ce7c35SAkinobu Mita V4L2_CID_VFLIP, 0, 1, 1, 0);
769f8ce7c35SAkinobu Mita v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
770f8ce7c35SAkinobu Mita V4L2_CID_GAIN, 0, 127, 1, 64);
771f8ce7c35SAkinobu Mita mt9m001->exposure = v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
772f8ce7c35SAkinobu Mita V4L2_CID_EXPOSURE, 1, 255, 1, 255);
773f8ce7c35SAkinobu Mita /*
774f8ce7c35SAkinobu Mita * Simulated autoexposure. If enabled, we calculate shutter width
775f8ce7c35SAkinobu Mita * ourselves in the driver based on vertical blanking and frame width
776f8ce7c35SAkinobu Mita */
777f8ce7c35SAkinobu Mita mt9m001->autoexposure = v4l2_ctrl_new_std_menu(&mt9m001->hdl,
778f8ce7c35SAkinobu Mita &mt9m001_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
779f8ce7c35SAkinobu Mita V4L2_EXPOSURE_AUTO);
780f8ce7c35SAkinobu Mita mt9m001->subdev.ctrl_handler = &mt9m001->hdl;
781f8ce7c35SAkinobu Mita if (mt9m001->hdl.error)
782f8ce7c35SAkinobu Mita return mt9m001->hdl.error;
783f8ce7c35SAkinobu Mita
784f8ce7c35SAkinobu Mita v4l2_ctrl_auto_cluster(2, &mt9m001->autoexposure,
785f8ce7c35SAkinobu Mita V4L2_EXPOSURE_MANUAL, true);
786f8ce7c35SAkinobu Mita
7878fcfc491SAkinobu Mita mutex_init(&mt9m001->mutex);
7888fcfc491SAkinobu Mita mt9m001->hdl.lock = &mt9m001->mutex;
7898fcfc491SAkinobu Mita
790f8ce7c35SAkinobu Mita /* Second stage probe - when a capture adapter is there */
791f8ce7c35SAkinobu Mita mt9m001->y_skip_top = 0;
792f8ce7c35SAkinobu Mita mt9m001->rect.left = MT9M001_COLUMN_SKIP;
793f8ce7c35SAkinobu Mita mt9m001->rect.top = MT9M001_ROW_SKIP;
794f8ce7c35SAkinobu Mita mt9m001->rect.width = MT9M001_MAX_WIDTH;
795f8ce7c35SAkinobu Mita mt9m001->rect.height = MT9M001_MAX_HEIGHT;
796f8ce7c35SAkinobu Mita
7978fcfc491SAkinobu Mita ret = mt9m001_power_on(&client->dev);
7988fcfc491SAkinobu Mita if (ret)
7998fcfc491SAkinobu Mita goto error_hdl_free;
8008fcfc491SAkinobu Mita
8018fcfc491SAkinobu Mita pm_runtime_set_active(&client->dev);
8028fcfc491SAkinobu Mita pm_runtime_enable(&client->dev);
803f8ce7c35SAkinobu Mita
80474021329SAkinobu Mita ret = mt9m001_video_probe(client);
8058fcfc491SAkinobu Mita if (ret)
8068fcfc491SAkinobu Mita goto error_power_off;
8078fcfc491SAkinobu Mita
80812d85c3eSAkinobu Mita mt9m001->pad.flags = MEDIA_PAD_FL_SOURCE;
80912d85c3eSAkinobu Mita mt9m001->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
81012d85c3eSAkinobu Mita ret = media_entity_pads_init(&mt9m001->subdev.entity, 1, &mt9m001->pad);
81112d85c3eSAkinobu Mita if (ret)
81212d85c3eSAkinobu Mita goto error_power_off;
81312d85c3eSAkinobu Mita
81473b33860SAkinobu Mita ret = v4l2_async_register_subdev(&mt9m001->subdev);
81573b33860SAkinobu Mita if (ret)
81673b33860SAkinobu Mita goto error_entity_cleanup;
81773b33860SAkinobu Mita
8188fcfc491SAkinobu Mita pm_runtime_idle(&client->dev);
8198fcfc491SAkinobu Mita
8208fcfc491SAkinobu Mita return 0;
8218fcfc491SAkinobu Mita
82273b33860SAkinobu Mita error_entity_cleanup:
82373b33860SAkinobu Mita media_entity_cleanup(&mt9m001->subdev.entity);
8248fcfc491SAkinobu Mita error_power_off:
8258fcfc491SAkinobu Mita pm_runtime_disable(&client->dev);
8268fcfc491SAkinobu Mita pm_runtime_set_suspended(&client->dev);
8278fcfc491SAkinobu Mita mt9m001_power_off(&client->dev);
8288fcfc491SAkinobu Mita
8298fcfc491SAkinobu Mita error_hdl_free:
830f8ce7c35SAkinobu Mita v4l2_ctrl_handler_free(&mt9m001->hdl);
8318fcfc491SAkinobu Mita mutex_destroy(&mt9m001->mutex);
832f8ce7c35SAkinobu Mita
833f8ce7c35SAkinobu Mita return ret;
834f8ce7c35SAkinobu Mita }
835f8ce7c35SAkinobu Mita
mt9m001_remove(struct i2c_client * client)836ed5c2f5fSUwe Kleine-König static void mt9m001_remove(struct i2c_client *client)
837f8ce7c35SAkinobu Mita {
838f8ce7c35SAkinobu Mita struct mt9m001 *mt9m001 = to_mt9m001(client);
839f8ce7c35SAkinobu Mita
840e7c018a9SMauro Carvalho Chehab /*
841e7c018a9SMauro Carvalho Chehab * As it increments RPM usage_count even on errors, we don't need to
842e7c018a9SMauro Carvalho Chehab * check the returned code here.
843e7c018a9SMauro Carvalho Chehab */
8448fcfc491SAkinobu Mita pm_runtime_get_sync(&client->dev);
8458fcfc491SAkinobu Mita
84673b33860SAkinobu Mita v4l2_async_unregister_subdev(&mt9m001->subdev);
84712d85c3eSAkinobu Mita media_entity_cleanup(&mt9m001->subdev.entity);
84812d85c3eSAkinobu Mita
8498fcfc491SAkinobu Mita pm_runtime_disable(&client->dev);
8508fcfc491SAkinobu Mita pm_runtime_set_suspended(&client->dev);
8518fcfc491SAkinobu Mita pm_runtime_put_noidle(&client->dev);
8528fcfc491SAkinobu Mita mt9m001_power_off(&client->dev);
8538fcfc491SAkinobu Mita
854f8ce7c35SAkinobu Mita v4l2_ctrl_handler_free(&mt9m001->hdl);
8558fcfc491SAkinobu Mita mutex_destroy(&mt9m001->mutex);
856f8ce7c35SAkinobu Mita }
857f8ce7c35SAkinobu Mita
858f8ce7c35SAkinobu Mita static const struct i2c_device_id mt9m001_id[] = {
859f8ce7c35SAkinobu Mita { "mt9m001", 0 },
860f8ce7c35SAkinobu Mita { }
861f8ce7c35SAkinobu Mita };
862f8ce7c35SAkinobu Mita MODULE_DEVICE_TABLE(i2c, mt9m001_id);
863f8ce7c35SAkinobu Mita
8648fcfc491SAkinobu Mita static const struct dev_pm_ops mt9m001_pm_ops = {
8658fcfc491SAkinobu Mita SET_RUNTIME_PM_OPS(mt9m001_power_off, mt9m001_power_on, NULL)
8668fcfc491SAkinobu Mita };
8678fcfc491SAkinobu Mita
8681e57e4ceSAkinobu Mita static const struct of_device_id mt9m001_of_match[] = {
8691e57e4ceSAkinobu Mita { .compatible = "onnn,mt9m001", },
8701e57e4ceSAkinobu Mita { /* sentinel */ },
8711e57e4ceSAkinobu Mita };
8721e57e4ceSAkinobu Mita MODULE_DEVICE_TABLE(of, mt9m001_of_match);
8731e57e4ceSAkinobu Mita
874f8ce7c35SAkinobu Mita static struct i2c_driver mt9m001_i2c_driver = {
875f8ce7c35SAkinobu Mita .driver = {
876f8ce7c35SAkinobu Mita .name = "mt9m001",
8778fcfc491SAkinobu Mita .pm = &mt9m001_pm_ops,
8781e57e4ceSAkinobu Mita .of_match_table = mt9m001_of_match,
879f8ce7c35SAkinobu Mita },
880*aaeb31c0SUwe Kleine-König .probe = mt9m001_probe,
881f8ce7c35SAkinobu Mita .remove = mt9m001_remove,
882f8ce7c35SAkinobu Mita .id_table = mt9m001_id,
883f8ce7c35SAkinobu Mita };
884f8ce7c35SAkinobu Mita
885f8ce7c35SAkinobu Mita module_i2c_driver(mt9m001_i2c_driver);
886f8ce7c35SAkinobu Mita
887f8ce7c35SAkinobu Mita MODULE_DESCRIPTION("Micron MT9M001 Camera driver");
888f8ce7c35SAkinobu Mita MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
8891f01091fSAkinobu Mita MODULE_LICENSE("GPL v2");
890