xref: /openbmc/linux/drivers/media/i2c/ov6650.c (revision aaeb31c0)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
4  *
5  * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
6  *
7  * Based on OmniVision OV96xx Camera Driver
8  * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
9  *
10  * Based on ov772x camera driver:
11  * Copyright (C) 2008 Renesas Solutions Corp.
12  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
13  *
14  * Based on ov7670 and soc_camera_platform driver,
15  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
16  * Copyright (C) 2008 Magnus Damm
17  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
18  *
19  * Hardware specific bits initially based on former work by Matt Callow
20  * drivers/media/video/omap/sensor_ov6650.c
21  * Copyright (C) 2006 Matt Callow
22  */
23 
24 #include <linux/bitops.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
28 #include <linux/slab.h>
29 #include <linux/v4l2-mediabus.h>
30 #include <linux/module.h>
31 
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-device.h>
34 
35 /* Register definitions */
36 #define REG_GAIN		0x00	/* range 00 - 3F */
37 #define REG_BLUE		0x01
38 #define REG_RED			0x02
39 #define REG_SAT			0x03	/* [7:4] saturation [0:3] reserved */
40 #define REG_HUE			0x04	/* [7:6] rsrvd [5] hue en [4:0] hue */
41 
42 #define REG_BRT			0x06
43 
44 #define REG_PIDH		0x0a
45 #define REG_PIDL		0x0b
46 
47 #define REG_AECH		0x10
48 #define REG_CLKRC		0x11	/* Data Format and Internal Clock */
49 					/* [7:6] Input system clock (MHz)*/
50 					/*   00=8, 01=12, 10=16, 11=24 */
51 					/* [5:0]: Internal Clock Pre-Scaler */
52 #define REG_COMA		0x12	/* [7] Reset */
53 #define REG_COMB		0x13
54 #define REG_COMC		0x14
55 #define REG_COMD		0x15
56 #define REG_COML		0x16
57 #define REG_HSTRT		0x17
58 #define REG_HSTOP		0x18
59 #define REG_VSTRT		0x19
60 #define REG_VSTOP		0x1a
61 #define REG_PSHFT		0x1b
62 #define REG_MIDH		0x1c
63 #define REG_MIDL		0x1d
64 #define REG_HSYNS		0x1e
65 #define REG_HSYNE		0x1f
66 #define REG_COME		0x20
67 #define REG_YOFF		0x21
68 #define REG_UOFF		0x22
69 #define REG_VOFF		0x23
70 #define REG_AEW			0x24
71 #define REG_AEB			0x25
72 #define REG_COMF		0x26
73 #define REG_COMG		0x27
74 #define REG_COMH		0x28
75 #define REG_COMI		0x29
76 
77 #define REG_FRARL		0x2b
78 #define REG_COMJ		0x2c
79 #define REG_COMK		0x2d
80 #define REG_AVGY		0x2e
81 #define REG_REF0		0x2f
82 #define REG_REF1		0x30
83 #define REG_REF2		0x31
84 #define REG_FRAJH		0x32
85 #define REG_FRAJL		0x33
86 #define REG_FACT		0x34
87 #define REG_L1AEC		0x35
88 #define REG_AVGU		0x36
89 #define REG_AVGV		0x37
90 
91 #define REG_SPCB		0x60
92 #define REG_SPCC		0x61
93 #define REG_GAM1		0x62
94 #define REG_GAM2		0x63
95 #define REG_GAM3		0x64
96 #define REG_SPCD		0x65
97 
98 #define REG_SPCE		0x68
99 #define REG_ADCL		0x69
100 
101 #define REG_RMCO		0x6c
102 #define REG_GMCO		0x6d
103 #define REG_BMCO		0x6e
104 
105 
106 /* Register bits, values, etc. */
107 #define OV6650_PIDH		0x66	/* high byte of product ID number */
108 #define OV6650_PIDL		0x50	/* low byte of product ID number */
109 #define OV6650_MIDH		0x7F	/* high byte of mfg ID */
110 #define OV6650_MIDL		0xA2	/* low byte of mfg ID */
111 
112 #define DEF_GAIN		0x00
113 #define DEF_BLUE		0x80
114 #define DEF_RED			0x80
115 
116 #define SAT_SHIFT		4
117 #define SAT_MASK		(0xf << SAT_SHIFT)
118 #define SET_SAT(x)		(((x) << SAT_SHIFT) & SAT_MASK)
119 
120 #define HUE_EN			BIT(5)
121 #define HUE_MASK		0x1f
122 #define DEF_HUE			0x10
123 #define SET_HUE(x)		(HUE_EN | ((x) & HUE_MASK))
124 
125 #define DEF_AECH		0x4D
126 
127 #define CLKRC_8MHz		0x00
128 #define CLKRC_12MHz		0x40
129 #define CLKRC_16MHz		0x80
130 #define CLKRC_24MHz		0xc0
131 #define CLKRC_DIV_MASK		0x3f
132 #define GET_CLKRC_DIV(x)	(((x) & CLKRC_DIV_MASK) + 1)
133 #define DEF_CLKRC		0x00
134 
135 #define COMA_RESET		BIT(7)
136 #define COMA_QCIF		BIT(5)
137 #define COMA_RAW_RGB		BIT(4)
138 #define COMA_RGB		BIT(3)
139 #define COMA_BW			BIT(2)
140 #define COMA_WORD_SWAP		BIT(1)
141 #define COMA_BYTE_SWAP		BIT(0)
142 #define DEF_COMA		0x00
143 
144 #define COMB_FLIP_V		BIT(7)
145 #define COMB_FLIP_H		BIT(5)
146 #define COMB_BAND_FILTER	BIT(4)
147 #define COMB_AWB		BIT(2)
148 #define COMB_AGC		BIT(1)
149 #define COMB_AEC		BIT(0)
150 #define DEF_COMB		0x5f
151 
152 #define COML_ONE_CHANNEL	BIT(7)
153 
154 #define DEF_HSTRT		0x24
155 #define DEF_HSTOP		0xd4
156 #define DEF_VSTRT		0x04
157 #define DEF_VSTOP		0x94
158 
159 #define COMF_HREF_LOW		BIT(4)
160 
161 #define COMJ_PCLK_RISING	BIT(4)
162 #define COMJ_VSYNC_HIGH		BIT(0)
163 
164 /* supported resolutions */
165 #define W_QCIF			(DEF_HSTOP - DEF_HSTRT)
166 #define W_CIF			(W_QCIF << 1)
167 #define H_QCIF			(DEF_VSTOP - DEF_VSTRT)
168 #define H_CIF			(H_QCIF << 1)
169 
170 #define FRAME_RATE_MAX		30
171 
172 
173 struct ov6650_reg {
174 	u8	reg;
175 	u8	val;
176 };
177 
178 struct ov6650 {
179 	struct v4l2_subdev	subdev;
180 	struct v4l2_ctrl_handler hdl;
181 	struct {
182 		/* exposure/autoexposure cluster */
183 		struct v4l2_ctrl *autoexposure;
184 		struct v4l2_ctrl *exposure;
185 	};
186 	struct {
187 		/* gain/autogain cluster */
188 		struct v4l2_ctrl *autogain;
189 		struct v4l2_ctrl *gain;
190 	};
191 	struct {
192 		/* blue/red/autowhitebalance cluster */
193 		struct v4l2_ctrl *autowb;
194 		struct v4l2_ctrl *blue;
195 		struct v4l2_ctrl *red;
196 	};
197 	struct clk		*clk;
198 	bool			half_scale;	/* scale down output by 2 */
199 	struct v4l2_rect	rect;		/* sensor cropping window */
200 	struct v4l2_fract	tpf;		/* as requested with s_frame_interval */
201 	u32 code;
202 };
203 
204 struct ov6650_xclk {
205 	unsigned long	rate;
206 	u8		clkrc;
207 };
208 
209 static const struct ov6650_xclk ov6650_xclk[] = {
210 {
211 	.rate	= 8000000,
212 	.clkrc	= CLKRC_8MHz,
213 },
214 {
215 	.rate	= 12000000,
216 	.clkrc	= CLKRC_12MHz,
217 },
218 {
219 	.rate	= 16000000,
220 	.clkrc	= CLKRC_16MHz,
221 },
222 {
223 	.rate	= 24000000,
224 	.clkrc	= CLKRC_24MHz,
225 },
226 };
227 
228 static u32 ov6650_codes[] = {
229 	MEDIA_BUS_FMT_YUYV8_2X8,
230 	MEDIA_BUS_FMT_UYVY8_2X8,
231 	MEDIA_BUS_FMT_YVYU8_2X8,
232 	MEDIA_BUS_FMT_VYUY8_2X8,
233 	MEDIA_BUS_FMT_SBGGR8_1X8,
234 	MEDIA_BUS_FMT_Y8_1X8,
235 };
236 
237 static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
238 	.width		= W_CIF,
239 	.height		= H_CIF,
240 	.code		= MEDIA_BUS_FMT_SBGGR8_1X8,
241 	.colorspace	= V4L2_COLORSPACE_SRGB,
242 	.field		= V4L2_FIELD_NONE,
243 	.ycbcr_enc	= V4L2_YCBCR_ENC_DEFAULT,
244 	.quantization	= V4L2_QUANTIZATION_DEFAULT,
245 	.xfer_func	= V4L2_XFER_FUNC_DEFAULT,
246 };
247 
248 /* read a register */
ov6650_reg_read(struct i2c_client * client,u8 reg,u8 * val)249 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
250 {
251 	int ret;
252 	u8 data = reg;
253 	struct i2c_msg msg = {
254 		.addr	= client->addr,
255 		.flags	= 0,
256 		.len	= 1,
257 		.buf	= &data,
258 	};
259 
260 	ret = i2c_transfer(client->adapter, &msg, 1);
261 	if (ret < 0)
262 		goto err;
263 
264 	msg.flags = I2C_M_RD;
265 	ret = i2c_transfer(client->adapter, &msg, 1);
266 	if (ret < 0)
267 		goto err;
268 
269 	*val = data;
270 	return 0;
271 
272 err:
273 	dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
274 	return ret;
275 }
276 
277 /* write a register */
ov6650_reg_write(struct i2c_client * client,u8 reg,u8 val)278 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
279 {
280 	int ret;
281 	unsigned char data[2] = { reg, val };
282 	struct i2c_msg msg = {
283 		.addr	= client->addr,
284 		.flags	= 0,
285 		.len	= 2,
286 		.buf	= data,
287 	};
288 
289 	ret = i2c_transfer(client->adapter, &msg, 1);
290 	udelay(100);
291 
292 	if (ret < 0) {
293 		dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
294 		return ret;
295 	}
296 	return 0;
297 }
298 
299 
300 /* Read a register, alter its bits, write it back */
ov6650_reg_rmw(struct i2c_client * client,u8 reg,u8 set,u8 mask)301 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
302 {
303 	u8 val;
304 	int ret;
305 
306 	ret = ov6650_reg_read(client, reg, &val);
307 	if (ret) {
308 		dev_err(&client->dev,
309 			"[Read]-Modify-Write of register 0x%02x failed!\n",
310 			reg);
311 		return ret;
312 	}
313 
314 	val &= ~mask;
315 	val |= set;
316 
317 	ret = ov6650_reg_write(client, reg, val);
318 	if (ret)
319 		dev_err(&client->dev,
320 			"Read-Modify-[Write] of register 0x%02x failed!\n",
321 			reg);
322 
323 	return ret;
324 }
325 
to_ov6650(const struct i2c_client * client)326 static struct ov6650 *to_ov6650(const struct i2c_client *client)
327 {
328 	return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
329 }
330 
331 /* Start/Stop streaming from the device */
ov6650_s_stream(struct v4l2_subdev * sd,int enable)332 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
333 {
334 	return 0;
335 }
336 
337 /* Get status of additional camera capabilities */
ov6550_g_volatile_ctrl(struct v4l2_ctrl * ctrl)338 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
339 {
340 	struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
341 	struct v4l2_subdev *sd = &priv->subdev;
342 	struct i2c_client *client = v4l2_get_subdevdata(sd);
343 	uint8_t reg, reg2;
344 	int ret;
345 
346 	switch (ctrl->id) {
347 	case V4L2_CID_AUTOGAIN:
348 		ret = ov6650_reg_read(client, REG_GAIN, &reg);
349 		if (!ret)
350 			priv->gain->val = reg;
351 		return ret;
352 	case V4L2_CID_AUTO_WHITE_BALANCE:
353 		ret = ov6650_reg_read(client, REG_BLUE, &reg);
354 		if (!ret)
355 			ret = ov6650_reg_read(client, REG_RED, &reg2);
356 		if (!ret) {
357 			priv->blue->val = reg;
358 			priv->red->val = reg2;
359 		}
360 		return ret;
361 	case V4L2_CID_EXPOSURE_AUTO:
362 		ret = ov6650_reg_read(client, REG_AECH, &reg);
363 		if (!ret)
364 			priv->exposure->val = reg;
365 		return ret;
366 	}
367 	return -EINVAL;
368 }
369 
370 /* Set status of additional camera capabilities */
ov6550_s_ctrl(struct v4l2_ctrl * ctrl)371 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
372 {
373 	struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
374 	struct v4l2_subdev *sd = &priv->subdev;
375 	struct i2c_client *client = v4l2_get_subdevdata(sd);
376 	int ret;
377 
378 	switch (ctrl->id) {
379 	case V4L2_CID_AUTOGAIN:
380 		ret = ov6650_reg_rmw(client, REG_COMB,
381 				ctrl->val ? COMB_AGC : 0, COMB_AGC);
382 		if (!ret && !ctrl->val)
383 			ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
384 		return ret;
385 	case V4L2_CID_AUTO_WHITE_BALANCE:
386 		ret = ov6650_reg_rmw(client, REG_COMB,
387 				ctrl->val ? COMB_AWB : 0, COMB_AWB);
388 		if (!ret && !ctrl->val) {
389 			ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
390 			if (!ret)
391 				ret = ov6650_reg_write(client, REG_RED,
392 							priv->red->val);
393 		}
394 		return ret;
395 	case V4L2_CID_SATURATION:
396 		return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
397 				SAT_MASK);
398 	case V4L2_CID_HUE:
399 		return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
400 				HUE_MASK);
401 	case V4L2_CID_BRIGHTNESS:
402 		return ov6650_reg_write(client, REG_BRT, ctrl->val);
403 	case V4L2_CID_EXPOSURE_AUTO:
404 		ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
405 				V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
406 		if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
407 			ret = ov6650_reg_write(client, REG_AECH,
408 						priv->exposure->val);
409 		return ret;
410 	case V4L2_CID_GAMMA:
411 		return ov6650_reg_write(client, REG_GAM1, ctrl->val);
412 	case V4L2_CID_VFLIP:
413 		return ov6650_reg_rmw(client, REG_COMB,
414 				ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
415 	case V4L2_CID_HFLIP:
416 		return ov6650_reg_rmw(client, REG_COMB,
417 				ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
418 	}
419 
420 	return -EINVAL;
421 }
422 
423 #ifdef CONFIG_VIDEO_ADV_DEBUG
ov6650_get_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)424 static int ov6650_get_register(struct v4l2_subdev *sd,
425 				struct v4l2_dbg_register *reg)
426 {
427 	struct i2c_client *client = v4l2_get_subdevdata(sd);
428 	int ret;
429 	u8 val;
430 
431 	if (reg->reg & ~0xff)
432 		return -EINVAL;
433 
434 	reg->size = 1;
435 
436 	ret = ov6650_reg_read(client, reg->reg, &val);
437 	if (!ret)
438 		reg->val = (__u64)val;
439 
440 	return ret;
441 }
442 
ov6650_set_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)443 static int ov6650_set_register(struct v4l2_subdev *sd,
444 				const struct v4l2_dbg_register *reg)
445 {
446 	struct i2c_client *client = v4l2_get_subdevdata(sd);
447 
448 	if (reg->reg & ~0xff || reg->val & ~0xff)
449 		return -EINVAL;
450 
451 	return ov6650_reg_write(client, reg->reg, reg->val);
452 }
453 #endif
454 
ov6650_s_power(struct v4l2_subdev * sd,int on)455 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
456 {
457 	struct i2c_client *client = v4l2_get_subdevdata(sd);
458 	struct ov6650 *priv = to_ov6650(client);
459 	int ret = 0;
460 
461 	if (on)
462 		ret = clk_prepare_enable(priv->clk);
463 	else
464 		clk_disable_unprepare(priv->clk);
465 
466 	return ret;
467 }
468 
ov6650_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)469 static int ov6650_get_selection(struct v4l2_subdev *sd,
470 		struct v4l2_subdev_state *sd_state,
471 		struct v4l2_subdev_selection *sel)
472 {
473 	struct i2c_client *client = v4l2_get_subdevdata(sd);
474 	struct ov6650 *priv = to_ov6650(client);
475 	struct v4l2_rect *rect;
476 
477 	if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
478 		/* pre-select try crop rectangle */
479 		rect = &sd_state->pads->try_crop;
480 
481 	} else {
482 		/* pre-select active crop rectangle */
483 		rect = &priv->rect;
484 	}
485 
486 	switch (sel->target) {
487 	case V4L2_SEL_TGT_CROP_BOUNDS:
488 		sel->r.left = DEF_HSTRT << 1;
489 		sel->r.top = DEF_VSTRT << 1;
490 		sel->r.width = W_CIF;
491 		sel->r.height = H_CIF;
492 		return 0;
493 
494 	case V4L2_SEL_TGT_CROP:
495 		/* use selected crop rectangle */
496 		sel->r = *rect;
497 		return 0;
498 
499 	default:
500 		return -EINVAL;
501 	}
502 }
503 
is_unscaled_ok(int width,int height,struct v4l2_rect * rect)504 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
505 {
506 	return width > rect->width >> 1 || height > rect->height >> 1;
507 }
508 
ov6650_bind_align_crop_rectangle(struct v4l2_rect * rect)509 static void ov6650_bind_align_crop_rectangle(struct v4l2_rect *rect)
510 {
511 	v4l_bound_align_image(&rect->width, 2, W_CIF, 1,
512 			      &rect->height, 2, H_CIF, 1, 0);
513 	v4l_bound_align_image(&rect->left, DEF_HSTRT << 1,
514 			      (DEF_HSTRT << 1) + W_CIF - (__s32)rect->width, 1,
515 			      &rect->top, DEF_VSTRT << 1,
516 			      (DEF_VSTRT << 1) + H_CIF - (__s32)rect->height,
517 			      1, 0);
518 }
519 
ov6650_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)520 static int ov6650_set_selection(struct v4l2_subdev *sd,
521 		struct v4l2_subdev_state *sd_state,
522 		struct v4l2_subdev_selection *sel)
523 {
524 	struct i2c_client *client = v4l2_get_subdevdata(sd);
525 	struct ov6650 *priv = to_ov6650(client);
526 	int ret;
527 
528 	if (sel->target != V4L2_SEL_TGT_CROP)
529 		return -EINVAL;
530 
531 	ov6650_bind_align_crop_rectangle(&sel->r);
532 
533 	if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
534 		struct v4l2_rect *crop = &sd_state->pads->try_crop;
535 		struct v4l2_mbus_framefmt *mf = &sd_state->pads->try_fmt;
536 		/* detect current pad config scaling factor */
537 		bool half_scale = !is_unscaled_ok(mf->width, mf->height, crop);
538 
539 		/* store new crop rectangle */
540 		*crop = sel->r;
541 
542 		/* adjust frame size */
543 		mf->width = crop->width >> half_scale;
544 		mf->height = crop->height >> half_scale;
545 
546 		return 0;
547 	}
548 
549 	/* V4L2_SUBDEV_FORMAT_ACTIVE */
550 
551 	/* apply new crop rectangle */
552 	ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1);
553 	if (!ret) {
554 		priv->rect.width += priv->rect.left - sel->r.left;
555 		priv->rect.left = sel->r.left;
556 		ret = ov6650_reg_write(client, REG_HSTOP,
557 				       (sel->r.left + sel->r.width) >> 1);
558 	}
559 	if (!ret) {
560 		priv->rect.width = sel->r.width;
561 		ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1);
562 	}
563 	if (!ret) {
564 		priv->rect.height += priv->rect.top - sel->r.top;
565 		priv->rect.top = sel->r.top;
566 		ret = ov6650_reg_write(client, REG_VSTOP,
567 				       (sel->r.top + sel->r.height) >> 1);
568 	}
569 	if (!ret)
570 		priv->rect.height = sel->r.height;
571 
572 	return ret;
573 }
574 
ov6650_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)575 static int ov6650_get_fmt(struct v4l2_subdev *sd,
576 		struct v4l2_subdev_state *sd_state,
577 		struct v4l2_subdev_format *format)
578 {
579 	struct v4l2_mbus_framefmt *mf = &format->format;
580 	struct i2c_client *client = v4l2_get_subdevdata(sd);
581 	struct ov6650 *priv = to_ov6650(client);
582 
583 	if (format->pad)
584 		return -EINVAL;
585 
586 	/* initialize response with default media bus frame format */
587 	*mf = ov6650_def_fmt;
588 
589 	/* update media bus format code and frame size */
590 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
591 		mf->width = sd_state->pads->try_fmt.width;
592 		mf->height = sd_state->pads->try_fmt.height;
593 		mf->code = sd_state->pads->try_fmt.code;
594 
595 	} else {
596 		mf->width = priv->rect.width >> priv->half_scale;
597 		mf->height = priv->rect.height >> priv->half_scale;
598 		mf->code = priv->code;
599 	}
600 	return 0;
601 }
602 
603 #define to_clkrc(div)	((div) - 1)
604 
605 /* set the format we will capture in */
ov6650_s_fmt(struct v4l2_subdev * sd,u32 code,bool half_scale)606 static int ov6650_s_fmt(struct v4l2_subdev *sd, u32 code, bool half_scale)
607 {
608 	struct i2c_client *client = v4l2_get_subdevdata(sd);
609 	struct ov6650 *priv = to_ov6650(client);
610 	u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask;
611 	int ret;
612 
613 	/* select color matrix configuration for given color encoding */
614 	switch (code) {
615 	case MEDIA_BUS_FMT_Y8_1X8:
616 		dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
617 		coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
618 		coma_set |= COMA_BW;
619 		break;
620 	case MEDIA_BUS_FMT_YUYV8_2X8:
621 		dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
622 		coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
623 		coma_set |= COMA_WORD_SWAP;
624 		break;
625 	case MEDIA_BUS_FMT_YVYU8_2X8:
626 		dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
627 		coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
628 				COMA_BYTE_SWAP;
629 		break;
630 	case MEDIA_BUS_FMT_UYVY8_2X8:
631 		dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
632 		if (half_scale) {
633 			coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
634 			coma_set |= COMA_BYTE_SWAP;
635 		} else {
636 			coma_mask |= COMA_RGB | COMA_BW;
637 			coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
638 		}
639 		break;
640 	case MEDIA_BUS_FMT_VYUY8_2X8:
641 		dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
642 		if (half_scale) {
643 			coma_mask |= COMA_RGB | COMA_BW;
644 			coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
645 		} else {
646 			coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
647 			coma_set |= COMA_BYTE_SWAP;
648 		}
649 		break;
650 	case MEDIA_BUS_FMT_SBGGR8_1X8:
651 		dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
652 		coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
653 		coma_set |= COMA_RAW_RGB | COMA_RGB;
654 		break;
655 	default:
656 		dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
657 		return -EINVAL;
658 	}
659 
660 	if (code == MEDIA_BUS_FMT_Y8_1X8 ||
661 			code == MEDIA_BUS_FMT_SBGGR8_1X8) {
662 		coml_mask = COML_ONE_CHANNEL;
663 		coml_set = 0;
664 	} else {
665 		coml_mask = 0;
666 		coml_set = COML_ONE_CHANNEL;
667 	}
668 
669 	if (half_scale) {
670 		dev_dbg(&client->dev, "max resolution: QCIF\n");
671 		coma_set |= COMA_QCIF;
672 	} else {
673 		dev_dbg(&client->dev, "max resolution: CIF\n");
674 		coma_mask |= COMA_QCIF;
675 	}
676 
677 	ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
678 	if (!ret) {
679 		priv->half_scale = half_scale;
680 
681 		ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
682 	}
683 	if (!ret)
684 		priv->code = code;
685 
686 	return ret;
687 }
688 
ov6650_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)689 static int ov6650_set_fmt(struct v4l2_subdev *sd,
690 		struct v4l2_subdev_state *sd_state,
691 		struct v4l2_subdev_format *format)
692 {
693 	struct v4l2_mbus_framefmt *mf = &format->format;
694 	struct i2c_client *client = v4l2_get_subdevdata(sd);
695 	struct ov6650 *priv = to_ov6650(client);
696 	struct v4l2_rect *crop;
697 	bool half_scale;
698 
699 	if (format->pad)
700 		return -EINVAL;
701 
702 	switch (mf->code) {
703 	case MEDIA_BUS_FMT_Y10_1X10:
704 		mf->code = MEDIA_BUS_FMT_Y8_1X8;
705 		fallthrough;
706 	case MEDIA_BUS_FMT_Y8_1X8:
707 	case MEDIA_BUS_FMT_YVYU8_2X8:
708 	case MEDIA_BUS_FMT_YUYV8_2X8:
709 	case MEDIA_BUS_FMT_VYUY8_2X8:
710 	case MEDIA_BUS_FMT_UYVY8_2X8:
711 		break;
712 	default:
713 		mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
714 		fallthrough;
715 	case MEDIA_BUS_FMT_SBGGR8_1X8:
716 		break;
717 	}
718 
719 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
720 		crop = &sd_state->pads->try_crop;
721 	else
722 		crop = &priv->rect;
723 
724 	half_scale = !is_unscaled_ok(mf->width, mf->height, crop);
725 
726 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
727 		/* store new mbus frame format code and size in pad config */
728 		sd_state->pads->try_fmt.width = crop->width >> half_scale;
729 		sd_state->pads->try_fmt.height = crop->height >> half_scale;
730 		sd_state->pads->try_fmt.code = mf->code;
731 
732 		/* return default mbus frame format updated with pad config */
733 		*mf = ov6650_def_fmt;
734 		mf->width = sd_state->pads->try_fmt.width;
735 		mf->height = sd_state->pads->try_fmt.height;
736 		mf->code = sd_state->pads->try_fmt.code;
737 
738 	} else {
739 		int ret = 0;
740 
741 		/* apply new media bus frame format and scaling if changed */
742 		if (mf->code != priv->code || half_scale != priv->half_scale)
743 			ret = ov6650_s_fmt(sd, mf->code, half_scale);
744 		if (ret)
745 			return ret;
746 
747 		/* return default format updated with active size and code */
748 		*mf = ov6650_def_fmt;
749 		mf->width = priv->rect.width >> priv->half_scale;
750 		mf->height = priv->rect.height >> priv->half_scale;
751 		mf->code = priv->code;
752 	}
753 	return 0;
754 }
755 
ov6650_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)756 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
757 		struct v4l2_subdev_state *sd_state,
758 		struct v4l2_subdev_mbus_code_enum *code)
759 {
760 	if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
761 		return -EINVAL;
762 
763 	code->code = ov6650_codes[code->index];
764 	return 0;
765 }
766 
ov6650_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval_enum * fie)767 static int ov6650_enum_frame_interval(struct v4l2_subdev *sd,
768 				    struct v4l2_subdev_state *sd_state,
769 				    struct v4l2_subdev_frame_interval_enum *fie)
770 {
771 	int i;
772 
773 	/* enumerate supported frame intervals not exceeding 1 second */
774 	if (fie->index > CLKRC_DIV_MASK ||
775 	    GET_CLKRC_DIV(fie->index) > FRAME_RATE_MAX)
776 		return -EINVAL;
777 
778 	for (i = 0; i < ARRAY_SIZE(ov6650_codes); i++)
779 		if (fie->code == ov6650_codes[i])
780 			break;
781 	if (i == ARRAY_SIZE(ov6650_codes))
782 		return -EINVAL;
783 
784 	if (!fie->width || fie->width > W_CIF ||
785 	    !fie->height || fie->height > H_CIF)
786 		return -EINVAL;
787 
788 	fie->interval.numerator = GET_CLKRC_DIV(fie->index);
789 	fie->interval.denominator = FRAME_RATE_MAX;
790 
791 	return 0;
792 }
793 
ov6650_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * ival)794 static int ov6650_g_frame_interval(struct v4l2_subdev *sd,
795 				   struct v4l2_subdev_frame_interval *ival)
796 {
797 	struct i2c_client *client = v4l2_get_subdevdata(sd);
798 	struct ov6650 *priv = to_ov6650(client);
799 
800 	ival->interval = priv->tpf;
801 
802 	dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
803 		ival->interval.numerator, ival->interval.denominator);
804 
805 	return 0;
806 }
807 
ov6650_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * ival)808 static int ov6650_s_frame_interval(struct v4l2_subdev *sd,
809 				   struct v4l2_subdev_frame_interval *ival)
810 {
811 	struct i2c_client *client = v4l2_get_subdevdata(sd);
812 	struct ov6650 *priv = to_ov6650(client);
813 	struct v4l2_fract *tpf = &ival->interval;
814 	int div, ret;
815 
816 	if (tpf->numerator == 0 || tpf->denominator == 0)
817 		div = 1;  /* Reset to full rate */
818 	else
819 		div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
820 
821 	if (div == 0)
822 		div = 1;
823 	else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
824 		div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
825 
826 	ret = ov6650_reg_rmw(client, REG_CLKRC, to_clkrc(div), CLKRC_DIV_MASK);
827 	if (!ret) {
828 		priv->tpf.numerator = div;
829 		priv->tpf.denominator = FRAME_RATE_MAX;
830 
831 		*tpf = priv->tpf;
832 	}
833 
834 	return ret;
835 }
836 
837 /* Soft reset the camera. This has nothing to do with the RESET pin! */
ov6650_reset(struct i2c_client * client)838 static int ov6650_reset(struct i2c_client *client)
839 {
840 	int ret;
841 
842 	dev_dbg(&client->dev, "reset\n");
843 
844 	ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
845 	if (ret)
846 		dev_err(&client->dev,
847 			"An error occurred while entering soft reset!\n");
848 
849 	return ret;
850 }
851 
852 /* program default register values */
ov6650_prog_dflt(struct i2c_client * client,u8 clkrc)853 static int ov6650_prog_dflt(struct i2c_client *client, u8 clkrc)
854 {
855 	int ret;
856 
857 	dev_dbg(&client->dev, "initializing\n");
858 
859 	ret = ov6650_reg_write(client, REG_COMA, 0);	/* ~COMA_RESET */
860 	if (!ret)
861 		ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
862 	if (!ret)
863 		ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
864 
865 	return ret;
866 }
867 
ov6650_video_probe(struct v4l2_subdev * sd)868 static int ov6650_video_probe(struct v4l2_subdev *sd)
869 {
870 	struct i2c_client *client = v4l2_get_subdevdata(sd);
871 	struct ov6650 *priv = to_ov6650(client);
872 	const struct ov6650_xclk *xclk = NULL;
873 	unsigned long rate;
874 	u8 pidh, pidl, midh, midl;
875 	int i, ret = 0;
876 
877 	priv->clk = devm_clk_get(&client->dev, NULL);
878 	if (IS_ERR(priv->clk)) {
879 		ret = PTR_ERR(priv->clk);
880 		dev_err(&client->dev, "clk request err: %d\n", ret);
881 		return ret;
882 	}
883 
884 	rate = clk_get_rate(priv->clk);
885 	for (i = 0; rate && i < ARRAY_SIZE(ov6650_xclk); i++) {
886 		if (rate != ov6650_xclk[i].rate)
887 			continue;
888 
889 		xclk = &ov6650_xclk[i];
890 		dev_info(&client->dev, "using host default clock rate %lukHz\n",
891 			 rate / 1000);
892 		break;
893 	}
894 	for (i = 0; !xclk && i < ARRAY_SIZE(ov6650_xclk); i++) {
895 		ret = clk_set_rate(priv->clk, ov6650_xclk[i].rate);
896 		if (ret || clk_get_rate(priv->clk) != ov6650_xclk[i].rate)
897 			continue;
898 
899 		xclk = &ov6650_xclk[i];
900 		dev_info(&client->dev, "using negotiated clock rate %lukHz\n",
901 			 xclk->rate / 1000);
902 		break;
903 	}
904 	if (!xclk) {
905 		dev_err(&client->dev, "unable to get supported clock rate\n");
906 		if (!ret)
907 			ret = -EINVAL;
908 		return ret;
909 	}
910 
911 	ret = ov6650_s_power(sd, 1);
912 	if (ret < 0)
913 		return ret;
914 
915 	msleep(20);
916 
917 	/*
918 	 * check and show product ID and manufacturer ID
919 	 */
920 	ret = ov6650_reg_read(client, REG_PIDH, &pidh);
921 	if (!ret)
922 		ret = ov6650_reg_read(client, REG_PIDL, &pidl);
923 	if (!ret)
924 		ret = ov6650_reg_read(client, REG_MIDH, &midh);
925 	if (!ret)
926 		ret = ov6650_reg_read(client, REG_MIDL, &midl);
927 
928 	if (ret)
929 		goto done;
930 
931 	if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
932 		dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
933 				pidh, pidl);
934 		ret = -ENODEV;
935 		goto done;
936 	}
937 
938 	dev_info(&client->dev,
939 		"ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
940 		pidh, pidl, midh, midl);
941 
942 	ret = ov6650_reset(client);
943 	if (!ret)
944 		ret = ov6650_prog_dflt(client, xclk->clkrc);
945 	if (!ret) {
946 		/* driver default frame format, no scaling */
947 		ret = ov6650_s_fmt(sd, ov6650_def_fmt.code, false);
948 	}
949 	if (!ret)
950 		ret = v4l2_ctrl_handler_setup(&priv->hdl);
951 
952 done:
953 	ov6650_s_power(sd, 0);
954 	return ret;
955 }
956 
957 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
958 	.g_volatile_ctrl = ov6550_g_volatile_ctrl,
959 	.s_ctrl = ov6550_s_ctrl,
960 };
961 
962 static const struct v4l2_subdev_core_ops ov6650_core_ops = {
963 #ifdef CONFIG_VIDEO_ADV_DEBUG
964 	.g_register		= ov6650_get_register,
965 	.s_register		= ov6650_set_register,
966 #endif
967 	.s_power		= ov6650_s_power,
968 };
969 
970 /* Request bus settings on camera side */
ov6650_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)971 static int ov6650_get_mbus_config(struct v4l2_subdev *sd,
972 				  unsigned int pad,
973 				  struct v4l2_mbus_config *cfg)
974 {
975 	struct i2c_client *client = v4l2_get_subdevdata(sd);
976 	u8 comj, comf;
977 	int ret;
978 
979 	ret = ov6650_reg_read(client, REG_COMJ, &comj);
980 	if (ret)
981 		return ret;
982 
983 	ret = ov6650_reg_read(client, REG_COMF, &comf);
984 	if (ret)
985 		return ret;
986 
987 	cfg->type = V4L2_MBUS_PARALLEL;
988 
989 	cfg->bus.parallel.flags = V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH
990 		| ((comj & COMJ_VSYNC_HIGH)  ? V4L2_MBUS_VSYNC_ACTIVE_HIGH
991 					     : V4L2_MBUS_VSYNC_ACTIVE_LOW)
992 		| ((comf & COMF_HREF_LOW)    ? V4L2_MBUS_HSYNC_ACTIVE_LOW
993 					     : V4L2_MBUS_HSYNC_ACTIVE_HIGH)
994 		| ((comj & COMJ_PCLK_RISING) ? V4L2_MBUS_PCLK_SAMPLE_RISING
995 					     : V4L2_MBUS_PCLK_SAMPLE_FALLING);
996 	return 0;
997 }
998 
999 static const struct v4l2_subdev_video_ops ov6650_video_ops = {
1000 	.s_stream	= ov6650_s_stream,
1001 	.g_frame_interval = ov6650_g_frame_interval,
1002 	.s_frame_interval = ov6650_s_frame_interval,
1003 };
1004 
1005 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
1006 	.enum_mbus_code		= ov6650_enum_mbus_code,
1007 	.enum_frame_interval	= ov6650_enum_frame_interval,
1008 	.get_selection		= ov6650_get_selection,
1009 	.set_selection		= ov6650_set_selection,
1010 	.get_fmt		= ov6650_get_fmt,
1011 	.set_fmt		= ov6650_set_fmt,
1012 	.get_mbus_config	= ov6650_get_mbus_config,
1013 };
1014 
1015 static const struct v4l2_subdev_ops ov6650_subdev_ops = {
1016 	.core	= &ov6650_core_ops,
1017 	.video	= &ov6650_video_ops,
1018 	.pad	= &ov6650_pad_ops,
1019 };
1020 
1021 static const struct v4l2_subdev_internal_ops ov6650_internal_ops = {
1022 	.registered = ov6650_video_probe,
1023 };
1024 
1025 /*
1026  * i2c_driver function
1027  */
ov6650_probe(struct i2c_client * client)1028 static int ov6650_probe(struct i2c_client *client)
1029 {
1030 	struct ov6650 *priv;
1031 	int ret;
1032 
1033 	priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1034 	if (!priv)
1035 		return -ENOMEM;
1036 
1037 	v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
1038 	v4l2_ctrl_handler_init(&priv->hdl, 13);
1039 	v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1040 			V4L2_CID_VFLIP, 0, 1, 1, 0);
1041 	v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1042 			V4L2_CID_HFLIP, 0, 1, 1, 0);
1043 	priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1044 			V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1045 	priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1046 			V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
1047 	priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1048 			V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1049 	priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1050 			V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
1051 	priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1052 			V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
1053 	v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1054 			V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
1055 	v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1056 			V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1057 	v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1058 			V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1059 	priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
1060 			&ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1061 			V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1062 	priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1063 			V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1064 	v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1065 			V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1066 
1067 	priv->subdev.ctrl_handler = &priv->hdl;
1068 	if (priv->hdl.error) {
1069 		ret = priv->hdl.error;
1070 		goto ectlhdlfree;
1071 	}
1072 
1073 	v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1074 	v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1075 	v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1076 				V4L2_EXPOSURE_MANUAL, true);
1077 
1078 	priv->rect.left	  = DEF_HSTRT << 1;
1079 	priv->rect.top	  = DEF_VSTRT << 1;
1080 	priv->rect.width  = W_CIF;
1081 	priv->rect.height = H_CIF;
1082 
1083 	/* Hardware default frame interval */
1084 	priv->tpf.numerator   = GET_CLKRC_DIV(DEF_CLKRC);
1085 	priv->tpf.denominator = FRAME_RATE_MAX;
1086 
1087 	priv->subdev.internal_ops = &ov6650_internal_ops;
1088 
1089 	ret = v4l2_async_register_subdev(&priv->subdev);
1090 	if (!ret)
1091 		return 0;
1092 ectlhdlfree:
1093 	v4l2_ctrl_handler_free(&priv->hdl);
1094 
1095 	return ret;
1096 }
1097 
ov6650_remove(struct i2c_client * client)1098 static void ov6650_remove(struct i2c_client *client)
1099 {
1100 	struct ov6650 *priv = to_ov6650(client);
1101 
1102 	v4l2_async_unregister_subdev(&priv->subdev);
1103 	v4l2_ctrl_handler_free(&priv->hdl);
1104 }
1105 
1106 static const struct i2c_device_id ov6650_id[] = {
1107 	{ "ov6650", 0 },
1108 	{ }
1109 };
1110 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1111 
1112 static struct i2c_driver ov6650_i2c_driver = {
1113 	.driver = {
1114 		.name = "ov6650",
1115 	},
1116 	.probe    = ov6650_probe,
1117 	.remove   = ov6650_remove,
1118 	.id_table = ov6650_id,
1119 };
1120 
1121 module_i2c_driver(ov6650_i2c_driver);
1122 
1123 MODULE_DESCRIPTION("V4L2 subdevice driver for OmniVision OV6650 camera sensor");
1124 MODULE_AUTHOR("Janusz Krzysztofik <jmkrzyszt@gmail.com");
1125 MODULE_LICENSE("GPL v2");
1126