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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci.txt7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
10 turned off, before applying sdhci-caps.
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
12 property corresponds to the bits in the sdhci capability register. If the
H A Dsdhci-common.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SDHCI Controller Common Properties
10 - Adrian Hunter <adrian.hunter@intel.com>
13 Common properties present on Secure Digital Host Controller Interface (SDHCI)
17 sdhci-caps:
20 Additionally present SDHCI capabilities - values for SDHCI_CAPABILITIES
23 sdhci-caps-mask:
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H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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/openbmc/linux/drivers/mmc/host/
H A Dsdhci-npcm.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include "sdhci-pltfm.h"
34 struct device *dev = &pdev->dev; in npcm_sdhci_probe()
36 u32 caps; in npcm_sdhci_probe() local
41 return -EINVAL; in npcm_sdhci_probe()
49 pltfm_host->clk = devm_clk_get_optional_enabled(dev, NULL); in npcm_sdhci_probe()
50 if (IS_ERR(pltfm_host->clk)) { in npcm_sdhci_probe()
51 ret = PTR_ERR(pltfm_host->clk); in npcm_sdhci_probe()
55 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in npcm_sdhci_probe()
56 if (caps & SDHCI_CAN_DO_8BIT) in npcm_sdhci_probe()
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H A Dsdhci-iproc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * iProc SDHCI platform driver
14 #include "sdhci-pltfm.h"
18 u32 caps; member
36 u32 val = readl(host->ioaddr + reg); in sdhci_iproc_readl()
39 mmc_hostname(host->mmc), reg, val); in sdhci_iproc_readl()
50 if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) { in sdhci_iproc_readw()
52 val = iproc_host->shadow_cmd; in sdhci_iproc_readw()
54 iproc_host->is_blk_shadowed) { in sdhci_iproc_readw()
56 val = iproc_host->shadow_blk; in sdhci_iproc_readw()
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H A Dsdhci-omap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SDHCI Controller driver for TI's OMAP SoCs
11 #include <linux/mmc/slot-gpio.h>
23 #include "sdhci-pltfm.h"
97 /* sdhci-omap controller flags */
103 u32 offset; /* Offset for SDHCI regs from base */
142 return readl(host->base + host->omap_offset + offset); in sdhci_omap_readl()
148 writel(data, host->base + host->omap_offset + offset); in sdhci_omap_writel()
155 struct device *dev = omap_host->dev; in sdhci_omap_set_pbias()
157 if (IS_ERR(omap_host->pbias)) in sdhci_omap_set_pbias()
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H A Dsdhci-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
15 #include "sdhci-cqhci.h"
16 #include "sdhci-pltfm.h"
62 /* Reset will clear this, so re-enable it */ in brcmstb_reset()
63 if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) in brcmstb_reset()
73 dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", in sdhci_brcmstb_hs400es()
75 reg = readl(host->ioaddr + SDHCI_VENDOR); in sdhci_brcmstb_hs400es()
76 if (ios->enhanced_strobe) in sdhci_brcmstb_hs400es()
80 writel(reg, host->ioaddr + SDHCI_VENDOR); in sdhci_brcmstb_hs400es()
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H A Dsdhci-pic32.c2 * Support of SDHCI platform devices for Microchip PIC32.
7 * Inspired by sdhci-pltfm.c
26 #include "sdhci.h"
27 #include "sdhci-pltfm.h"
28 #include <linux/platform_data/sdhci-pic32.h>
55 return clk_get_rate(sdhci_pdata->base_clk); in pic32_sdhci_get_max_clock()
65 if (host->version >= SDHCI_SPEC_300) in pic32_sdhci_set_bus_width()
68 if (host->version >= SDHCI_SPEC_300) in pic32_sdhci_set_bus_width()
109 u32 bus = readl(host->ioaddr + SDH_SHARED_BUS_CTRL); in pic32_sdhci_shared_bus()
121 writel(bus, host->ioaddr + SDH_SHARED_BUS_CTRL); in pic32_sdhci_shared_bus()
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H A Dsdhci-pxav3.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include "sdhci.h"
28 #include "sdhci-pltfm.h"
80 dev_err(&pdev->dev, "no mbus dram info\n"); in mv_conf_mbus_windows()
81 return -EINVAL; in mv_conf_mbus_windows()
86 dev_err(&pdev->dev, "cannot get mbus registers\n"); in mv_conf_mbus_windows()
87 return -EINVAL; in mv_conf_mbus_windows()
90 regs = ioremap(res->start, resource_size(res)); in mv_conf_mbus_windows()
92 dev_err(&pdev->dev, "cannot map mbus registers\n"); in mv_conf_mbus_windows()
93 return -ENOMEM; in mv_conf_mbus_windows()
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H A Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
9 * SDHCI (HSMMC) support for Samsung SoC
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
29 #include "sdhci.h"
104 * struct sdhci_s3c - S3C SDHCI instance
105 * @host: The SDHCI host created
114 * @no_divider: No or non-standard internal clock divider.
132 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
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H A Dsdhci-st.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for SDHCI on STMicroelectronics SoCs
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
102 /* register to provide the phase-shift value for DLL */
119 * DLL procedure has finished before switching to ultra-speed modes.
136 * @host: sdhci host
139 * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
140 * or eMMC4.3. This has to be done before registering the sdhci host.
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H A Dsdhci-of-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/mmc/slot-gpio.h>
24 #include "sdhci-pltfm.h"
57 mc1r = readb(host->ioaddr + SDMMC_MC1R); in sdhci_at91_set_force_card_detect()
59 writeb(mc1r, host->ioaddr + SDMMC_MC1R); in sdhci_at91_set_force_card_detect()
66 host->mmc->actual_clock = 0; in sdhci_at91_set_clock()
71 * internal clock, changing the configuration and re-enabling the in sdhci_at91_set_clock()
83 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_at91_set_clock()
92 mmc_hostname(host->mmc)); in sdhci_at91_set_clock()
121 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_at91_reset()
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H A Dsdhci-pxav2.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #include "sdhci.h"
27 #include "sdhci-pltfm.h"
55 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); in pxav2_reset()
56 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; in pxav2_reset()
67 if (pdata && pdata->clk_delay_sel == 1) { in pxav2_reset()
68 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
71 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) in pxav2_reset()
76 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
79 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) { in pxav2_reset()
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H A Dsdhci-acpi.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/dma-mapping.h>
32 #include <linux/mmc/slot-gpio.h>
39 #include "sdhci.h"
51 unsigned long caps; member
60 unsigned long caps; member
90 return (void *)c->private; in sdhci_acpi_priv()
95 return c->slot && (c->slot->flags & flag); in sdhci_acpi_flag()
127 return -EOPNOTSUPP; in __intel_dsm()
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H A Dsdhci_am654.c1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
111 "ti,itap-del-sel-mmc-hs",
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H A Dsdhci-esdhc-mcf.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/platform_data/mmc-esdhc-mcf.h>
13 #include "sdhci-pltfm.h"
14 #include "sdhci-esdhc.h"
49 void __iomem *base = host->ioaddr + (reg & ~3); in esdhc_clrset_be()
62 * Note: mcf is big-endian, single bytes need to be accessed at big endian
67 void __iomem *base = host->ioaddr + (reg & ~3); in esdhc_mcf_writeb_be()
74 u8 tmp = readb(host->ioaddr + SDHCI_HOST_CONTROL + 1); in esdhc_mcf_writeb_be()
85 writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_mcf_writeb_be()
97 void __iomem *base = host->ioaddr + (reg & ~3); in esdhc_mcf_writew_be()
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H A Dsdhci-bcm-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
17 #include "sdhci.h"
63 return -EFAULT; in sdhci_bcm_kona_sd_reset()
72 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
73 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
74 * is very low w.r.t AHB clock, mainly during boot-time and during card in sdhci_bcm_kona_sd_reset()
75 * insert-removal. in sdhci_bcm_kona_sd_reset()
97 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_init()
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H A Dsdhci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
9 * - JMicron (hardware and technical support)
19 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
35 #include "sdhci.h"
37 #define DRIVER_NAME "sdhci"
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
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H A Dsdhci-pci-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
8 * - JMicron (hardware and technical support)
17 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
41 #include "sdhci.h"
42 #include "sdhci-cqhci.h"
43 #include "sdhci-pci.h"
54 for (i = 0; i < chip->num_slots; i++) { in sdhci_pci_init_wakeup()
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H A Dsdhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
20 #include <linux/mmc/slot-gpio.h>
32 #include "sdhci-cqhci.h"
33 #include "sdhci-pltf
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H A Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
22 #include "sdhci-pltfm.h"
23 #include "sdhci-xenon.h"
42 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
43 return -ETIMEDOUT; in xenon_enable_internal_clk()
51 /* Set SDCLK-off-while-idle */
92 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
97 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
138 /* Disable the Re-Tuning Request functionality */ in xenon_retune_setup()
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H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
101 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
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/openbmc/u-boot/drivers/mmc/
H A Dmsm_sdhci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Qualcomm SDHCI driver - SD/eMMC controller
13 #include <sdhci.h>
18 /* Non-standard registers needed for SDHCI startup */
32 /* Offset to SDHCI registers */
35 /* Non standard (?) SDHCI register */
53 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency", in msm_sdc_clk_init()
61 ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2); in msm_sdc_clk_init()
65 clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); in msm_sdc_clk_init()
91 struct sdhci_host *host = &prv->host; in msm_sdc_probe()
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654-base-board-u-boot.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/pinctrl/k3-am65.h>
10 stdout-path = "serial2:115200n8";
19 u-boot,dm-spl;
22 compatible = "pinctrl-single";
24 #pinctrl-cells = <1>;
25 pinctrl-single,register-width = <32>;
26 pinctrl-single,function-mask = <0xffffffff>;
30 compatible = "pinctrl-single";
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