12aec85b2SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
22aec85b2SThomas Gleixner // Copyright (C) 2014 Broadcom Corporation
3b580c52dSScott Branden
4b580c52dSScott Branden /*
5b580c52dSScott Branden * iProc SDHCI platform driver
6b580c52dSScott Branden */
7b580c52dSScott Branden
87c7ba433SSrinath Mannam #include <linux/acpi.h>
9b580c52dSScott Branden #include <linux/delay.h>
10b580c52dSScott Branden #include <linux/module.h>
11b580c52dSScott Branden #include <linux/mmc/host.h>
12b580c52dSScott Branden #include <linux/of.h>
13c62da8a8SRob Herring #include <linux/platform_device.h>
14b580c52dSScott Branden #include "sdhci-pltfm.h"
15b580c52dSScott Branden
16b580c52dSScott Branden struct sdhci_iproc_data {
17b580c52dSScott Branden const struct sdhci_pltfm_data *pdata;
18b580c52dSScott Branden u32 caps;
19b580c52dSScott Branden u32 caps1;
20b17b4ab8SStefan Wahren u32 mmc_caps;
21f3200164SAdrian Hunter bool missing_caps;
22b580c52dSScott Branden };
23b580c52dSScott Branden
24b580c52dSScott Branden struct sdhci_iproc_host {
25b580c52dSScott Branden const struct sdhci_iproc_data *data;
26b580c52dSScott Branden u32 shadow_cmd;
27b580c52dSScott Branden u32 shadow_blk;
285f651b87SCorneliu Doban bool is_cmd_shadowed;
295f651b87SCorneliu Doban bool is_blk_shadowed;
30b580c52dSScott Branden };
31b580c52dSScott Branden
32b580c52dSScott Branden #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
33b580c52dSScott Branden
sdhci_iproc_readl(struct sdhci_host * host,int reg)34b580c52dSScott Branden static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
35b580c52dSScott Branden {
36b580c52dSScott Branden u32 val = readl(host->ioaddr + reg);
37b580c52dSScott Branden
38b580c52dSScott Branden pr_debug("%s: readl [0x%02x] 0x%08x\n",
39b580c52dSScott Branden mmc_hostname(host->mmc), reg, val);
40b580c52dSScott Branden return val;
41b580c52dSScott Branden }
42b580c52dSScott Branden
sdhci_iproc_readw(struct sdhci_host * host,int reg)43b580c52dSScott Branden static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
44b580c52dSScott Branden {
455f651b87SCorneliu Doban struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
465f651b87SCorneliu Doban struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
475f651b87SCorneliu Doban u32 val;
485f651b87SCorneliu Doban u16 word;
495f651b87SCorneliu Doban
505f651b87SCorneliu Doban if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
515f651b87SCorneliu Doban /* Get the saved transfer mode */
525f651b87SCorneliu Doban val = iproc_host->shadow_cmd;
535f651b87SCorneliu Doban } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
545f651b87SCorneliu Doban iproc_host->is_blk_shadowed) {
555f651b87SCorneliu Doban /* Get the saved block info */
565f651b87SCorneliu Doban val = iproc_host->shadow_blk;
575f651b87SCorneliu Doban } else {
585f651b87SCorneliu Doban val = sdhci_iproc_readl(host, (reg & ~3));
595f651b87SCorneliu Doban }
605f651b87SCorneliu Doban word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
61b580c52dSScott Branden return word;
62b580c52dSScott Branden }
63b580c52dSScott Branden
sdhci_iproc_readb(struct sdhci_host * host,int reg)64b580c52dSScott Branden static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
65b580c52dSScott Branden {
66b580c52dSScott Branden u32 val = sdhci_iproc_readl(host, (reg & ~3));
67b580c52dSScott Branden u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
68b580c52dSScott Branden return byte;
69b580c52dSScott Branden }
70b580c52dSScott Branden
sdhci_iproc_writel(struct sdhci_host * host,u32 val,int reg)71b580c52dSScott Branden static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
72b580c52dSScott Branden {
73b580c52dSScott Branden pr_debug("%s: writel [0x%02x] 0x%08x\n",
74b580c52dSScott Branden mmc_hostname(host->mmc), reg, val);
75b580c52dSScott Branden
76b580c52dSScott Branden writel(val, host->ioaddr + reg);
77b580c52dSScott Branden
78b580c52dSScott Branden if (host->clock <= 400000) {
79b580c52dSScott Branden /* Round up to micro-second four SD clock delay */
80b580c52dSScott Branden if (host->clock)
81b580c52dSScott Branden udelay((4 * 1000000 + host->clock - 1) / host->clock);
82b580c52dSScott Branden else
83b580c52dSScott Branden udelay(10);
84b580c52dSScott Branden }
85b580c52dSScott Branden }
86b580c52dSScott Branden
87b580c52dSScott Branden /*
88b580c52dSScott Branden * The Arasan has a bugette whereby it may lose the content of successive
89b580c52dSScott Branden * writes to the same register that are within two SD-card clock cycles of
90b580c52dSScott Branden * each other (a clock domain crossing problem). The data
91b580c52dSScott Branden * register does not have this problem, which is just as well - otherwise we'd
92b580c52dSScott Branden * have to nobble the DMA engine too.
93b580c52dSScott Branden *
94b580c52dSScott Branden * This wouldn't be a problem with the code except that we can only write the
95b580c52dSScott Branden * controller with 32-bit writes. So two different 16-bit registers are
96b580c52dSScott Branden * written back to back creates the problem.
97b580c52dSScott Branden *
98b580c52dSScott Branden * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
99b580c52dSScott Branden * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
100b580c52dSScott Branden * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
101b580c52dSScott Branden * the work around can be further optimized. We can keep shadow values of
102b580c52dSScott Branden * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
103b580c52dSScott Branden * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
104b580c52dSScott Branden * by the TRANSFER+COMMAND in another 32-bit write.
105b580c52dSScott Branden */
sdhci_iproc_writew(struct sdhci_host * host,u16 val,int reg)106b580c52dSScott Branden static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
107b580c52dSScott Branden {
108b580c52dSScott Branden struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
109b1ddaa3dSDmitry Torokhov struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
110b580c52dSScott Branden u32 word_shift = REG_OFFSET_IN_BITS(reg);
111b580c52dSScott Branden u32 mask = 0xffff << word_shift;
112b580c52dSScott Branden u32 oldval, newval;
113b580c52dSScott Branden
114b580c52dSScott Branden if (reg == SDHCI_COMMAND) {
115b580c52dSScott Branden /* Write the block now as we are issuing a command */
1165f651b87SCorneliu Doban if (iproc_host->is_blk_shadowed) {
117b580c52dSScott Branden sdhci_iproc_writel(host, iproc_host->shadow_blk,
118b580c52dSScott Branden SDHCI_BLOCK_SIZE);
1195f651b87SCorneliu Doban iproc_host->is_blk_shadowed = false;
120b580c52dSScott Branden }
121b580c52dSScott Branden oldval = iproc_host->shadow_cmd;
1225f651b87SCorneliu Doban iproc_host->is_cmd_shadowed = false;
1235f651b87SCorneliu Doban } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
1245f651b87SCorneliu Doban iproc_host->is_blk_shadowed) {
125b580c52dSScott Branden /* Block size and count are stored in shadow reg */
126b580c52dSScott Branden oldval = iproc_host->shadow_blk;
127b580c52dSScott Branden } else {
128b580c52dSScott Branden /* Read reg, all other registers are not shadowed */
129b580c52dSScott Branden oldval = sdhci_iproc_readl(host, (reg & ~3));
130b580c52dSScott Branden }
131b580c52dSScott Branden newval = (oldval & ~mask) | (val << word_shift);
132b580c52dSScott Branden
133b580c52dSScott Branden if (reg == SDHCI_TRANSFER_MODE) {
134b580c52dSScott Branden /* Save the transfer mode until the command is issued */
135b580c52dSScott Branden iproc_host->shadow_cmd = newval;
1365f651b87SCorneliu Doban iproc_host->is_cmd_shadowed = true;
137b580c52dSScott Branden } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
138b580c52dSScott Branden /* Save the block info until the command is issued */
139b580c52dSScott Branden iproc_host->shadow_blk = newval;
1405f651b87SCorneliu Doban iproc_host->is_blk_shadowed = true;
141b580c52dSScott Branden } else {
142b580c52dSScott Branden /* Command or other regular 32-bit write */
143b580c52dSScott Branden sdhci_iproc_writel(host, newval, reg & ~3);
144b580c52dSScott Branden }
145b580c52dSScott Branden }
146b580c52dSScott Branden
sdhci_iproc_writeb(struct sdhci_host * host,u8 val,int reg)147b580c52dSScott Branden static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
148b580c52dSScott Branden {
149b580c52dSScott Branden u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
150b580c52dSScott Branden u32 byte_shift = REG_OFFSET_IN_BITS(reg);
151b580c52dSScott Branden u32 mask = 0xff << byte_shift;
152b580c52dSScott Branden u32 newval = (oldval & ~mask) | (val << byte_shift);
153b580c52dSScott Branden
154b580c52dSScott Branden sdhci_iproc_writel(host, newval, reg & ~3);
155b580c52dSScott Branden }
156b580c52dSScott Branden
sdhci_iproc_get_max_clock(struct sdhci_host * host)1577c7ba433SSrinath Mannam static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
1587c7ba433SSrinath Mannam {
1597c7ba433SSrinath Mannam struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1607c7ba433SSrinath Mannam
1617c7ba433SSrinath Mannam if (pltfm_host->clk)
1627c7ba433SSrinath Mannam return sdhci_pltfm_clk_get_max_clock(host);
1637c7ba433SSrinath Mannam else
1647c7ba433SSrinath Mannam return pltfm_host->clock;
1657c7ba433SSrinath Mannam }
1667c7ba433SSrinath Mannam
167c9107dd0SNicolas Saenz Julienne /*
168c9107dd0SNicolas Saenz Julienne * There is a known bug on BCM2711's SDHCI core integration where the
169c9107dd0SNicolas Saenz Julienne * controller will hang when the difference between the core clock and the bus
170c9107dd0SNicolas Saenz Julienne * clock is too great. Specifically this can be reproduced under the following
171c9107dd0SNicolas Saenz Julienne * conditions:
172c9107dd0SNicolas Saenz Julienne *
173c9107dd0SNicolas Saenz Julienne * - No SD card plugged in, polling thread is running, probing cards at
174c9107dd0SNicolas Saenz Julienne * 100 kHz.
175c9107dd0SNicolas Saenz Julienne * - BCM2711's core clock configured at 500MHz or more
176c9107dd0SNicolas Saenz Julienne *
177c9107dd0SNicolas Saenz Julienne * So we set 200kHz as the minimum clock frequency available for that SoC.
178c9107dd0SNicolas Saenz Julienne */
sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host * host)179c9107dd0SNicolas Saenz Julienne static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
180c9107dd0SNicolas Saenz Julienne {
181c9107dd0SNicolas Saenz Julienne return 200000;
182c9107dd0SNicolas Saenz Julienne }
183c9107dd0SNicolas Saenz Julienne
184b580c52dSScott Branden static const struct sdhci_ops sdhci_iproc_ops = {
185c833e92bSScott Branden .set_clock = sdhci_set_clock,
1867c7ba433SSrinath Mannam .get_max_clock = sdhci_iproc_get_max_clock,
187c833e92bSScott Branden .set_bus_width = sdhci_set_bus_width,
188c833e92bSScott Branden .reset = sdhci_reset,
189c833e92bSScott Branden .set_uhs_signaling = sdhci_set_uhs_signaling,
190c833e92bSScott Branden };
191c833e92bSScott Branden
192c833e92bSScott Branden static const struct sdhci_ops sdhci_iproc_32only_ops = {
193b580c52dSScott Branden .read_l = sdhci_iproc_readl,
194b580c52dSScott Branden .read_w = sdhci_iproc_readw,
195b580c52dSScott Branden .read_b = sdhci_iproc_readb,
196b580c52dSScott Branden .write_l = sdhci_iproc_writel,
197b580c52dSScott Branden .write_w = sdhci_iproc_writew,
198b580c52dSScott Branden .write_b = sdhci_iproc_writeb,
199b580c52dSScott Branden .set_clock = sdhci_set_clock,
2007c7ba433SSrinath Mannam .get_max_clock = sdhci_iproc_get_max_clock,
201b580c52dSScott Branden .set_bus_width = sdhci_set_bus_width,
202b580c52dSScott Branden .reset = sdhci_reset,
203b580c52dSScott Branden .set_uhs_signaling = sdhci_set_uhs_signaling,
204b580c52dSScott Branden };
205b580c52dSScott Branden
206c833e92bSScott Branden static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
207b7dfa695STrac Hoang .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
208b7dfa695STrac Hoang SDHCI_QUIRK_NO_HISPD_BIT,
2093de06d5aSCorneliu Doban .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
210c833e92bSScott Branden .ops = &sdhci_iproc_32only_ops,
211c833e92bSScott Branden };
212c833e92bSScott Branden
213c833e92bSScott Branden static const struct sdhci_iproc_data iproc_cygnus_data = {
214c833e92bSScott Branden .pdata = &sdhci_iproc_cygnus_pltfm_data,
215c833e92bSScott Branden .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
216c833e92bSScott Branden & SDHCI_MAX_BLOCK_MASK) |
217c833e92bSScott Branden SDHCI_CAN_VDD_330 |
218c833e92bSScott Branden SDHCI_CAN_VDD_180 |
219c833e92bSScott Branden SDHCI_CAN_DO_SUSPEND |
220c833e92bSScott Branden SDHCI_CAN_DO_HISPD |
221c833e92bSScott Branden SDHCI_CAN_DO_ADMA2 |
222c833e92bSScott Branden SDHCI_CAN_DO_SDMA,
223c833e92bSScott Branden .caps1 = SDHCI_DRIVER_TYPE_C |
224c833e92bSScott Branden SDHCI_DRIVER_TYPE_D |
225c833e92bSScott Branden SDHCI_SUPPORT_DDR50,
226c833e92bSScott Branden .mmc_caps = MMC_CAP_1_8V_DDR,
227c833e92bSScott Branden };
228c833e92bSScott Branden
229b580c52dSScott Branden static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
230f5f968f2SSrinath Mannam .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
231ec0970e0STrac Hoang SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
232ec0970e0STrac Hoang SDHCI_QUIRK_NO_HISPD_BIT,
233b580c52dSScott Branden .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
234b580c52dSScott Branden .ops = &sdhci_iproc_ops,
235b580c52dSScott Branden };
236b580c52dSScott Branden
237b580c52dSScott Branden static const struct sdhci_iproc_data iproc_data = {
238b580c52dSScott Branden .pdata = &sdhci_iproc_pltfm_data,
2391883edd1SStefan Wahren .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
2401883edd1SStefan Wahren & SDHCI_MAX_BLOCK_MASK) |
2411883edd1SStefan Wahren SDHCI_CAN_VDD_330 |
2421883edd1SStefan Wahren SDHCI_CAN_VDD_180 |
2431883edd1SStefan Wahren SDHCI_CAN_DO_SUSPEND |
2441883edd1SStefan Wahren SDHCI_CAN_DO_HISPD |
2451883edd1SStefan Wahren SDHCI_CAN_DO_ADMA2 |
2461883edd1SStefan Wahren SDHCI_CAN_DO_SDMA,
2471883edd1SStefan Wahren .caps1 = SDHCI_DRIVER_TYPE_C |
2481883edd1SStefan Wahren SDHCI_DRIVER_TYPE_D |
2491883edd1SStefan Wahren SDHCI_SUPPORT_DDR50,
250b580c52dSScott Branden };
251b580c52dSScott Branden
25277cb7d3aSStefan Wahren static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
25377cb7d3aSStefan Wahren .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
25477cb7d3aSStefan Wahren SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
255c82c2775SStefan Wahren SDHCI_QUIRK_NO_HISPD_BIT,
2567f7a385dSStefan Wahren .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
257c833e92bSScott Branden .ops = &sdhci_iproc_32only_ops,
25877cb7d3aSStefan Wahren };
25977cb7d3aSStefan Wahren
26077cb7d3aSStefan Wahren static const struct sdhci_iproc_data bcm2835_data = {
26177cb7d3aSStefan Wahren .pdata = &sdhci_bcm2835_pltfm_data,
26240165de2SStefan Wahren .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
26340165de2SStefan Wahren & SDHCI_MAX_BLOCK_MASK) |
26440165de2SStefan Wahren SDHCI_CAN_VDD_330 |
265c82c2775SStefan Wahren SDHCI_CAN_DO_HISPD,
266c82c2775SStefan Wahren .caps1 = SDHCI_DRIVER_TYPE_A |
267c82c2775SStefan Wahren SDHCI_DRIVER_TYPE_C,
26877cb7d3aSStefan Wahren .mmc_caps = 0x00000000,
269f3200164SAdrian Hunter .missing_caps = true,
27077cb7d3aSStefan Wahren };
27177cb7d3aSStefan Wahren
272f87391eeSNicolas Saenz Julienne static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
273f87391eeSNicolas Saenz Julienne .read_l = sdhci_iproc_readl,
274f87391eeSNicolas Saenz Julienne .read_w = sdhci_iproc_readw,
275f87391eeSNicolas Saenz Julienne .read_b = sdhci_iproc_readb,
276f87391eeSNicolas Saenz Julienne .write_l = sdhci_iproc_writel,
277f87391eeSNicolas Saenz Julienne .write_w = sdhci_iproc_writew,
278f87391eeSNicolas Saenz Julienne .write_b = sdhci_iproc_writeb,
279f87391eeSNicolas Saenz Julienne .set_clock = sdhci_set_clock,
280f87391eeSNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage,
281f87391eeSNicolas Saenz Julienne .get_max_clock = sdhci_iproc_get_max_clock,
282c9107dd0SNicolas Saenz Julienne .get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
283f87391eeSNicolas Saenz Julienne .set_bus_width = sdhci_set_bus_width,
284f87391eeSNicolas Saenz Julienne .reset = sdhci_reset,
285f87391eeSNicolas Saenz Julienne .set_uhs_signaling = sdhci_set_uhs_signaling,
286f87391eeSNicolas Saenz Julienne };
287f87391eeSNicolas Saenz Julienne
288f84e411cSStefan Wahren static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
289885814a9SUlf Hansson .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
290f87391eeSNicolas Saenz Julienne .ops = &sdhci_iproc_bcm2711_ops,
291f84e411cSStefan Wahren };
292f84e411cSStefan Wahren
293f84e411cSStefan Wahren static const struct sdhci_iproc_data bcm2711_data = {
294f84e411cSStefan Wahren .pdata = &sdhci_bcm2711_pltfm_data,
2958d62fa83SStefan Wahren .mmc_caps = MMC_CAP_3_3V_DDR,
296f84e411cSStefan Wahren };
297f84e411cSStefan Wahren
29898b5ce4cSAl Cooper static const struct sdhci_pltfm_data sdhci_bcm7211a0_pltfm_data = {
299f3200164SAdrian Hunter .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
30098b5ce4cSAl Cooper SDHCI_QUIRK_BROKEN_DMA |
30198b5ce4cSAl Cooper SDHCI_QUIRK_BROKEN_ADMA,
30298b5ce4cSAl Cooper .ops = &sdhci_iproc_ops,
30398b5ce4cSAl Cooper };
30498b5ce4cSAl Cooper
30598b5ce4cSAl Cooper #define BCM7211A0_BASE_CLK_MHZ 100
30698b5ce4cSAl Cooper static const struct sdhci_iproc_data bcm7211a0_data = {
30798b5ce4cSAl Cooper .pdata = &sdhci_bcm7211a0_pltfm_data,
30898b5ce4cSAl Cooper .caps = ((BCM7211A0_BASE_CLK_MHZ / 2) << SDHCI_TIMEOUT_CLK_SHIFT) |
30998b5ce4cSAl Cooper (BCM7211A0_BASE_CLK_MHZ << SDHCI_CLOCK_BASE_SHIFT) |
31098b5ce4cSAl Cooper ((0x2 << SDHCI_MAX_BLOCK_SHIFT)
31198b5ce4cSAl Cooper & SDHCI_MAX_BLOCK_MASK) |
31298b5ce4cSAl Cooper SDHCI_CAN_VDD_330 |
31398b5ce4cSAl Cooper SDHCI_CAN_VDD_180 |
31498b5ce4cSAl Cooper SDHCI_CAN_DO_SUSPEND |
31598b5ce4cSAl Cooper SDHCI_CAN_DO_HISPD,
31698b5ce4cSAl Cooper .caps1 = SDHCI_DRIVER_TYPE_C |
31798b5ce4cSAl Cooper SDHCI_DRIVER_TYPE_D,
318f3200164SAdrian Hunter .missing_caps = true,
31998b5ce4cSAl Cooper };
32098b5ce4cSAl Cooper
321b580c52dSScott Branden static const struct of_device_id sdhci_iproc_of_match[] = {
32277cb7d3aSStefan Wahren { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
323f84e411cSStefan Wahren { .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
324c833e92bSScott Branden { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
325c833e92bSScott Branden { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
32698b5ce4cSAl Cooper { .compatible = "brcm,bcm7211a0-sdhci", .data = &bcm7211a0_data },
327b580c52dSScott Branden { }
328b580c52dSScott Branden };
329b580c52dSScott Branden MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
330b580c52dSScott Branden
331edfa69deSLee Jones #ifdef CONFIG_ACPI
3324f9833d3SJeremy Linton /*
3334f9833d3SJeremy Linton * This is a duplicate of bcm2835_(pltfrm_)data without caps quirks
3344f9833d3SJeremy Linton * which are provided by the ACPI table.
3354f9833d3SJeremy Linton */
3364f9833d3SJeremy Linton static const struct sdhci_pltfm_data sdhci_bcm_arasan_data = {
3374f9833d3SJeremy Linton .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
3384f9833d3SJeremy Linton SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
3394f9833d3SJeremy Linton SDHCI_QUIRK_NO_HISPD_BIT,
3404f9833d3SJeremy Linton .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
3414f9833d3SJeremy Linton .ops = &sdhci_iproc_32only_ops,
3424f9833d3SJeremy Linton };
3434f9833d3SJeremy Linton
3444f9833d3SJeremy Linton static const struct sdhci_iproc_data bcm_arasan_data = {
3454f9833d3SJeremy Linton .pdata = &sdhci_bcm_arasan_data,
3464f9833d3SJeremy Linton };
3474f9833d3SJeremy Linton
3487c7ba433SSrinath Mannam static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
3497c7ba433SSrinath Mannam { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
3507c7ba433SSrinath Mannam { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
3514f9833d3SJeremy Linton { .id = "BCM2847", .driver_data = (kernel_ulong_t)&bcm_arasan_data },
3524f9833d3SJeremy Linton { .id = "BRCME88C", .driver_data = (kernel_ulong_t)&bcm2711_data },
3537c7ba433SSrinath Mannam { /* sentinel */ }
3547c7ba433SSrinath Mannam };
3557c7ba433SSrinath Mannam MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
356edfa69deSLee Jones #endif
3577c7ba433SSrinath Mannam
sdhci_iproc_probe(struct platform_device * pdev)358b580c52dSScott Branden static int sdhci_iproc_probe(struct platform_device *pdev)
359b580c52dSScott Branden {
3607c7ba433SSrinath Mannam struct device *dev = &pdev->dev;
3617c7ba433SSrinath Mannam const struct sdhci_iproc_data *iproc_data = NULL;
362b580c52dSScott Branden struct sdhci_host *host;
363b580c52dSScott Branden struct sdhci_iproc_host *iproc_host;
364b580c52dSScott Branden struct sdhci_pltfm_host *pltfm_host;
365b580c52dSScott Branden int ret;
366b580c52dSScott Branden
3677c7ba433SSrinath Mannam iproc_data = device_get_match_data(dev);
3687c7ba433SSrinath Mannam if (!iproc_data)
3697c7ba433SSrinath Mannam return -ENODEV;
370b580c52dSScott Branden
371b580c52dSScott Branden host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
372b580c52dSScott Branden if (IS_ERR(host))
373b580c52dSScott Branden return PTR_ERR(host);
374b580c52dSScott Branden
375b580c52dSScott Branden pltfm_host = sdhci_priv(host);
376b580c52dSScott Branden iproc_host = sdhci_pltfm_priv(pltfm_host);
377b580c52dSScott Branden
378b580c52dSScott Branden iproc_host->data = iproc_data;
379b580c52dSScott Branden
3802bd44dadSStefan Wahren ret = mmc_of_parse(host->mmc);
3812bd44dadSStefan Wahren if (ret)
3822bd44dadSStefan Wahren goto err;
3832bd44dadSStefan Wahren
3847c7ba433SSrinath Mannam sdhci_get_property(pdev);
385b580c52dSScott Branden
386b17b4ab8SStefan Wahren host->mmc->caps |= iproc_host->data->mmc_caps;
387b580c52dSScott Branden
3887c7ba433SSrinath Mannam if (dev->of_node) {
389*3f377134SAdrian Hunter pltfm_host->clk = devm_clk_get_enabled(dev, NULL);
390b580c52dSScott Branden if (IS_ERR(pltfm_host->clk)) {
391b580c52dSScott Branden ret = PTR_ERR(pltfm_host->clk);
392b580c52dSScott Branden goto err;
393b580c52dSScott Branden }
3947c7ba433SSrinath Mannam }
395b580c52dSScott Branden
396f3200164SAdrian Hunter if (iproc_host->data->missing_caps) {
397f3200164SAdrian Hunter __sdhci_read_caps(host, NULL,
398f3200164SAdrian Hunter &iproc_host->data->caps,
399f3200164SAdrian Hunter &iproc_host->data->caps1);
400b580c52dSScott Branden }
401b580c52dSScott Branden
4021d6ad057SStefan Wahren ret = sdhci_add_host(host);
4031d6ad057SStefan Wahren if (ret)
404*3f377134SAdrian Hunter goto err;
4051d6ad057SStefan Wahren
4061d6ad057SStefan Wahren return 0;
407b580c52dSScott Branden
408b580c52dSScott Branden err:
409b580c52dSScott Branden sdhci_pltfm_free(pdev);
410b580c52dSScott Branden return ret;
411b580c52dSScott Branden }
412b580c52dSScott Branden
sdhci_iproc_shutdown(struct platform_device * pdev)41398b5ce4cSAl Cooper static void sdhci_iproc_shutdown(struct platform_device *pdev)
41498b5ce4cSAl Cooper {
41598b5ce4cSAl Cooper sdhci_pltfm_suspend(&pdev->dev);
41698b5ce4cSAl Cooper }
41798b5ce4cSAl Cooper
418b580c52dSScott Branden static struct platform_driver sdhci_iproc_driver = {
419b580c52dSScott Branden .driver = {
420b580c52dSScott Branden .name = "sdhci-iproc",
42121b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
422b580c52dSScott Branden .of_match_table = sdhci_iproc_of_match,
4237c7ba433SSrinath Mannam .acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
424fa243f64SUlf Hansson .pm = &sdhci_pltfm_pmops,
425b580c52dSScott Branden },
426b580c52dSScott Branden .probe = sdhci_iproc_probe,
427*3f377134SAdrian Hunter .remove_new = sdhci_pltfm_remove,
42898b5ce4cSAl Cooper .shutdown = sdhci_iproc_shutdown,
429b580c52dSScott Branden };
430b580c52dSScott Branden module_platform_driver(sdhci_iproc_driver);
431b580c52dSScott Branden
432b580c52dSScott Branden MODULE_AUTHOR("Broadcom");
433b580c52dSScott Branden MODULE_DESCRIPTION("IPROC SDHCI driver");
434b580c52dSScott Branden MODULE_LICENSE("GPL v2");
435