/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | nvidia,tegra234-mgbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller 10 - Thierry Reding <treding@nvidia.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 const: nvidia,tegra234-mgbe 20 reg-names: 22 - const: hypervisor [all …]
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/openbmc/linux/drivers/net/ethernet/freescale/dpaa2/ |
H A D | dpaa2-mac.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 5 #include <linux/pcs-lynx.h> 9 #include "dpaa2-eth.h" 10 #include "dpaa2-mac.h" 23 if (mac->ver_major == ver_major) in dpaa2_mac_cmp_ver() 24 return mac->ver_minor - ver_minor; in dpaa2_mac_cmp_ver() 25 return mac->ver_major - ver_major; in dpaa2_mac_cmp_ver() 30 mac->features = 0; in dpaa2_mac_detect_features() 34 mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE; in dpaa2_mac_detect_features() 61 return -EINVAL; in phy_mode() [all …]
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/openbmc/u-boot/include/linux/ |
H A D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 4 * Copyright 2006-2009 Solarflare Communications Inc. 24 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ 52 /* Media-dependent registers. */ 53 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ 54 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ 55 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. 56 * Lanes B-D are numbered 134-136. */ 57 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ 58 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ [all …]
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/openbmc/linux/include/uapi/linux/ |
H A D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 4 * Copyright 2006-2009 Solarflare Communications Inc. 25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ 58 /* Media-dependent registers. */ 59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ 60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ 61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. 62 * Lanes B-D are numbered 134-136. */ 63 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */ 64 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ [all …]
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/openbmc/linux/drivers/thunderbolt/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 14 Apple hardware or on PCs with Intel Falcon Ridge or newer. 16 To compile this driver a module, choose M here. The module will be 51 dongle that has TX/RX lines crossed, or by simply connecting a 55 To compile this driver a module, choose M here. The module will be
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/openbmc/linux/drivers/net/ethernet/freescale/fman/ |
H A D | fman_memac.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later 3 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 14 #include <linux/pcs-lynx.h> 24 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ 56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ 57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */ 58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */ 59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ 62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ 63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ [all …]
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
H A D | stmmac_ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 44 #define STMMAC_STAT(m) \ argument 45 { #m, sizeof_field(struct stmmac_extra_stats, m), \ 46 offsetof(struct stmmac_priv, xstats.m)} 79 /* Tx/Rx IRQ error info */ 89 /* Tx/Rx IRQ Events */ 129 /* PCS */ 167 /* statistics collected in queue which will be summed up for all TX or RX 168 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n). [all …]
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/openbmc/linux/drivers/net/ethernet/sun/ |
H A D | cassini.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as 30 * 32-bit words. there is no i/o port access. REG_ addresses are 42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit 62 /* top level interrupts [0-9] are auto-cleared to 0 when the status 63 * register is read. second level interrupts [13 - 18] are cleared at 64 * the source. tx completion register 3 is replicated in [19 - 31] 81 from RX FIFO to host mem. 82 RX completion reg updated. 86 RX Kick == RX complete */ [all …]
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/openbmc/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra234-clock.h> 4 #include <dt-bindings/gpio/tegra234-gpio.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/mailbox/tegra186-hsp.h> 7 #include <dt-bindings/memory/tegra234-mc.h> 8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9 #include <dt-bindings/power/tegra234-powergate.h> 10 #include <dt-bindings/reset/tegra234-reset.h> 11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h> [all …]
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/openbmc/linux/drivers/net/ethernet/intel/igb/ |
H A D | e1000_82575.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 61 * igb_write_vfta_i350 - Write value to VLAN filter table 71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350() 74 for (i = 10; i--;) in igb_write_vfta_i350() 78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350() 82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575() 114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked 121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap() [all …]
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H A D | e1000_defines.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 62 /* Interrupt acknowledge Auto-mask */ 118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 135 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 138 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 139 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ [all …]
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/openbmc/linux/drivers/phy/ti/ |
H A D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * phy-ti-pipe3 - PIPE3 PHY driver. 5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 130 u16 m; member 179 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */ 215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */ 241 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */ 266 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */ 302 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params() 304 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params() [all …]
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/openbmc/linux/drivers/net/ethernet/hisilicon/hns/ |
H A D | hns_dsaf_gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright (c) 2014-2015 Hisilicon Limited. 65 /*enable GE rX/tX */ in hns_gmac_enable() 70 /* enable rx pcs */ in hns_gmac_enable() 80 /*disable GE rX/tX */ in hns_gmac_disable() 85 /* disable rx pcs */ in hns_gmac_disable() 91 /* hns_gmac_get_en - get port enable 93 * @rx:rx enable 96 static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx) in hns_gmac_get_en() argument 103 *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B); in hns_gmac_get_en() [all …]
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/openbmc/linux/Documentation/networking/device_drivers/ethernet/cirrus/ |
H A D | cs89x0.rst | 1 .. SPDX-License-Identifier: GPL-2.0 33 2.1 CS8900-based Adapter Configuration 34 2.2 CS8920-based Adapter Configuration 41 4.3 Compiling the driver to support Rx DMA 46 5.2.1 Diagnostic Self-Test 66 The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow 67 IEEE 802.3 standards and support half or full-duplex operation in ISA bus 69 in 16-bit ISA or EISA bus expansion slots and are available in 70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5 73 CS8920-based adapters are similar to the CS8900-based adapter with additional [all …]
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb/ |
H A D | vsc7326_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 8 * Straight off the data sheet, VMDS-10038 Rev 2.0 and 9 * PD0011-01-14-Meigs-II 2002-12-12 69 * fn = FIFO number, 0-9 84 * bn = bucket number 0-10 (yes, 11 buckets) 114 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */ 133 * tri-speed are only defined with the version that needs a port number. 140 /* 10GbE specific, and different from tri-speed */ 144 #define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */ 147 #define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */ [all …]
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/openbmc/linux/drivers/staging/qlge/ |
H A D | qlge_dbg.c | 1 // SPDX-License-Identifier: GPL-2.0 18 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT) in qlge_read_other_func_reg() 35 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT) in qlge_write_other_func_reg() 47 for (count = 10; count; count--) { in qlge_wait_other_func_reg_rdy() 52 return -1; in qlge_wait_other_func_reg_rdy() 57 return -1; in qlge_wait_other_func_reg_rdy() 172 /* now see if i'm NIC 1 or NIC 2 */ in qlge_get_serdes_regs() 173 if (qdev->func & 1) in qlge_get_serdes_regs() 174 /* I'm NIC 2, so the indirect (NIC1) xfi is up. */ in qlge_get_serdes_regs() 181 /* now see if i'm NIC 1 or NIC 2 */ in qlge_get_serdes_regs() [all …]
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/openbmc/linux/drivers/net/dsa/ |
H A D | mt7530.c | 1 // SPDX-License-Identifier: GPL-2.0-only 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) in pcs_to_mt753x_pcs() argument 29 return container_of(pcs, struct mt753x_pcs, pcs); in pcs_to_mt753x_pcs() 85 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect() 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect() 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect() 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect() 104 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect() 108 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect() 117 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect() [all …]
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/openbmc/linux/drivers/net/ethernet/intel/e1000/ |
H A D | e1000_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2006 Intel Corporation. */ 422 /* MAC decode size is 128K - This is the size of BAR0 */ 443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 486 * E1000_RAR_ENTRIES - 1 multicast addresses. 503 /* Receive Descriptor - Extended */ 511 __le32 mrq; /* Multiple Rx Queues */ 529 /* Receive Descriptor - Packet Split */ 537 __le32 mrq; /* Multiple Rx Queues */ 553 __le16 length[3]; /* length of buffers 1-3 */ [all …]
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/openbmc/qemu/hw/net/ |
H A D | trace-events | 3 # allwinner-sun8i-emac.c 6 allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" P… 31 open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x" 32 open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x" 33 open_eth_update_irq(uint32_t v) "IRQ <- 0x%x" 34 open_eth_receive(unsigned len) "RX: len: %u" 36 open_eth_receive_reject(void) "RX: rejected" 37 open_eth_receive_desc(uint32_t addr, uint32_t len_flags) "RX: 0x%08x, len_flags: 0x%08x" 39 open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x" 40 open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x" [all …]
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/openbmc/linux/drivers/scsi/bfa/ |
H A D | bfa_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 4 * Copyright (c) 2014- QLogic Corporation. 8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. 34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */ 72 #define bfa_mfg_increment_wwn_mac(m, i) \ argument 74 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \ 75 (u32)(m)[2]; \ 77 (m)[0] = (t >> 16) & 0xFF; \ 78 (m)[1] = (t >> 8) & 0xFF; \ [all …]
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/openbmc/linux/drivers/net/dsa/realtek/ |
H A D | rtl8365mb.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. 4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk> 5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk> 7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4 9 * can be connected to the CPU - or another PHY - via either MII, RMII, or 15 * .-----------------------------------. 17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC | 18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC | 19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC | [all …]
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/openbmc/u-boot/drivers/net/ |
H A D | e1000.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 5 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 10 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 36 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args) 40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args) 51 writel((value), ((a)->hw_addr + E1000_##reg)) 53 readl((a)->hw_addr + E1000_##reg) 55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) 57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) 349 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ [all …]
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/openbmc/linux/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_type.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 81 #define IXGBE_CAT(r, m) IXGBE_##r##_##m argument 83 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, IDX)]) 273 (0x012300 + (((_i) - 24) * 4))) 277 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 278 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 280 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 281 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 290 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ [all …]
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/openbmc/u-boot/cmd/aspeed/nettest/ |
H A D | phy.c | 1 // SPDX-License-Identifier: GPL-2.0+ 63 //------------------------------------------------------------ 65 //------------------------------------------------------------ 71 if (eng->env.is_new_mdio_reg[eng->run.mdio_idx]) { in phy_write() 73 MDIO_SET_PHY_ADDR(eng->phy.Adr) | in phy_write() 75 writel(wr_data, eng->run.mdio_base); in phy_write() 76 /* check time-out */ in phy_write() 77 while (readl(eng->run.mdio_base) & MDIO_FIRE_BUSY) { in phy_write() 79 if (!eng->run.tm_tx_only) in phy_write() 81 "[PHY-Write] Time out: %08x\n", in phy_write() [all …]
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/openbmc/linux/drivers/net/ethernet/sfc/ |
H A D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 4 * Copyright 2009-2018 Solarflare Communications Inc. 5 * Copyright 2019-2020 Xilinx Inc. 13 /* Power-on reset state */ 35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 38 /* The rest of these are firmware-defined */ 46 /* Values to be written to the per-port status dword in shared 71 * | | \--- Response 72 * | \------- Error 73 * \------------------------------ Resync (always set) [all …]
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