1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 251dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3dee1ad47SJeff Kirsher 4dee1ad47SJeff Kirsher #ifndef _IXGBE_TYPE_H_ 5dee1ad47SJeff Kirsher #define _IXGBE_TYPE_H_ 6dee1ad47SJeff Kirsher 7dee1ad47SJeff Kirsher #include <linux/types.h> 8dee1ad47SJeff Kirsher #include <linux/mdio.h> 9dee1ad47SJeff Kirsher #include <linux/netdevice.h> 10dee1ad47SJeff Kirsher 11dee1ad47SJeff Kirsher /* Device IDs */ 12dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598 0x10B6 13dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598_BX 0x1508 14dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 15dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 16dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 17dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598AT 0x10C8 18dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598AT2 0x150B 19dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598EB_CX4 0x10DD 20dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 21dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 22dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 23dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 24dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_KX4 0x10F7 25dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 26dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_KR 0x1517 27dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_T3_LOM 0x151C 28dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_CX4 0x10F9 29dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_SFP 0x10FB 30dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a 31dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 32dee1ad47SJeff Kirsher #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 3387557440SMark Rustad #define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071 34b6dfd939SDon Skidmore #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 350e22d043SDon Skidmore #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 365700ff26SEmil Tantilov #define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B 3700103a6cSEmil Tantilov #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159 3800103a6cSEmil Tantilov #define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D 3900103a6cSEmil Tantilov #define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008 4000103a6cSEmil Tantilov #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976 4100103a6cSEmil Tantilov #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE 42f8a06c2cSEmil Tantilov #define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 43dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_SFP_EM 0x1507 44dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 457d145282SEmil Tantilov #define IXGBE_DEV_ID_82599EN_SFP 0x1557 465daebbb0SDon Skidmore #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 47dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 48dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 49dee1ad47SJeff Kirsher #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 50dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_82599_LS 0x154F 51dee1ad47SJeff Kirsher #define IXGBE_DEV_ID_X540T 0x1528 529e791e4aSEmil Tantilov #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 538f58332bSDon Skidmore #define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558 54df376f0dSjoshua.a.hay@intel.com #define IXGBE_DEV_ID_X540T1 0x1560 55dee1ad47SJeff Kirsher 566a14ee0cSDon Skidmore #define IXGBE_DEV_ID_X550T 0x1563 57a711ad89SMark Rustad #define IXGBE_DEV_ID_X550T1 0x15D1 586a14ee0cSDon Skidmore #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA 596a14ee0cSDon Skidmore #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB 606a14ee0cSDon Skidmore #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC 616a14ee0cSDon Skidmore #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD 626a14ee0cSDon Skidmore #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE 6318e01ee7SDon Skidmore #define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0 64f572b2c4SMark Rustad #define IXGBE_DEV_ID_X550EM_A_KR 0x15C2 65f572b2c4SMark Rustad #define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3 66207969b9SMark Rustad #define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4 67200157c2SMark Rustad #define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6 68200157c2SMark Rustad #define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7 6992ed8430SDon Skidmore #define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8 70c898fe28SMark Rustad #define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE 71b3eb4e18SMark Rustad #define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4 72b3eb4e18SMark Rustad #define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5 73207969b9SMark Rustad 74207969b9SMark Rustad /* VF Device IDs */ 75c6bda30aSGreg Rose #define IXGBE_DEV_ID_82599_VF 0x10ED 76c6bda30aSGreg Rose #define IXGBE_DEV_ID_X540_VF 0x1515 779a75a1acSDon Skidmore #define IXGBE_DEV_ID_X550_VF 0x1565 789a75a1acSDon Skidmore #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 79207969b9SMark Rustad #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5 80c6bda30aSGreg Rose 819a900ecaSDon Skidmore #define IXGBE_CAT(r, m) IXGBE_##r##_##m 829a900ecaSDon Skidmore 839a900ecaSDon Skidmore #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, IDX)]) 849a900ecaSDon Skidmore 85dee1ad47SJeff Kirsher /* General Registers */ 86dee1ad47SJeff Kirsher #define IXGBE_CTRL 0x00000 87dee1ad47SJeff Kirsher #define IXGBE_STATUS 0x00008 88dee1ad47SJeff Kirsher #define IXGBE_CTRL_EXT 0x00018 89dee1ad47SJeff Kirsher #define IXGBE_ESDP 0x00020 90dee1ad47SJeff Kirsher #define IXGBE_EODSDP 0x00028 919a900ecaSDon Skidmore 929a900ecaSDon Skidmore #define IXGBE_I2CCTL_8259X 0x00028 939a900ecaSDon Skidmore #define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_8259X 949a900ecaSDon Skidmore #define IXGBE_I2CCTL_X550 0x15F5C 959a900ecaSDon Skidmore #define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550 969a900ecaSDon Skidmore #define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550 979a900ecaSDon Skidmore #define IXGBE_I2CCTL(_hw) IXGBE_BY_MAC((_hw), I2CCTL) 989a900ecaSDon Skidmore 99dee1ad47SJeff Kirsher #define IXGBE_LEDCTL 0x00200 100dee1ad47SJeff Kirsher #define IXGBE_FRTIMER 0x00048 101dee1ad47SJeff Kirsher #define IXGBE_TCPTIMER 0x0004C 102dee1ad47SJeff Kirsher #define IXGBE_CORESPARE 0x00600 103dee1ad47SJeff Kirsher #define IXGBE_EXVET 0x05078 104dee1ad47SJeff Kirsher 105dee1ad47SJeff Kirsher /* NVM Registers */ 1069a900ecaSDon Skidmore #define IXGBE_EEC_8259X 0x10010 1079a900ecaSDon Skidmore #define IXGBE_EEC_X540 IXGBE_EEC_8259X 1089a900ecaSDon Skidmore #define IXGBE_EEC_X550 IXGBE_EEC_8259X 1099a900ecaSDon Skidmore #define IXGBE_EEC_X550EM_x IXGBE_EEC_8259X 1109a900ecaSDon Skidmore #define IXGBE_EEC_X550EM_a 0x15FF8 1119a900ecaSDon Skidmore #define IXGBE_EEC(_hw) IXGBE_BY_MAC((_hw), EEC) 112dee1ad47SJeff Kirsher #define IXGBE_EERD 0x10014 113dee1ad47SJeff Kirsher #define IXGBE_EEWR 0x10018 1149a900ecaSDon Skidmore #define IXGBE_FLA_8259X 0x1001C 1159a900ecaSDon Skidmore #define IXGBE_FLA_X540 IXGBE_FLA_8259X 1169a900ecaSDon Skidmore #define IXGBE_FLA_X550 IXGBE_FLA_8259X 1179a900ecaSDon Skidmore #define IXGBE_FLA_X550EM_x IXGBE_FLA_8259X 118207969b9SMark Rustad #define IXGBE_FLA_X550EM_a 0x15F68 1199a900ecaSDon Skidmore #define IXGBE_FLA(_hw) IXGBE_BY_MAC((_hw), FLA) 120dee1ad47SJeff Kirsher #define IXGBE_EEMNGCTL 0x10110 121dee1ad47SJeff Kirsher #define IXGBE_EEMNGDATA 0x10114 122dee1ad47SJeff Kirsher #define IXGBE_FLMNGCTL 0x10118 123dee1ad47SJeff Kirsher #define IXGBE_FLMNGDATA 0x1011C 124dee1ad47SJeff Kirsher #define IXGBE_FLMNGCNT 0x10120 125dee1ad47SJeff Kirsher #define IXGBE_FLOP 0x1013C 1269a900ecaSDon Skidmore #define IXGBE_GRC_8259X 0x10200 1279a900ecaSDon Skidmore #define IXGBE_GRC_X540 IXGBE_GRC_8259X 1289a900ecaSDon Skidmore #define IXGBE_GRC_X550 IXGBE_GRC_8259X 1299a900ecaSDon Skidmore #define IXGBE_GRC_X550EM_x IXGBE_GRC_8259X 1309a900ecaSDon Skidmore #define IXGBE_GRC_X550EM_a 0x15F64 1319a900ecaSDon Skidmore #define IXGBE_GRC(_hw) IXGBE_BY_MAC((_hw), GRC) 1329a900ecaSDon Skidmore 133dee1ad47SJeff Kirsher /* General Receive Control */ 134dee1ad47SJeff Kirsher #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 135dee1ad47SJeff Kirsher #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 136dee1ad47SJeff Kirsher 137dee1ad47SJeff Kirsher #define IXGBE_VPDDIAG0 0x10204 138dee1ad47SJeff Kirsher #define IXGBE_VPDDIAG1 0x10208 139dee1ad47SJeff Kirsher 140dee1ad47SJeff Kirsher /* I2CCTL Bit Masks */ 1419a900ecaSDon Skidmore #define IXGBE_I2C_CLK_IN_8259X 0x00000001 1429a900ecaSDon Skidmore #define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN_8259X 1439a900ecaSDon Skidmore #define IXGBE_I2C_CLK_IN_X550 0x00004000 1449a900ecaSDon Skidmore #define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550 1459a900ecaSDon Skidmore #define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550 1469a900ecaSDon Skidmore #define IXGBE_I2C_CLK_IN(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN) 1479a900ecaSDon Skidmore 1489a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OUT_8259X 0x00000002 1499a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT_8259X 1509a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OUT_X550 0x00000200 1519a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550 1529a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550 1539a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OUT(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT) 1549a900ecaSDon Skidmore 1559a900ecaSDon Skidmore #define IXGBE_I2C_DATA_IN_8259X 0x00000004 1569a900ecaSDon Skidmore #define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN_8259X 1579a900ecaSDon Skidmore #define IXGBE_I2C_DATA_IN_X550 0x00001000 1589a900ecaSDon Skidmore #define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550 1599a900ecaSDon Skidmore #define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550 1609a900ecaSDon Skidmore #define IXGBE_I2C_DATA_IN(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN) 1619a900ecaSDon Skidmore 1629a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OUT_8259X 0x00000008 1639a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT_8259X 1649a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OUT_X550 0x00000400 1659a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550 1669a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550 1679a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OUT(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT) 1689a900ecaSDon Skidmore 1699a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OE_N_EN_8259X 0 1709a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN_8259X 1719a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800 1729a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550 1739a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550 1749a900ecaSDon Skidmore #define IXGBE_I2C_DATA_OE_N_EN(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN) 1759a900ecaSDon Skidmore 1769a900ecaSDon Skidmore #define IXGBE_I2C_BB_EN_8259X 0 1779a900ecaSDon Skidmore #define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN_8259X 1789a900ecaSDon Skidmore #define IXGBE_I2C_BB_EN_X550 0x00000100 1799a900ecaSDon Skidmore #define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550 1809a900ecaSDon Skidmore #define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550 1819a900ecaSDon Skidmore #define IXGBE_I2C_BB_EN(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN) 1829a900ecaSDon Skidmore 1839a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OE_N_EN_8259X 0 1849a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN_8259X 1859a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000 1869a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550 1879a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550 1889a900ecaSDon Skidmore #define IXGBE_I2C_CLK_OE_N_EN(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN) 1899a900ecaSDon Skidmore 1908f56e4b9SDon Skidmore #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 191dee1ad47SJeff Kirsher 192e1ea9158SDon Skidmore #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8 193e1ea9158SDon Skidmore #define IXGBE_EMC_INTERNAL_DATA 0x00 194e1ea9158SDon Skidmore #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20 195e1ea9158SDon Skidmore #define IXGBE_EMC_DIODE1_DATA 0x01 196e1ea9158SDon Skidmore #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19 197e1ea9158SDon Skidmore #define IXGBE_EMC_DIODE2_DATA 0x23 198e1ea9158SDon Skidmore #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A 199e1ea9158SDon Skidmore 200e1ea9158SDon Skidmore #define IXGBE_MAX_SENSORS 3 201e1ea9158SDon Skidmore 202e1ea9158SDon Skidmore struct ixgbe_thermal_diode_data { 203e1ea9158SDon Skidmore u8 location; 204e1ea9158SDon Skidmore u8 temp; 205e1ea9158SDon Skidmore u8 caution_thresh; 206e1ea9158SDon Skidmore u8 max_op_thresh; 207e1ea9158SDon Skidmore }; 208e1ea9158SDon Skidmore 209e1ea9158SDon Skidmore struct ixgbe_thermal_sensor_data { 210e1ea9158SDon Skidmore struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS]; 211e1ea9158SDon Skidmore }; 212e1ea9158SDon Skidmore 21373834aecSPaul Greenwalt #define NVM_OROM_OFFSET 0x17 21473834aecSPaul Greenwalt #define NVM_OROM_BLK_LOW 0x83 21573834aecSPaul Greenwalt #define NVM_OROM_BLK_HI 0x84 21673834aecSPaul Greenwalt #define NVM_OROM_PATCH_MASK 0xFF 21773834aecSPaul Greenwalt #define NVM_OROM_SHIFT 8 21873834aecSPaul Greenwalt 21973834aecSPaul Greenwalt #define NVM_VER_MASK 0x00FF /* version mask */ 22073834aecSPaul Greenwalt #define NVM_VER_SHIFT 8 /* version bit shift */ 22173834aecSPaul Greenwalt #define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */ 22273834aecSPaul Greenwalt #define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */ 22373834aecSPaul Greenwalt #define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */ 22473834aecSPaul Greenwalt #define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */ 22573834aecSPaul Greenwalt #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */ 22673834aecSPaul Greenwalt #define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */ 22773834aecSPaul Greenwalt #define NVM_ETK_OFF_LOW 0x2D /* version low order word */ 22873834aecSPaul Greenwalt #define NVM_ETK_OFF_HI 0x2E /* version high order word */ 22973834aecSPaul Greenwalt #define NVM_ETK_SHIFT 16 /* high version word shift */ 23073834aecSPaul Greenwalt #define NVM_VER_INVALID 0xFFFF 23173834aecSPaul Greenwalt #define NVM_ETK_VALID 0x8000 23273834aecSPaul Greenwalt #define NVM_INVALID_PTR 0xFFFF 23373834aecSPaul Greenwalt #define NVM_VER_SIZE 32 /* version sting size */ 23473834aecSPaul Greenwalt 23573834aecSPaul Greenwalt struct ixgbe_nvm_version { 23673834aecSPaul Greenwalt u32 etk_id; 23773834aecSPaul Greenwalt u8 nvm_major; 23873834aecSPaul Greenwalt u16 nvm_minor; 23973834aecSPaul Greenwalt u8 nvm_id; 24073834aecSPaul Greenwalt 24173834aecSPaul Greenwalt bool oem_valid; 24273834aecSPaul Greenwalt u8 oem_major; 24373834aecSPaul Greenwalt u8 oem_minor; 24473834aecSPaul Greenwalt u16 oem_release; 24573834aecSPaul Greenwalt 24673834aecSPaul Greenwalt bool or_valid; 24773834aecSPaul Greenwalt u8 or_major; 24873834aecSPaul Greenwalt u16 or_build; 24973834aecSPaul Greenwalt u8 or_patch; 25073834aecSPaul Greenwalt }; 25173834aecSPaul Greenwalt 252dee1ad47SJeff Kirsher /* Interrupt Registers */ 253dee1ad47SJeff Kirsher #define IXGBE_EICR 0x00800 254dee1ad47SJeff Kirsher #define IXGBE_EICS 0x00808 255dee1ad47SJeff Kirsher #define IXGBE_EIMS 0x00880 256dee1ad47SJeff Kirsher #define IXGBE_EIMC 0x00888 257dee1ad47SJeff Kirsher #define IXGBE_EIAC 0x00810 258dee1ad47SJeff Kirsher #define IXGBE_EIAM 0x00890 259dee1ad47SJeff Kirsher #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 260dee1ad47SJeff Kirsher #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 261dee1ad47SJeff Kirsher #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 262dee1ad47SJeff Kirsher #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 263dee1ad47SJeff Kirsher /* 264dee1ad47SJeff Kirsher * 82598 EITR is 16 bits but set the limits based on the max 265dee1ad47SJeff Kirsher * supported by all ixgbe hardware. 82599 EITR is only 12 bits, 266dee1ad47SJeff Kirsher * with the lower 3 always zero. 267dee1ad47SJeff Kirsher */ 268dee1ad47SJeff Kirsher #define IXGBE_MAX_INT_RATE 488281 269dee1ad47SJeff Kirsher #define IXGBE_MIN_INT_RATE 956 270dee1ad47SJeff Kirsher #define IXGBE_MAX_EITR 0x00000FF8 271dee1ad47SJeff Kirsher #define IXGBE_MIN_EITR 8 272dee1ad47SJeff Kirsher #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 273dee1ad47SJeff Kirsher (0x012300 + (((_i) - 24) * 4))) 274dee1ad47SJeff Kirsher #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 275dee1ad47SJeff Kirsher #define IXGBE_EITR_LLI_MOD 0x00008000 276dee1ad47SJeff Kirsher #define IXGBE_EITR_CNT_WDIS 0x80000000 277dee1ad47SJeff Kirsher #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 278dee1ad47SJeff Kirsher #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 279dee1ad47SJeff Kirsher #define IXGBE_EITRSEL 0x00894 280dee1ad47SJeff Kirsher #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 281dee1ad47SJeff Kirsher #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 282dee1ad47SJeff Kirsher #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 283dee1ad47SJeff Kirsher #define IXGBE_GPIE 0x00898 284dee1ad47SJeff Kirsher 285dee1ad47SJeff Kirsher /* Flow Control Registers */ 286dee1ad47SJeff Kirsher #define IXGBE_FCADBUL 0x03210 287dee1ad47SJeff Kirsher #define IXGBE_FCADBUH 0x03214 288dee1ad47SJeff Kirsher #define IXGBE_FCAMACL 0x04328 289dee1ad47SJeff Kirsher #define IXGBE_FCAMACH 0x0432C 290dee1ad47SJeff Kirsher #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 291dee1ad47SJeff Kirsher #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 292dee1ad47SJeff Kirsher #define IXGBE_PFCTOP 0x03008 293dee1ad47SJeff Kirsher #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 294dee1ad47SJeff Kirsher #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 295dee1ad47SJeff Kirsher #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 296dee1ad47SJeff Kirsher #define IXGBE_FCRTV 0x032A0 297dee1ad47SJeff Kirsher #define IXGBE_FCCFG 0x03D00 298dee1ad47SJeff Kirsher #define IXGBE_TFCS 0x0CE00 299dee1ad47SJeff Kirsher 300dee1ad47SJeff Kirsher /* Receive DMA Registers */ 301dee1ad47SJeff Kirsher #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 302795be954SAlexander Duyck (0x0D000 + (((_i) - 64) * 0x40))) 303dee1ad47SJeff Kirsher #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 304795be954SAlexander Duyck (0x0D004 + (((_i) - 64) * 0x40))) 305dee1ad47SJeff Kirsher #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 306795be954SAlexander Duyck (0x0D008 + (((_i) - 64) * 0x40))) 307dee1ad47SJeff Kirsher #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 308795be954SAlexander Duyck (0x0D010 + (((_i) - 64) * 0x40))) 309dee1ad47SJeff Kirsher #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 310795be954SAlexander Duyck (0x0D018 + (((_i) - 64) * 0x40))) 311dee1ad47SJeff Kirsher #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 312795be954SAlexander Duyck (0x0D028 + (((_i) - 64) * 0x40))) 313dee1ad47SJeff Kirsher #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 314795be954SAlexander Duyck (0x0D02C + (((_i) - 64) * 0x40))) 315dee1ad47SJeff Kirsher #define IXGBE_RSCDBU 0x03028 316dee1ad47SJeff Kirsher #define IXGBE_RDDCC 0x02F20 317dee1ad47SJeff Kirsher #define IXGBE_RXMEMWRAP 0x03190 318dee1ad47SJeff Kirsher #define IXGBE_STARCTRL 0x03024 319dee1ad47SJeff Kirsher /* 320dee1ad47SJeff Kirsher * Split and Replication Receive Control Registers 321dee1ad47SJeff Kirsher * 00-15 : 0x02100 + n*4 322dee1ad47SJeff Kirsher * 16-64 : 0x01014 + n*0x40 323dee1ad47SJeff Kirsher * 64-127: 0x0D014 + (n-64)*0x40 324dee1ad47SJeff Kirsher */ 325dee1ad47SJeff Kirsher #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 326dee1ad47SJeff Kirsher (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 327795be954SAlexander Duyck (0x0D014 + (((_i) - 64) * 0x40)))) 328dee1ad47SJeff Kirsher /* 329dee1ad47SJeff Kirsher * Rx DCA Control Register: 330dee1ad47SJeff Kirsher * 00-15 : 0x02200 + n*4 331dee1ad47SJeff Kirsher * 16-64 : 0x0100C + n*0x40 332dee1ad47SJeff Kirsher * 64-127: 0x0D00C + (n-64)*0x40 333dee1ad47SJeff Kirsher */ 334dee1ad47SJeff Kirsher #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 335dee1ad47SJeff Kirsher (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 336795be954SAlexander Duyck (0x0D00C + (((_i) - 64) * 0x40)))) 337dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL 0x02F00 338dee1ad47SJeff Kirsher #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 339dee1ad47SJeff Kirsher /* 8 of these 0x03C00 - 0x03C1C */ 340dee1ad47SJeff Kirsher #define IXGBE_RXCTRL 0x03000 341dee1ad47SJeff Kirsher #define IXGBE_DROPEN 0x03D04 342dee1ad47SJeff Kirsher #define IXGBE_RXPBSIZE_SHIFT 10 343dee1ad47SJeff Kirsher 344dee1ad47SJeff Kirsher /* Receive Registers */ 345dee1ad47SJeff Kirsher #define IXGBE_RXCSUM 0x05000 346dee1ad47SJeff Kirsher #define IXGBE_RFCTL 0x05008 347dee1ad47SJeff Kirsher #define IXGBE_DRECCCTL 0x02F08 348dee1ad47SJeff Kirsher #define IXGBE_DRECCCTL_DISABLE 0 349dee1ad47SJeff Kirsher /* Multicast Table Array - 128 entries */ 350dee1ad47SJeff Kirsher #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 351dee1ad47SJeff Kirsher #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 352dee1ad47SJeff Kirsher (0x0A200 + ((_i) * 8))) 353dee1ad47SJeff Kirsher #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 354dee1ad47SJeff Kirsher (0x0A204 + ((_i) * 8))) 355dee1ad47SJeff Kirsher #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 356dee1ad47SJeff Kirsher #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 357dee1ad47SJeff Kirsher /* Packet split receive type */ 358dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 359dee1ad47SJeff Kirsher (0x0EA00 + ((_i) * 4))) 360dee1ad47SJeff Kirsher /* array of 4096 1-bit vlan filters */ 361dee1ad47SJeff Kirsher #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 362dee1ad47SJeff Kirsher /*array of 4096 4-bit vlan vmdq indices */ 363dee1ad47SJeff Kirsher #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 364dee1ad47SJeff Kirsher #define IXGBE_FCTRL 0x05080 365dee1ad47SJeff Kirsher #define IXGBE_VLNCTRL 0x05088 366dee1ad47SJeff Kirsher #define IXGBE_MCSTCTRL 0x05090 367dee1ad47SJeff Kirsher #define IXGBE_MRQC 0x05818 368dee1ad47SJeff Kirsher #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 369dee1ad47SJeff Kirsher #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 370dee1ad47SJeff Kirsher #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 371dee1ad47SJeff Kirsher #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 372dee1ad47SJeff Kirsher #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 373dee1ad47SJeff Kirsher #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 374dee1ad47SJeff Kirsher #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 375dee1ad47SJeff Kirsher #define IXGBE_RQTC 0x0EC70 376dee1ad47SJeff Kirsher #define IXGBE_MTQC 0x08120 377dee1ad47SJeff Kirsher #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 378dee1ad47SJeff Kirsher #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 379dee1ad47SJeff Kirsher #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 3806d4c96adSDon Skidmore #define IXGBE_PFFLPL 0x050B0 3816d4c96adSDon Skidmore #define IXGBE_PFFLPH 0x050B4 382dee1ad47SJeff Kirsher #define IXGBE_VT_CTL 0x051B0 383dee1ad47SJeff Kirsher #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 384dee1ad47SJeff Kirsher #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */ 385dee1ad47SJeff Kirsher #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 386dee1ad47SJeff Kirsher #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 387dee1ad47SJeff Kirsher #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 388dee1ad47SJeff Kirsher #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 389dee1ad47SJeff Kirsher #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 390dee1ad47SJeff Kirsher #define IXGBE_QDE 0x2F04 391dee1ad47SJeff Kirsher #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 392dee1ad47SJeff Kirsher #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 393dee1ad47SJeff Kirsher #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 394dee1ad47SJeff Kirsher #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 395dee1ad47SJeff Kirsher #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 396dee1ad47SJeff Kirsher #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 397207969b9SMark Rustad #define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */ 398207969b9SMark Rustad #define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */ 399dee1ad47SJeff Kirsher #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 400dee1ad47SJeff Kirsher #define IXGBE_RXFECCERR0 0x051B8 401dee1ad47SJeff Kirsher #define IXGBE_LLITHRESH 0x0EC90 402dee1ad47SJeff Kirsher #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 403dee1ad47SJeff Kirsher #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 404dee1ad47SJeff Kirsher #define IXGBE_IMIRVP 0x05AC0 405dee1ad47SJeff Kirsher #define IXGBE_VMD_CTL 0x0581C 406dee1ad47SJeff Kirsher #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 4070f9b232bSDon Skidmore #define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */ 408dee1ad47SJeff Kirsher #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 409dee1ad47SJeff Kirsher 4109a75a1acSDon Skidmore /* Registers for setting up RSS on X550 with SRIOV 4119a75a1acSDon Skidmore * _p - pool number (0..63) 4129a75a1acSDon Skidmore * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA) 4139a75a1acSDon Skidmore */ 4149a75a1acSDon Skidmore #define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4)) 4159a75a1acSDon Skidmore #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40)) 4169a75a1acSDon Skidmore #define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40)) 4179a75a1acSDon Skidmore 418dee1ad47SJeff Kirsher /* Flow Director registers */ 419dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL 0x0EE00 420dee1ad47SJeff Kirsher #define IXGBE_FDIRHKEY 0x0EE68 421dee1ad47SJeff Kirsher #define IXGBE_FDIRSKEY 0x0EE6C 422dee1ad47SJeff Kirsher #define IXGBE_FDIRDIP4M 0x0EE3C 423dee1ad47SJeff Kirsher #define IXGBE_FDIRSIP4M 0x0EE40 424dee1ad47SJeff Kirsher #define IXGBE_FDIRTCPM 0x0EE44 425dee1ad47SJeff Kirsher #define IXGBE_FDIRUDPM 0x0EE48 4265532408bSDon Skidmore #define IXGBE_FDIRSCTPM 0x0EE78 427dee1ad47SJeff Kirsher #define IXGBE_FDIRIP6M 0x0EE74 428dee1ad47SJeff Kirsher #define IXGBE_FDIRM 0x0EE70 429dee1ad47SJeff Kirsher 430dee1ad47SJeff Kirsher /* Flow Director Stats registers */ 431dee1ad47SJeff Kirsher #define IXGBE_FDIRFREE 0x0EE38 432dee1ad47SJeff Kirsher #define IXGBE_FDIRLEN 0x0EE4C 433dee1ad47SJeff Kirsher #define IXGBE_FDIRUSTAT 0x0EE50 434dee1ad47SJeff Kirsher #define IXGBE_FDIRFSTAT 0x0EE54 435dee1ad47SJeff Kirsher #define IXGBE_FDIRMATCH 0x0EE58 436dee1ad47SJeff Kirsher #define IXGBE_FDIRMISS 0x0EE5C 437dee1ad47SJeff Kirsher 438dee1ad47SJeff Kirsher /* Flow Director Programming registers */ 439dee1ad47SJeff Kirsher #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 440dee1ad47SJeff Kirsher #define IXGBE_FDIRIPSA 0x0EE18 441dee1ad47SJeff Kirsher #define IXGBE_FDIRIPDA 0x0EE1C 442dee1ad47SJeff Kirsher #define IXGBE_FDIRPORT 0x0EE20 443dee1ad47SJeff Kirsher #define IXGBE_FDIRVLAN 0x0EE24 444dee1ad47SJeff Kirsher #define IXGBE_FDIRHASH 0x0EE28 445dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD 0x0EE2C 446dee1ad47SJeff Kirsher 447dee1ad47SJeff Kirsher /* Transmit DMA registers */ 448dee1ad47SJeff Kirsher #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ 449dee1ad47SJeff Kirsher #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 450dee1ad47SJeff Kirsher #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 451dee1ad47SJeff Kirsher #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 452dee1ad47SJeff Kirsher #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 453dee1ad47SJeff Kirsher #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 454dee1ad47SJeff Kirsher #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 455dee1ad47SJeff Kirsher #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 456dee1ad47SJeff Kirsher #define IXGBE_DTXCTL 0x07E00 457dee1ad47SJeff Kirsher 458dee1ad47SJeff Kirsher #define IXGBE_DMATXCTL 0x04A80 459dee1ad47SJeff Kirsher #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 460dee1ad47SJeff Kirsher #define IXGBE_PFDTXGSWC 0x08220 461dee1ad47SJeff Kirsher #define IXGBE_DTXMXSZRQ 0x08100 462dee1ad47SJeff Kirsher #define IXGBE_DTXTCPFLGL 0x04A88 463dee1ad47SJeff Kirsher #define IXGBE_DTXTCPFLGH 0x04A8C 464dee1ad47SJeff Kirsher #define IXGBE_LBDRPEN 0x0CA00 465dee1ad47SJeff Kirsher #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 466dee1ad47SJeff Kirsher 467dee1ad47SJeff Kirsher #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 468dee1ad47SJeff Kirsher #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 469dee1ad47SJeff Kirsher #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 470207969b9SMark Rustad #define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */ 471207969b9SMark Rustad #define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */ 472dee1ad47SJeff Kirsher #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 473dee1ad47SJeff Kirsher 474dee1ad47SJeff Kirsher #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 475dee1ad47SJeff Kirsher 476dee1ad47SJeff Kirsher /* Anti-spoofing defines */ 477dee1ad47SJeff Kirsher #define IXGBE_SPOOF_MACAS_MASK 0xFF 478dee1ad47SJeff Kirsher #define IXGBE_SPOOF_VLANAS_MASK 0xFF00 479dee1ad47SJeff Kirsher #define IXGBE_SPOOF_VLANAS_SHIFT 8 4805b7f000fSDon Skidmore #define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000 4815b7f000fSDon Skidmore #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16 482dee1ad47SJeff Kirsher #define IXGBE_PFVFSPOOF_REG_COUNT 8 483dee1ad47SJeff Kirsher 484dee1ad47SJeff Kirsher #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ 485dee1ad47SJeff Kirsher /* Tx DCA Control register : 128 of these (0-127) */ 486dee1ad47SJeff Kirsher #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 487dee1ad47SJeff Kirsher #define IXGBE_TIPG 0x0CB00 488dee1ad47SJeff Kirsher #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 489dee1ad47SJeff Kirsher #define IXGBE_MNGTXMAP 0x0CD10 490dee1ad47SJeff Kirsher #define IXGBE_TIPG_FIBER_DEFAULT 3 491dee1ad47SJeff Kirsher #define IXGBE_TXPBSIZE_SHIFT 10 492dee1ad47SJeff Kirsher 493dee1ad47SJeff Kirsher /* Wake up registers */ 494dee1ad47SJeff Kirsher #define IXGBE_WUC 0x05800 495dee1ad47SJeff Kirsher #define IXGBE_WUFC 0x05808 496dee1ad47SJeff Kirsher #define IXGBE_WUS 0x05810 497dee1ad47SJeff Kirsher #define IXGBE_IPAV 0x05838 498dee1ad47SJeff Kirsher #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 499dee1ad47SJeff Kirsher #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 500dee1ad47SJeff Kirsher 501dee1ad47SJeff Kirsher #define IXGBE_WUPL 0x05900 502dee1ad47SJeff Kirsher #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 5033f207800SDon Skidmore #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */ 504795be954SAlexander Duyck #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ 505795be954SAlexander Duyck #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host 506dee1ad47SJeff Kirsher * Filter Table */ 507dee1ad47SJeff Kirsher 508a21d0822SEmil Tantilov /* masks for accessing VXLAN and GENEVE UDP ports */ 509a21d0822SEmil Tantilov #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */ 510a21d0822SEmil Tantilov #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */ 511a21d0822SEmil Tantilov #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */ 512a21d0822SEmil Tantilov 513a21d0822SEmil Tantilov #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16 514a21d0822SEmil Tantilov 515dee1ad47SJeff Kirsher #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 516dee1ad47SJeff Kirsher #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 517dee1ad47SJeff Kirsher 518dee1ad47SJeff Kirsher /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 519dee1ad47SJeff Kirsher #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 520dee1ad47SJeff Kirsher #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 521dee1ad47SJeff Kirsher #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 522dee1ad47SJeff Kirsher 523dee1ad47SJeff Kirsher /* Definitions for power management and wakeup registers */ 524dee1ad47SJeff Kirsher /* Wake Up Control */ 525dee1ad47SJeff Kirsher #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 526dee1ad47SJeff Kirsher #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 527dee1ad47SJeff Kirsher #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 528dee1ad47SJeff Kirsher 529dee1ad47SJeff Kirsher /* Wake Up Filter Control */ 530dee1ad47SJeff Kirsher #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 531dee1ad47SJeff Kirsher #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 532dee1ad47SJeff Kirsher #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 533dee1ad47SJeff Kirsher #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 534dee1ad47SJeff Kirsher #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 535dee1ad47SJeff Kirsher #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 536dee1ad47SJeff Kirsher #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 537dee1ad47SJeff Kirsher #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 538dee1ad47SJeff Kirsher #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 539dee1ad47SJeff Kirsher 540dee1ad47SJeff Kirsher #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 541dee1ad47SJeff Kirsher #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 542dee1ad47SJeff Kirsher #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 543dee1ad47SJeff Kirsher #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 544dee1ad47SJeff Kirsher #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 545dee1ad47SJeff Kirsher #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 546dee1ad47SJeff Kirsher #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 547dee1ad47SJeff Kirsher #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 548dee1ad47SJeff Kirsher #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */ 549dee1ad47SJeff Kirsher #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */ 550dee1ad47SJeff Kirsher #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 551dee1ad47SJeff Kirsher 552dee1ad47SJeff Kirsher /* Wake Up Status */ 553dee1ad47SJeff Kirsher #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 554dee1ad47SJeff Kirsher #define IXGBE_WUS_MAG IXGBE_WUFC_MAG 555dee1ad47SJeff Kirsher #define IXGBE_WUS_EX IXGBE_WUFC_EX 556dee1ad47SJeff Kirsher #define IXGBE_WUS_MC IXGBE_WUFC_MC 557dee1ad47SJeff Kirsher #define IXGBE_WUS_BC IXGBE_WUFC_BC 558dee1ad47SJeff Kirsher #define IXGBE_WUS_ARP IXGBE_WUFC_ARP 559dee1ad47SJeff Kirsher #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 560dee1ad47SJeff Kirsher #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 561dee1ad47SJeff Kirsher #define IXGBE_WUS_MNG IXGBE_WUFC_MNG 562dee1ad47SJeff Kirsher #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 563dee1ad47SJeff Kirsher #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 564dee1ad47SJeff Kirsher #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 565dee1ad47SJeff Kirsher #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 566dee1ad47SJeff Kirsher #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 567dee1ad47SJeff Kirsher #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 568dee1ad47SJeff Kirsher #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 569dee1ad47SJeff Kirsher 570dee1ad47SJeff Kirsher /* Wake Up Packet Length */ 571dee1ad47SJeff Kirsher #define IXGBE_WUPL_LENGTH_MASK 0xFFFF 572dee1ad47SJeff Kirsher 573dee1ad47SJeff Kirsher /* DCB registers */ 5749da712d2SJohn Fastabend #define MAX_TRAFFIC_CLASS 8 5754de2a022SJohn Fastabend #define X540_TRAFFIC_CLASS 4 5768829009dSUsha Ketineni #define DEF_TRAFFIC_CLASS 1 577dee1ad47SJeff Kirsher #define IXGBE_RMCS 0x03D00 578dee1ad47SJeff Kirsher #define IXGBE_DPMCS 0x07F40 579dee1ad47SJeff Kirsher #define IXGBE_PDPMCS 0x0CD00 580dee1ad47SJeff Kirsher #define IXGBE_RUPPBMR 0x050A0 581dee1ad47SJeff Kirsher #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 582dee1ad47SJeff Kirsher #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 583dee1ad47SJeff Kirsher #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 584dee1ad47SJeff Kirsher #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 585dee1ad47SJeff Kirsher #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 586dee1ad47SJeff Kirsher #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 587dee1ad47SJeff Kirsher 588dee1ad47SJeff Kirsher /* Security Control Registers */ 589dee1ad47SJeff Kirsher #define IXGBE_SECTXCTRL 0x08800 590dee1ad47SJeff Kirsher #define IXGBE_SECTXSTAT 0x08804 591dee1ad47SJeff Kirsher #define IXGBE_SECTXBUFFAF 0x08808 592dee1ad47SJeff Kirsher #define IXGBE_SECTXMINIFG 0x08810 593dee1ad47SJeff Kirsher #define IXGBE_SECRXCTRL 0x08D00 594dee1ad47SJeff Kirsher #define IXGBE_SECRXSTAT 0x08D04 595dee1ad47SJeff Kirsher 596dee1ad47SJeff Kirsher /* Security Bit Fields and Masks */ 597dee1ad47SJeff Kirsher #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 598dee1ad47SJeff Kirsher #define IXGBE_SECTXCTRL_TX_DIS 0x00000002 599dee1ad47SJeff Kirsher #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 600dee1ad47SJeff Kirsher 601dee1ad47SJeff Kirsher #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 602421d954cSAlexander Duyck #define IXGBE_SECTXSTAT_SECTX_OFF_DIS 0x00000002 603421d954cSAlexander Duyck #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000004 604dee1ad47SJeff Kirsher 605dee1ad47SJeff Kirsher #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 606dee1ad47SJeff Kirsher #define IXGBE_SECRXCTRL_RX_DIS 0x00000002 607dee1ad47SJeff Kirsher 608dee1ad47SJeff Kirsher #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 609421d954cSAlexander Duyck #define IXGBE_SECRXSTAT_SECRX_OFF_DIS 0x00000002 610421d954cSAlexander Duyck #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000004 611dee1ad47SJeff Kirsher 612dee1ad47SJeff Kirsher /* LinkSec (MacSec) Registers */ 613dee1ad47SJeff Kirsher #define IXGBE_LSECTXCAP 0x08A00 614dee1ad47SJeff Kirsher #define IXGBE_LSECRXCAP 0x08F00 615dee1ad47SJeff Kirsher #define IXGBE_LSECTXCTRL 0x08A04 616dee1ad47SJeff Kirsher #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 617dee1ad47SJeff Kirsher #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 618dee1ad47SJeff Kirsher #define IXGBE_LSECTXSA 0x08A10 619dee1ad47SJeff Kirsher #define IXGBE_LSECTXPN0 0x08A14 620dee1ad47SJeff Kirsher #define IXGBE_LSECTXPN1 0x08A18 621dee1ad47SJeff Kirsher #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 622dee1ad47SJeff Kirsher #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 623dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL 0x08F04 624dee1ad47SJeff Kirsher #define IXGBE_LSECRXSCL 0x08F08 625dee1ad47SJeff Kirsher #define IXGBE_LSECRXSCH 0x08F0C 626dee1ad47SJeff Kirsher #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 627dee1ad47SJeff Kirsher #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 628dee1ad47SJeff Kirsher #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 629dee1ad47SJeff Kirsher #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 630dee1ad47SJeff Kirsher #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 631dee1ad47SJeff Kirsher #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 632dee1ad47SJeff Kirsher #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 633dee1ad47SJeff Kirsher #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 634dee1ad47SJeff Kirsher #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 635dee1ad47SJeff Kirsher #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 636dee1ad47SJeff Kirsher #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 637dee1ad47SJeff Kirsher #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 638dee1ad47SJeff Kirsher #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 639dee1ad47SJeff Kirsher #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 640dee1ad47SJeff Kirsher #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 641dee1ad47SJeff Kirsher #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 642dee1ad47SJeff Kirsher #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 643dee1ad47SJeff Kirsher #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 644dee1ad47SJeff Kirsher #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 645dee1ad47SJeff Kirsher #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 646dee1ad47SJeff Kirsher #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 647dee1ad47SJeff Kirsher #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 648dee1ad47SJeff Kirsher 649dee1ad47SJeff Kirsher /* LinkSec (MacSec) Bit Fields and Masks */ 650dee1ad47SJeff Kirsher #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 651dee1ad47SJeff Kirsher #define IXGBE_LSECTXCAP_SUM_SHIFT 16 652dee1ad47SJeff Kirsher #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 653dee1ad47SJeff Kirsher #define IXGBE_LSECRXCAP_SUM_SHIFT 16 654dee1ad47SJeff Kirsher 655dee1ad47SJeff Kirsher #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 656dee1ad47SJeff Kirsher #define IXGBE_LSECTXCTRL_DISABLE 0x0 657dee1ad47SJeff Kirsher #define IXGBE_LSECTXCTRL_AUTH 0x1 658dee1ad47SJeff Kirsher #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 659dee1ad47SJeff Kirsher #define IXGBE_LSECTXCTRL_AISCI 0x00000020 660dee1ad47SJeff Kirsher #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 661dee1ad47SJeff Kirsher #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 662dee1ad47SJeff Kirsher 663dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 664dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_EN_SHIFT 2 665dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_DISABLE 0x0 666dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_CHECK 0x1 667dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_STRICT 0x2 668dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_DROP 0x3 669dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_PLSH 0x00000040 670dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_RP 0x00000080 671dee1ad47SJeff Kirsher #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 672dee1ad47SJeff Kirsher 673dee1ad47SJeff Kirsher /* IpSec Registers */ 674dee1ad47SJeff Kirsher #define IXGBE_IPSTXIDX 0x08900 675dee1ad47SJeff Kirsher #define IXGBE_IPSTXSALT 0x08904 676dee1ad47SJeff Kirsher #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 677dee1ad47SJeff Kirsher #define IXGBE_IPSRXIDX 0x08E00 678dee1ad47SJeff Kirsher #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 679dee1ad47SJeff Kirsher #define IXGBE_IPSRXSPI 0x08E14 680dee1ad47SJeff Kirsher #define IXGBE_IPSRXIPIDX 0x08E18 681dee1ad47SJeff Kirsher #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 682dee1ad47SJeff Kirsher #define IXGBE_IPSRXSALT 0x08E2C 683dee1ad47SJeff Kirsher #define IXGBE_IPSRXMOD 0x08E30 684dee1ad47SJeff Kirsher 685dee1ad47SJeff Kirsher #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 686dee1ad47SJeff Kirsher 687dee1ad47SJeff Kirsher /* DCB registers */ 688dee1ad47SJeff Kirsher #define IXGBE_RTRPCS 0x02430 689dee1ad47SJeff Kirsher #define IXGBE_RTTDCS 0x04900 690dee1ad47SJeff Kirsher #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 691dee1ad47SJeff Kirsher #define IXGBE_RTTPCS 0x0CD00 692dee1ad47SJeff Kirsher #define IXGBE_RTRUP2TC 0x03020 693dee1ad47SJeff Kirsher #define IXGBE_RTTUP2TC 0x0C800 694dee1ad47SJeff Kirsher #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 695dee1ad47SJeff Kirsher #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 696dee1ad47SJeff Kirsher #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 697dee1ad47SJeff Kirsher #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 698dee1ad47SJeff Kirsher #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 699dee1ad47SJeff Kirsher #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 700dee1ad47SJeff Kirsher #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 701dee1ad47SJeff Kirsher #define IXGBE_RTTDQSEL 0x04904 702dee1ad47SJeff Kirsher #define IXGBE_RTTDT1C 0x04908 703dee1ad47SJeff Kirsher #define IXGBE_RTTDT1S 0x0490C 70451e409f1SLeonardo Potenza #define IXGBE_RTTQCNCR 0x08B00 70551e409f1SLeonardo Potenza #define IXGBE_RTTQCNTG 0x04A90 70651e409f1SLeonardo Potenza #define IXGBE_RTTBCNRD 0x0498C 70751e409f1SLeonardo Potenza #define IXGBE_RTTQCNRR 0x0498C 708dee1ad47SJeff Kirsher #define IXGBE_RTTDTECC 0x04990 709dee1ad47SJeff Kirsher #define IXGBE_RTTDTECC_NO_BCN 0x00000100 710dee1ad47SJeff Kirsher #define IXGBE_RTTBCNRC 0x04984 711dee1ad47SJeff Kirsher #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 712dee1ad47SJeff Kirsher #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 713dee1ad47SJeff Kirsher #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 714dee1ad47SJeff Kirsher #define IXGBE_RTTBCNRC_RF_INT_MASK \ 715dee1ad47SJeff Kirsher (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 716dee1ad47SJeff Kirsher #define IXGBE_RTTBCNRM 0x04980 71751e409f1SLeonardo Potenza #define IXGBE_RTTQCNRM 0x04980 718dee1ad47SJeff Kirsher 719ea412015SVasu Dev /* FCoE Direct DMA Context */ 720ea412015SVasu Dev #define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10)) 721dee1ad47SJeff Kirsher /* FCoE DMA Context Registers */ 722dee1ad47SJeff Kirsher #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 723dee1ad47SJeff Kirsher #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 724dee1ad47SJeff Kirsher #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 725dee1ad47SJeff Kirsher #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 726dee1ad47SJeff Kirsher #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ 727dee1ad47SJeff Kirsher #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) 728b4f47a48SJacob Keller #define IXGBE_FCBUFF_VALID BIT(0) /* DMA Context Valid */ 729b4f47a48SJacob Keller #define IXGBE_FCBUFF_BUFFSIZE (3u << 3) /* User Buffer Size */ 730b4f47a48SJacob Keller #define IXGBE_FCBUFF_WRCONTX BIT(7) /* 0: Initiator, 1: Target */ 731dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 732dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 733dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 734dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 735dee1ad47SJeff Kirsher #define IXGBE_FCBUFF_OFFSET_SHIFT 16 736b4f47a48SJacob Keller #define IXGBE_FCDMARW_WE BIT(14) /* Write enable */ 737b4f47a48SJacob Keller #define IXGBE_FCDMARW_RE BIT(15) /* Read enable */ 738dee1ad47SJeff Kirsher #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 739dee1ad47SJeff Kirsher #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 740dee1ad47SJeff Kirsher #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 741dee1ad47SJeff Kirsher 742dee1ad47SJeff Kirsher /* FCoE SOF/EOF */ 743dee1ad47SJeff Kirsher #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 744dee1ad47SJeff Kirsher #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 745dee1ad47SJeff Kirsher #define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 746dee1ad47SJeff Kirsher #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 747ea412015SVasu Dev /* FCoE Direct Filter Context */ 748ea412015SVasu Dev #define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10)) 749ea412015SVasu Dev #define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4)) 750dee1ad47SJeff Kirsher /* FCoE Filter Context Registers */ 751dee1ad47SJeff Kirsher #define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 752dee1ad47SJeff Kirsher #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 753dee1ad47SJeff Kirsher #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 754b4f47a48SJacob Keller #define IXGBE_FCFLT_VALID BIT(0) /* Filter Context Valid */ 755b4f47a48SJacob Keller #define IXGBE_FCFLT_FIRST BIT(1) /* Filter First */ 756dee1ad47SJeff Kirsher #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 757dee1ad47SJeff Kirsher #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 758b4f47a48SJacob Keller #define IXGBE_FCFLTRW_RVALDT BIT(13) /* Fast Re-Validation */ 759b4f47a48SJacob Keller #define IXGBE_FCFLTRW_WE BIT(14) /* Write Enable */ 760b4f47a48SJacob Keller #define IXGBE_FCFLTRW_RE BIT(15) /* Read Enable */ 761dee1ad47SJeff Kirsher /* FCoE Receive Control */ 762dee1ad47SJeff Kirsher #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 763b4f47a48SJacob Keller #define IXGBE_FCRXCTRL_FCOELLI BIT(0) /* Low latency interrupt */ 764b4f47a48SJacob Keller #define IXGBE_FCRXCTRL_SAVBAD BIT(1) /* Save Bad Frames */ 765b4f47a48SJacob Keller #define IXGBE_FCRXCTRL_FRSTRDH BIT(2) /* EN 1st Read Header */ 766b4f47a48SJacob Keller #define IXGBE_FCRXCTRL_LASTSEQH BIT(3) /* EN Last Header in Seq */ 767b4f47a48SJacob Keller #define IXGBE_FCRXCTRL_ALLH BIT(4) /* EN All Headers */ 768b4f47a48SJacob Keller #define IXGBE_FCRXCTRL_FRSTSEQH BIT(5) /* EN 1st Seq. Header */ 769b4f47a48SJacob Keller #define IXGBE_FCRXCTRL_ICRC BIT(6) /* Ignore Bad FC CRC */ 770b4f47a48SJacob Keller #define IXGBE_FCRXCTRL_FCCRCBO BIT(7) /* FC CRC Byte Ordering */ 771dee1ad47SJeff Kirsher #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 772dee1ad47SJeff Kirsher #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 773dee1ad47SJeff Kirsher /* FCoE Redirection */ 774dee1ad47SJeff Kirsher #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 775dee1ad47SJeff Kirsher #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 776dee1ad47SJeff Kirsher #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 777dee1ad47SJeff Kirsher #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 778dee1ad47SJeff Kirsher #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 779dee1ad47SJeff Kirsher #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 780ea412015SVasu Dev #define IXGBE_FCRETA_SIZE_X550 32 /* Max entries in FCRETA */ 781ea412015SVasu Dev /* Higher 7 bits for the queue index */ 782ea412015SVasu Dev #define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000 783ea412015SVasu Dev #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16 784dee1ad47SJeff Kirsher 785dee1ad47SJeff Kirsher /* Stats registers */ 786dee1ad47SJeff Kirsher #define IXGBE_CRCERRS 0x04000 787dee1ad47SJeff Kirsher #define IXGBE_ILLERRC 0x04004 788dee1ad47SJeff Kirsher #define IXGBE_ERRBC 0x04008 789dee1ad47SJeff Kirsher #define IXGBE_MSPDC 0x04010 790dee1ad47SJeff Kirsher #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 791dee1ad47SJeff Kirsher #define IXGBE_MLFC 0x04034 792dee1ad47SJeff Kirsher #define IXGBE_MRFC 0x04038 793dee1ad47SJeff Kirsher #define IXGBE_RLEC 0x04040 794dee1ad47SJeff Kirsher #define IXGBE_LXONTXC 0x03F60 795dee1ad47SJeff Kirsher #define IXGBE_LXONRXC 0x0CF60 796dee1ad47SJeff Kirsher #define IXGBE_LXOFFTXC 0x03F68 797dee1ad47SJeff Kirsher #define IXGBE_LXOFFRXC 0x0CF68 798dee1ad47SJeff Kirsher #define IXGBE_LXONRXCNT 0x041A4 799dee1ad47SJeff Kirsher #define IXGBE_LXOFFRXCNT 0x041A8 800dee1ad47SJeff Kirsher #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 801dee1ad47SJeff Kirsher #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 802dee1ad47SJeff Kirsher #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 803dee1ad47SJeff Kirsher #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 804dee1ad47SJeff Kirsher #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 805dee1ad47SJeff Kirsher #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 806dee1ad47SJeff Kirsher #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 807dee1ad47SJeff Kirsher #define IXGBE_PRC64 0x0405C 808dee1ad47SJeff Kirsher #define IXGBE_PRC127 0x04060 809dee1ad47SJeff Kirsher #define IXGBE_PRC255 0x04064 810dee1ad47SJeff Kirsher #define IXGBE_PRC511 0x04068 811dee1ad47SJeff Kirsher #define IXGBE_PRC1023 0x0406C 812dee1ad47SJeff Kirsher #define IXGBE_PRC1522 0x04070 813dee1ad47SJeff Kirsher #define IXGBE_GPRC 0x04074 814dee1ad47SJeff Kirsher #define IXGBE_BPRC 0x04078 815dee1ad47SJeff Kirsher #define IXGBE_MPRC 0x0407C 816dee1ad47SJeff Kirsher #define IXGBE_GPTC 0x04080 817dee1ad47SJeff Kirsher #define IXGBE_GORCL 0x04088 818dee1ad47SJeff Kirsher #define IXGBE_GORCH 0x0408C 819dee1ad47SJeff Kirsher #define IXGBE_GOTCL 0x04090 820dee1ad47SJeff Kirsher #define IXGBE_GOTCH 0x04094 821dee1ad47SJeff Kirsher #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 822dee1ad47SJeff Kirsher #define IXGBE_RUC 0x040A4 823dee1ad47SJeff Kirsher #define IXGBE_RFC 0x040A8 824dee1ad47SJeff Kirsher #define IXGBE_ROC 0x040AC 825dee1ad47SJeff Kirsher #define IXGBE_RJC 0x040B0 826dee1ad47SJeff Kirsher #define IXGBE_MNGPRC 0x040B4 827dee1ad47SJeff Kirsher #define IXGBE_MNGPDC 0x040B8 828dee1ad47SJeff Kirsher #define IXGBE_MNGPTC 0x0CF90 829dee1ad47SJeff Kirsher #define IXGBE_TORL 0x040C0 830dee1ad47SJeff Kirsher #define IXGBE_TORH 0x040C4 831dee1ad47SJeff Kirsher #define IXGBE_TPR 0x040D0 832dee1ad47SJeff Kirsher #define IXGBE_TPT 0x040D4 833dee1ad47SJeff Kirsher #define IXGBE_PTC64 0x040D8 834dee1ad47SJeff Kirsher #define IXGBE_PTC127 0x040DC 835dee1ad47SJeff Kirsher #define IXGBE_PTC255 0x040E0 836dee1ad47SJeff Kirsher #define IXGBE_PTC511 0x040E4 837dee1ad47SJeff Kirsher #define IXGBE_PTC1023 0x040E8 838dee1ad47SJeff Kirsher #define IXGBE_PTC1522 0x040EC 839dee1ad47SJeff Kirsher #define IXGBE_MPTC 0x040F0 840dee1ad47SJeff Kirsher #define IXGBE_BPTC 0x040F4 841dee1ad47SJeff Kirsher #define IXGBE_XEC 0x04120 842dee1ad47SJeff Kirsher #define IXGBE_SSVPC 0x08780 843dee1ad47SJeff Kirsher 844dee1ad47SJeff Kirsher #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 845dee1ad47SJeff Kirsher #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 846dee1ad47SJeff Kirsher (0x08600 + ((_i) * 4))) 847dee1ad47SJeff Kirsher #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 848dee1ad47SJeff Kirsher 849dee1ad47SJeff Kirsher #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 850dee1ad47SJeff Kirsher #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 851dee1ad47SJeff Kirsher #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 852dee1ad47SJeff Kirsher #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 853dee1ad47SJeff Kirsher #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 854dee1ad47SJeff Kirsher #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 855dee1ad47SJeff Kirsher #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 856dee1ad47SJeff Kirsher #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 857dee1ad47SJeff Kirsher #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 858dee1ad47SJeff Kirsher #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */ 859dee1ad47SJeff Kirsher #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 860dee1ad47SJeff Kirsher #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 861dee1ad47SJeff Kirsher #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 862dee1ad47SJeff Kirsher #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 863dee1ad47SJeff Kirsher #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 864dee1ad47SJeff Kirsher #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 865dee1ad47SJeff Kirsher #define IXGBE_O2BGPTC 0x041C4 866dee1ad47SJeff Kirsher #define IXGBE_O2BSPC 0x087B0 867dee1ad47SJeff Kirsher #define IXGBE_B2OSPC 0x041C0 868dee1ad47SJeff Kirsher #define IXGBE_B2OGPRC 0x02F90 869dee1ad47SJeff Kirsher #define IXGBE_PCRC8ECL 0x0E810 870dee1ad47SJeff Kirsher #define IXGBE_PCRC8ECH 0x0E811 871dee1ad47SJeff Kirsher #define IXGBE_PCRC8ECH_MASK 0x1F 872dee1ad47SJeff Kirsher #define IXGBE_LDPCECL 0x0E820 873dee1ad47SJeff Kirsher #define IXGBE_LDPCECH 0x0E821 874dee1ad47SJeff Kirsher 8756a14ee0cSDon Skidmore /* MII clause 22/28 definitions */ 8766a14ee0cSDon Skidmore #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 8776a14ee0cSDon Skidmore 8786a14ee0cSDon Skidmore #define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register */ 8796a14ee0cSDon Skidmore #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */ 8806a14ee0cSDon Skidmore 8816a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */ 8826a14ee0cSDon Skidmore 8836a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */ 8846ac74394SDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6 /* Speed Mask */ 8856a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */ 8866a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */ 8876a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s H Duplex */ 8886a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s F Duplex */ 8896a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */ 8906a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */ 8916a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */ 8926a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */ 8936ac74394SDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4 /* 1Gb/s */ 8946ac74394SDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6 /* 10Gb/s */ 8956ac74394SDon Skidmore 8966ac74394SDon Skidmore #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 8976ac74394SDon Skidmore #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 8986ac74394SDon Skidmore #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 8996ac74394SDon Skidmore #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 9006ac74394SDon Skidmore #define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400 9016ac74394SDon Skidmore #define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800 9026ac74394SDon Skidmore #define IXGBE_MII_RESTART 0x200 9036ac74394SDon Skidmore #define IXGBE_MII_AUTONEG_LINK_UP 0x04 9046ac74394SDon Skidmore #define IXGBE_MII_AUTONEG_REG 0x0 9056a14ee0cSDon Skidmore 906dee1ad47SJeff Kirsher /* Management */ 907dee1ad47SJeff Kirsher #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 908dee1ad47SJeff Kirsher #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 909dee1ad47SJeff Kirsher #define IXGBE_MANC 0x05820 910dee1ad47SJeff Kirsher #define IXGBE_MFVAL 0x05824 911dee1ad47SJeff Kirsher #define IXGBE_MANC2H 0x05860 912dee1ad47SJeff Kirsher #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 913dee1ad47SJeff Kirsher #define IXGBE_MIPAF 0x058B0 914dee1ad47SJeff Kirsher #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 915dee1ad47SJeff Kirsher #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 916dee1ad47SJeff Kirsher #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 917dee1ad47SJeff Kirsher #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 918dee1ad47SJeff Kirsher #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 919dee1ad47SJeff Kirsher #define IXGBE_LSWFW 0x15014 920dee1ad47SJeff Kirsher 9210b2679d6SDon Skidmore /* Management Bit Fields and Masks */ 9220b2679d6SDon Skidmore #define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ 9230b2679d6SDon Skidmore 9240b2679d6SDon Skidmore /* Firmware Semaphore Register */ 9250b2679d6SDon Skidmore #define IXGBE_FWSM_MODE_MASK 0xE 9260b2679d6SDon Skidmore #define IXGBE_FWSM_FW_MODE_PT 0x4 92759dd45d5SSebastian Basierski #define IXGBE_FWSM_FW_NVM_RECOVERY_MODE BIT(5) 92859dd45d5SSebastian Basierski #define IXGBE_FWSM_EXT_ERR_IND_MASK 0x01F80000 92959dd45d5SSebastian Basierski #define IXGBE_FWSM_FW_VAL_BIT BIT(15) 9300b2679d6SDon Skidmore 931dee1ad47SJeff Kirsher /* ARC Subsystem registers */ 932dee1ad47SJeff Kirsher #define IXGBE_HICR 0x15F00 933dee1ad47SJeff Kirsher #define IXGBE_FWSTS 0x15F0C 934dee1ad47SJeff Kirsher #define IXGBE_HSMC0R 0x15F04 935dee1ad47SJeff Kirsher #define IXGBE_HSMC1R 0x15F08 936dee1ad47SJeff Kirsher #define IXGBE_SWSR 0x15F10 937dee1ad47SJeff Kirsher #define IXGBE_HFDR 0x15FE8 938dee1ad47SJeff Kirsher #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 939dee1ad47SJeff Kirsher 940dee1ad47SJeff Kirsher #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 941dee1ad47SJeff Kirsher /* Driver sets this bit when done to put command in RAM */ 942dee1ad47SJeff Kirsher #define IXGBE_HICR_C 0x02 943dee1ad47SJeff Kirsher #define IXGBE_HICR_SV 0x04 /* Status Validity */ 944dee1ad47SJeff Kirsher #define IXGBE_HICR_FW_RESET_ENABLE 0x40 945dee1ad47SJeff Kirsher #define IXGBE_HICR_FW_RESET 0x80 946dee1ad47SJeff Kirsher 947dee1ad47SJeff Kirsher /* PCI-E registers */ 948dee1ad47SJeff Kirsher #define IXGBE_GCR 0x11000 949dee1ad47SJeff Kirsher #define IXGBE_GTV 0x11004 950dee1ad47SJeff Kirsher #define IXGBE_FUNCTAG 0x11008 951dee1ad47SJeff Kirsher #define IXGBE_GLT 0x1100C 952dee1ad47SJeff Kirsher #define IXGBE_GSCL_1 0x11010 953dee1ad47SJeff Kirsher #define IXGBE_GSCL_2 0x11014 954dee1ad47SJeff Kirsher #define IXGBE_GSCL_3 0x11018 955dee1ad47SJeff Kirsher #define IXGBE_GSCL_4 0x1101C 956dee1ad47SJeff Kirsher #define IXGBE_GSCN_0 0x11020 957dee1ad47SJeff Kirsher #define IXGBE_GSCN_1 0x11024 958dee1ad47SJeff Kirsher #define IXGBE_GSCN_2 0x11028 959dee1ad47SJeff Kirsher #define IXGBE_GSCN_3 0x1102C 9609a900ecaSDon Skidmore #define IXGBE_FACTPS_8259X 0x10150 9619a900ecaSDon Skidmore #define IXGBE_FACTPS_X540 IXGBE_FACTPS_8259X 9629a900ecaSDon Skidmore #define IXGBE_FACTPS_X550 IXGBE_FACTPS_8259X 9639a900ecaSDon Skidmore #define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS_8259X 9649a900ecaSDon Skidmore #define IXGBE_FACTPS_X550EM_a 0x15FEC 9659a900ecaSDon Skidmore #define IXGBE_FACTPS(_hw) IXGBE_BY_MAC((_hw), FACTPS) 9669a900ecaSDon Skidmore 967dee1ad47SJeff Kirsher #define IXGBE_PCIEANACTL 0x11040 9689a900ecaSDon Skidmore #define IXGBE_SWSM_8259X 0x10140 9699a900ecaSDon Skidmore #define IXGBE_SWSM_X540 IXGBE_SWSM_8259X 9709a900ecaSDon Skidmore #define IXGBE_SWSM_X550 IXGBE_SWSM_8259X 9719a900ecaSDon Skidmore #define IXGBE_SWSM_X550EM_x IXGBE_SWSM_8259X 9729a900ecaSDon Skidmore #define IXGBE_SWSM_X550EM_a 0x15F70 9739a900ecaSDon Skidmore #define IXGBE_SWSM(_hw) IXGBE_BY_MAC((_hw), SWSM) 9749a900ecaSDon Skidmore #define IXGBE_FWSM_8259X 0x10148 9759a900ecaSDon Skidmore #define IXGBE_FWSM_X540 IXGBE_FWSM_8259X 9769a900ecaSDon Skidmore #define IXGBE_FWSM_X550 IXGBE_FWSM_8259X 9779a900ecaSDon Skidmore #define IXGBE_FWSM_X550EM_x IXGBE_FWSM_8259X 9789a900ecaSDon Skidmore #define IXGBE_FWSM_X550EM_a 0x15F74 9799a900ecaSDon Skidmore #define IXGBE_FWSM(_hw) IXGBE_BY_MAC((_hw), FWSM) 980dee1ad47SJeff Kirsher #define IXGBE_GSSR 0x10160 981dee1ad47SJeff Kirsher #define IXGBE_MREVID 0x11064 982dee1ad47SJeff Kirsher #define IXGBE_DCA_ID 0x11070 983dee1ad47SJeff Kirsher #define IXGBE_DCA_CTRL 0x11074 9849a900ecaSDon Skidmore #define IXGBE_SWFW_SYNC_8259X IXGBE_GSSR 9859a900ecaSDon Skidmore #define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC_8259X 9869a900ecaSDon Skidmore #define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC_8259X 9879a900ecaSDon Skidmore #define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC_8259X 9889a900ecaSDon Skidmore #define IXGBE_SWFW_SYNC_X550EM_a 0x15F78 9899a900ecaSDon Skidmore #define IXGBE_SWFW_SYNC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC) 990dee1ad47SJeff Kirsher 991dee1ad47SJeff Kirsher /* PCIe registers 82599-specific */ 992dee1ad47SJeff Kirsher #define IXGBE_GCR_EXT 0x11050 993dee1ad47SJeff Kirsher #define IXGBE_GSCL_5_82599 0x11030 994dee1ad47SJeff Kirsher #define IXGBE_GSCL_6_82599 0x11034 995dee1ad47SJeff Kirsher #define IXGBE_GSCL_7_82599 0x11038 996dee1ad47SJeff Kirsher #define IXGBE_GSCL_8_82599 0x1103C 997dee1ad47SJeff Kirsher #define IXGBE_PHYADR_82599 0x11040 998dee1ad47SJeff Kirsher #define IXGBE_PHYDAT_82599 0x11044 999dee1ad47SJeff Kirsher #define IXGBE_PHYCTL_82599 0x11048 1000dee1ad47SJeff Kirsher #define IXGBE_PBACLR_82599 0x11068 10019a900ecaSDon Skidmore 10029a900ecaSDon Skidmore #define IXGBE_CIAA_8259X 0x11088 10039a900ecaSDon Skidmore #define IXGBE_CIAA_X540 IXGBE_CIAA_8259X 10049a75a1acSDon Skidmore #define IXGBE_CIAA_X550 0x11508 10059a900ecaSDon Skidmore #define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550 10069a900ecaSDon Skidmore #define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550 10079a900ecaSDon Skidmore #define IXGBE_CIAA(_hw) IXGBE_BY_MAC((_hw), CIAA) 10089a900ecaSDon Skidmore 10099a900ecaSDon Skidmore #define IXGBE_CIAD_8259X 0x1108C 10109a900ecaSDon Skidmore #define IXGBE_CIAD_X540 IXGBE_CIAD_8259X 10119a75a1acSDon Skidmore #define IXGBE_CIAD_X550 0x11510 10129a900ecaSDon Skidmore #define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550 10139a900ecaSDon Skidmore #define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550 10149a900ecaSDon Skidmore #define IXGBE_CIAD(_hw) IXGBE_BY_MAC((_hw), CIAD) 10159a900ecaSDon Skidmore 1016dee1ad47SJeff Kirsher #define IXGBE_PICAUSE 0x110B0 1017dee1ad47SJeff Kirsher #define IXGBE_PIENA 0x110B8 1018dee1ad47SJeff Kirsher #define IXGBE_CDQ_MBR_82599 0x110B4 1019dee1ad47SJeff Kirsher #define IXGBE_PCIESPARE 0x110BC 1020dee1ad47SJeff Kirsher #define IXGBE_MISC_REG_82599 0x110F0 1021dee1ad47SJeff Kirsher #define IXGBE_ECC_CTRL_0_82599 0x11100 1022dee1ad47SJeff Kirsher #define IXGBE_ECC_CTRL_1_82599 0x11104 1023dee1ad47SJeff Kirsher #define IXGBE_ECC_STATUS_82599 0x110E0 1024dee1ad47SJeff Kirsher #define IXGBE_BAR_CTRL_82599 0x110F4 1025dee1ad47SJeff Kirsher 1026dee1ad47SJeff Kirsher /* PCI Express Control */ 1027dee1ad47SJeff Kirsher #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 1028dee1ad47SJeff Kirsher #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 1029dee1ad47SJeff Kirsher #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 1030dee1ad47SJeff Kirsher #define IXGBE_GCR_CAP_VER2 0x00040000 1031dee1ad47SJeff Kirsher 1032dee1ad47SJeff Kirsher #define IXGBE_GCR_EXT_MSIX_EN 0x80000000 1033ff9d1a5aSEmil Tantilov #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 1034dee1ad47SJeff Kirsher #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 1035dee1ad47SJeff Kirsher #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 1036dee1ad47SJeff Kirsher #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 1037dee1ad47SJeff Kirsher #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 1038dee1ad47SJeff Kirsher IXGBE_GCR_EXT_VT_MODE_64) 1039dee1ad47SJeff Kirsher 1040dee1ad47SJeff Kirsher /* Time Sync Registers */ 1041dee1ad47SJeff Kirsher #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 1042dee1ad47SJeff Kirsher #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 1043dee1ad47SJeff Kirsher #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 1044dee1ad47SJeff Kirsher #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 1045dee1ad47SJeff Kirsher #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 1046dee1ad47SJeff Kirsher #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 1047dee1ad47SJeff Kirsher #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 1048dee1ad47SJeff Kirsher #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 1049dee1ad47SJeff Kirsher #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 1050dee1ad47SJeff Kirsher #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 1051dee1ad47SJeff Kirsher #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 1052a9763f3cSMark Rustad #define IXGBE_SYSTIMR 0x08C58 /* System time register Residue - RO */ 1053dee1ad47SJeff Kirsher #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 1054dee1ad47SJeff Kirsher #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 1055dee1ad47SJeff Kirsher #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 1056dee1ad47SJeff Kirsher #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 1057dee1ad47SJeff Kirsher #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 1058dee1ad47SJeff Kirsher #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 1059dee1ad47SJeff Kirsher #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 1060dee1ad47SJeff Kirsher #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 1061681ae1adSJacob E Keller #define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ 1062681ae1adSJacob E Keller #define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ 1063dee1ad47SJeff Kirsher #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 1064dee1ad47SJeff Kirsher #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 1065dee1ad47SJeff Kirsher #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 1066dee1ad47SJeff Kirsher #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 1067dee1ad47SJeff Kirsher #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 1068dee1ad47SJeff Kirsher #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 1069a9763f3cSMark Rustad #define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */ 1070cd458320SJacob Keller #define IXGBE_TSSDP 0x0003C /* TimeSync SDP Configuration Register - RW */ 1071dee1ad47SJeff Kirsher 1072dee1ad47SJeff Kirsher /* Diagnostic Registers */ 1073dee1ad47SJeff Kirsher #define IXGBE_RDSTATCTL 0x02C20 1074dee1ad47SJeff Kirsher #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 1075dee1ad47SJeff Kirsher #define IXGBE_RDHMPN 0x02F08 1076dee1ad47SJeff Kirsher #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 1077dee1ad47SJeff Kirsher #define IXGBE_RDPROBE 0x02F20 1078dee1ad47SJeff Kirsher #define IXGBE_RDMAM 0x02F30 1079dee1ad47SJeff Kirsher #define IXGBE_RDMAD 0x02F34 1080dee1ad47SJeff Kirsher #define IXGBE_TDSTATCTL 0x07C20 1081dee1ad47SJeff Kirsher #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 1082dee1ad47SJeff Kirsher #define IXGBE_TDHMPN 0x07F08 1083dee1ad47SJeff Kirsher #define IXGBE_TDHMPN2 0x082FC 1084dee1ad47SJeff Kirsher #define IXGBE_TXDESCIC 0x082CC 1085dee1ad47SJeff Kirsher #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 1086dee1ad47SJeff Kirsher #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 1087dee1ad47SJeff Kirsher #define IXGBE_TDPROBE 0x07F20 1088dee1ad47SJeff Kirsher #define IXGBE_TXBUFCTRL 0x0C600 108945a88dfcSPreethi Banala #define IXGBE_TXBUFDATA(_i) (0x0C610 + ((_i) * 4)) /* 4 of these (0-3) */ 1090dee1ad47SJeff Kirsher #define IXGBE_RXBUFCTRL 0x03600 109145a88dfcSPreethi Banala #define IXGBE_RXBUFDATA(_i) (0x03610 + ((_i) * 4)) /* 4 of these (0-3) */ 1092dee1ad47SJeff Kirsher #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 1093dee1ad47SJeff Kirsher #define IXGBE_RFVAL 0x050A4 1094dee1ad47SJeff Kirsher #define IXGBE_MDFTC1 0x042B8 1095dee1ad47SJeff Kirsher #define IXGBE_MDFTC2 0x042C0 1096dee1ad47SJeff Kirsher #define IXGBE_MDFTFIFO1 0x042C4 1097dee1ad47SJeff Kirsher #define IXGBE_MDFTFIFO2 0x042C8 1098dee1ad47SJeff Kirsher #define IXGBE_MDFTS 0x042CC 1099dee1ad47SJeff Kirsher #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 1100dee1ad47SJeff Kirsher #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 1101dee1ad47SJeff Kirsher #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 1102dee1ad47SJeff Kirsher #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 1103dee1ad47SJeff Kirsher #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 1104dee1ad47SJeff Kirsher #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 1105dee1ad47SJeff Kirsher #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 1106dee1ad47SJeff Kirsher #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 1107dee1ad47SJeff Kirsher #define IXGBE_PCIEECCCTL 0x1106C 1108dee1ad47SJeff Kirsher #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 1109dee1ad47SJeff Kirsher #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 1110dee1ad47SJeff Kirsher #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 1111dee1ad47SJeff Kirsher #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 1112dee1ad47SJeff Kirsher #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 1113dee1ad47SJeff Kirsher #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 1114dee1ad47SJeff Kirsher #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 1115dee1ad47SJeff Kirsher #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 1116dee1ad47SJeff Kirsher #define IXGBE_PCIEECCCTL0 0x11100 1117dee1ad47SJeff Kirsher #define IXGBE_PCIEECCCTL1 0x11104 1118dee1ad47SJeff Kirsher #define IXGBE_RXDBUECC 0x03F70 1119dee1ad47SJeff Kirsher #define IXGBE_TXDBUECC 0x0CF70 1120dee1ad47SJeff Kirsher #define IXGBE_RXDBUEST 0x03F74 1121dee1ad47SJeff Kirsher #define IXGBE_TXDBUEST 0x0CF74 1122dee1ad47SJeff Kirsher #define IXGBE_PBTXECC 0x0C300 1123dee1ad47SJeff Kirsher #define IXGBE_PBRXECC 0x03300 1124dee1ad47SJeff Kirsher #define IXGBE_GHECCR 0x110B0 1125dee1ad47SJeff Kirsher 1126dee1ad47SJeff Kirsher /* MAC Registers */ 1127dee1ad47SJeff Kirsher #define IXGBE_PCS1GCFIG 0x04200 1128dee1ad47SJeff Kirsher #define IXGBE_PCS1GLCTL 0x04208 1129dee1ad47SJeff Kirsher #define IXGBE_PCS1GLSTA 0x0420C 1130dee1ad47SJeff Kirsher #define IXGBE_PCS1GDBG0 0x04210 1131dee1ad47SJeff Kirsher #define IXGBE_PCS1GDBG1 0x04214 1132dee1ad47SJeff Kirsher #define IXGBE_PCS1GANA 0x04218 1133dee1ad47SJeff Kirsher #define IXGBE_PCS1GANLP 0x0421C 1134dee1ad47SJeff Kirsher #define IXGBE_PCS1GANNP 0x04220 1135dee1ad47SJeff Kirsher #define IXGBE_PCS1GANLPNP 0x04224 1136dee1ad47SJeff Kirsher #define IXGBE_HLREG0 0x04240 1137dee1ad47SJeff Kirsher #define IXGBE_HLREG1 0x04244 1138dee1ad47SJeff Kirsher #define IXGBE_PAP 0x04248 1139dee1ad47SJeff Kirsher #define IXGBE_MACA 0x0424C 1140dee1ad47SJeff Kirsher #define IXGBE_APAE 0x04250 1141dee1ad47SJeff Kirsher #define IXGBE_ARD 0x04254 1142dee1ad47SJeff Kirsher #define IXGBE_AIS 0x04258 1143dee1ad47SJeff Kirsher #define IXGBE_MSCA 0x0425C 1144dee1ad47SJeff Kirsher #define IXGBE_MSRWD 0x04260 1145dee1ad47SJeff Kirsher #define IXGBE_MLADD 0x04264 1146dee1ad47SJeff Kirsher #define IXGBE_MHADD 0x04268 1147dee1ad47SJeff Kirsher #define IXGBE_MAXFRS 0x04268 1148dee1ad47SJeff Kirsher #define IXGBE_TREG 0x0426C 1149dee1ad47SJeff Kirsher #define IXGBE_PCSS1 0x04288 1150dee1ad47SJeff Kirsher #define IXGBE_PCSS2 0x0428C 1151dee1ad47SJeff Kirsher #define IXGBE_XPCSS 0x04290 1152dee1ad47SJeff Kirsher #define IXGBE_MFLCN 0x04294 1153dee1ad47SJeff Kirsher #define IXGBE_SERDESC 0x04298 11542f2219beSMark Rustad #define IXGBE_MAC_SGMII_BUSY 0x04298 1155dee1ad47SJeff Kirsher #define IXGBE_MACS 0x0429C 1156dee1ad47SJeff Kirsher #define IXGBE_AUTOC 0x042A0 1157dee1ad47SJeff Kirsher #define IXGBE_LINKS 0x042A4 1158dee1ad47SJeff Kirsher #define IXGBE_LINKS2 0x04324 1159dee1ad47SJeff Kirsher #define IXGBE_AUTOC2 0x042A8 1160dee1ad47SJeff Kirsher #define IXGBE_AUTOC3 0x042AC 1161dee1ad47SJeff Kirsher #define IXGBE_ANLP1 0x042B0 1162dee1ad47SJeff Kirsher #define IXGBE_ANLP2 0x042B4 1163dee1ad47SJeff Kirsher #define IXGBE_MACC 0x04330 1164dee1ad47SJeff Kirsher #define IXGBE_ATLASCTL 0x04800 1165dee1ad47SJeff Kirsher #define IXGBE_MMNGC 0x042D0 1166dee1ad47SJeff Kirsher #define IXGBE_ANLPNP1 0x042D4 1167dee1ad47SJeff Kirsher #define IXGBE_ANLPNP2 0x042D8 1168dee1ad47SJeff Kirsher #define IXGBE_KRPCSFC 0x042E0 1169dee1ad47SJeff Kirsher #define IXGBE_KRPCSS 0x042E4 1170dee1ad47SJeff Kirsher #define IXGBE_FECS1 0x042E8 1171dee1ad47SJeff Kirsher #define IXGBE_FECS2 0x042EC 1172dee1ad47SJeff Kirsher #define IXGBE_SMADARCTL 0x14F10 1173dee1ad47SJeff Kirsher #define IXGBE_MPVC 0x04318 1174dee1ad47SJeff Kirsher #define IXGBE_SGMIIC 0x04314 1175dee1ad47SJeff Kirsher 1176dee1ad47SJeff Kirsher /* Statistics Registers */ 1177dee1ad47SJeff Kirsher #define IXGBE_RXNFGPC 0x041B0 1178dee1ad47SJeff Kirsher #define IXGBE_RXNFGBCL 0x041B4 1179dee1ad47SJeff Kirsher #define IXGBE_RXNFGBCH 0x041B8 1180dee1ad47SJeff Kirsher #define IXGBE_RXDGPC 0x02F50 1181dee1ad47SJeff Kirsher #define IXGBE_RXDGBCL 0x02F54 1182dee1ad47SJeff Kirsher #define IXGBE_RXDGBCH 0x02F58 1183dee1ad47SJeff Kirsher #define IXGBE_RXDDGPC 0x02F5C 1184dee1ad47SJeff Kirsher #define IXGBE_RXDDGBCL 0x02F60 1185dee1ad47SJeff Kirsher #define IXGBE_RXDDGBCH 0x02F64 1186dee1ad47SJeff Kirsher #define IXGBE_RXLPBKGPC 0x02F68 1187dee1ad47SJeff Kirsher #define IXGBE_RXLPBKGBCL 0x02F6C 1188dee1ad47SJeff Kirsher #define IXGBE_RXLPBKGBCH 0x02F70 1189dee1ad47SJeff Kirsher #define IXGBE_RXDLPBKGPC 0x02F74 1190dee1ad47SJeff Kirsher #define IXGBE_RXDLPBKGBCL 0x02F78 1191dee1ad47SJeff Kirsher #define IXGBE_RXDLPBKGBCH 0x02F7C 1192dee1ad47SJeff Kirsher #define IXGBE_TXDGPC 0x087A0 1193dee1ad47SJeff Kirsher #define IXGBE_TXDGBCL 0x087A4 1194dee1ad47SJeff Kirsher #define IXGBE_TXDGBCH 0x087A8 1195dee1ad47SJeff Kirsher 1196dee1ad47SJeff Kirsher #define IXGBE_RXDSTATCTRL 0x02F40 1197dee1ad47SJeff Kirsher 1198dee1ad47SJeff Kirsher /* Copper Pond 2 link timeout */ 1199dee1ad47SJeff Kirsher #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 1200dee1ad47SJeff Kirsher 1201dee1ad47SJeff Kirsher /* Omer CORECTL */ 1202dee1ad47SJeff Kirsher #define IXGBE_CORECTL 0x014F00 1203dee1ad47SJeff Kirsher /* BARCTRL */ 1204dee1ad47SJeff Kirsher #define IXGBE_BARCTRL 0x110F4 1205dee1ad47SJeff Kirsher #define IXGBE_BARCTRL_FLSIZE 0x0700 1206dee1ad47SJeff Kirsher #define IXGBE_BARCTRL_FLSIZE_SHIFT 8 1207dee1ad47SJeff Kirsher #define IXGBE_BARCTRL_CSRSIZE 0x2000 1208dee1ad47SJeff Kirsher 1209dee1ad47SJeff Kirsher /* RSCCTL Bit Masks */ 1210dee1ad47SJeff Kirsher #define IXGBE_RSCCTL_RSCEN 0x01 1211dee1ad47SJeff Kirsher #define IXGBE_RSCCTL_MAXDESC_1 0x00 1212dee1ad47SJeff Kirsher #define IXGBE_RSCCTL_MAXDESC_4 0x04 1213dee1ad47SJeff Kirsher #define IXGBE_RSCCTL_MAXDESC_8 0x08 1214dee1ad47SJeff Kirsher #define IXGBE_RSCCTL_MAXDESC_16 0x0C 1215dee1ad47SJeff Kirsher 1216dee1ad47SJeff Kirsher /* RSCDBU Bit Masks */ 1217dee1ad47SJeff Kirsher #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 1218dee1ad47SJeff Kirsher #define IXGBE_RSCDBU_RSCACKDIS 0x00000080 1219dee1ad47SJeff Kirsher 1220dee1ad47SJeff Kirsher /* RDRXCTL Bit Masks */ 1221dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ 1222dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1223f961ddaeSMark Rustad #define IXGBE_RDRXCTL_PSP 0x00000004 /* Pad small packet */ 1224dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_MVMEN 0x00000020 1225dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1226dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 1227dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 1228dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ 1229dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */ 1230dee1ad47SJeff Kirsher #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */ 1231207969b9SMark Rustad #define IXGBE_RDRXCTL_MBINTEN 0x10000000 1232207969b9SMark Rustad #define IXGBE_RDRXCTL_MDP_EN 0x20000000 1233dee1ad47SJeff Kirsher 1234dee1ad47SJeff Kirsher /* RQTC Bit Masks and Shifts */ 1235dee1ad47SJeff Kirsher #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 1236dee1ad47SJeff Kirsher #define IXGBE_RQTC_TC0_MASK (0x7 << 0) 1237dee1ad47SJeff Kirsher #define IXGBE_RQTC_TC1_MASK (0x7 << 4) 1238dee1ad47SJeff Kirsher #define IXGBE_RQTC_TC2_MASK (0x7 << 8) 1239dee1ad47SJeff Kirsher #define IXGBE_RQTC_TC3_MASK (0x7 << 12) 1240dee1ad47SJeff Kirsher #define IXGBE_RQTC_TC4_MASK (0x7 << 16) 1241dee1ad47SJeff Kirsher #define IXGBE_RQTC_TC5_MASK (0x7 << 20) 1242dee1ad47SJeff Kirsher #define IXGBE_RQTC_TC6_MASK (0x7 << 24) 1243dee1ad47SJeff Kirsher #define IXGBE_RQTC_TC7_MASK (0x7 << 28) 1244dee1ad47SJeff Kirsher 1245dee1ad47SJeff Kirsher /* PSRTYPE.RQPL Bit masks and shift */ 1246dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_RQPL_MASK 0x7 1247dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_RQPL_SHIFT 29 1248dee1ad47SJeff Kirsher 1249dee1ad47SJeff Kirsher /* CTRL Bit Masks */ 125093b067f1SPiotr Skajewski #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Primary Disable bit */ 1251dee1ad47SJeff Kirsher #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 1252dee1ad47SJeff Kirsher #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 12538132b54eSAlexander Duyck #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 1254dee1ad47SJeff Kirsher 1255dee1ad47SJeff Kirsher /* FACTPS */ 12560b2679d6SDon Skidmore #define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */ 1257dee1ad47SJeff Kirsher #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 1258dee1ad47SJeff Kirsher 1259dee1ad47SJeff Kirsher /* MHADD Bit Masks */ 1260dee1ad47SJeff Kirsher #define IXGBE_MHADD_MFS_MASK 0xFFFF0000 1261dee1ad47SJeff Kirsher #define IXGBE_MHADD_MFS_SHIFT 16 1262dee1ad47SJeff Kirsher 1263dee1ad47SJeff Kirsher /* Extended Device Control */ 1264dee1ad47SJeff Kirsher #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 1265dee1ad47SJeff Kirsher #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 1266dee1ad47SJeff Kirsher #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1267dee1ad47SJeff Kirsher #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1268dee1ad47SJeff Kirsher 1269dee1ad47SJeff Kirsher /* Direct Cache Access (DCA) definitions */ 1270dee1ad47SJeff Kirsher #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 1271dee1ad47SJeff Kirsher #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 1272dee1ad47SJeff Kirsher 1273dee1ad47SJeff Kirsher #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 1274dee1ad47SJeff Kirsher #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 1275dee1ad47SJeff Kirsher 1276dee1ad47SJeff Kirsher #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1277dee1ad47SJeff Kirsher #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1278dee1ad47SJeff Kirsher #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1279b4f47a48SJacob Keller #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */ 1280b4f47a48SJacob Keller #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */ 1281b4f47a48SJacob Keller #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */ 1282b4f47a48SJacob Keller #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */ 1283b4f47a48SJacob Keller #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ 1284b4f47a48SJacob Keller #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ 1285dee1ad47SJeff Kirsher 1286dee1ad47SJeff Kirsher #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1287dee1ad47SJeff Kirsher #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1288dee1ad47SJeff Kirsher #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1289b4f47a48SJacob Keller #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ 1290b4f47a48SJacob Keller #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ 1291b4f47a48SJacob Keller #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ 1292b4f47a48SJacob Keller #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ 1293dee1ad47SJeff Kirsher #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1294dee1ad47SJeff Kirsher 1295dee1ad47SJeff Kirsher /* MSCA Bit Masks */ 1296dee1ad47SJeff Kirsher #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ 1297dee1ad47SJeff Kirsher #define IXGBE_MSCA_NP_ADDR_SHIFT 0 1298dee1ad47SJeff Kirsher #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ 1299dee1ad47SJeff Kirsher #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ 1300dee1ad47SJeff Kirsher #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 1301dee1ad47SJeff Kirsher #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 1302dee1ad47SJeff Kirsher #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 1303dee1ad47SJeff Kirsher #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 1304dee1ad47SJeff Kirsher #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 1305dee1ad47SJeff Kirsher #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ 1306dee1ad47SJeff Kirsher #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */ 1307dee1ad47SJeff Kirsher #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/ 1308dee1ad47SJeff Kirsher #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 1309dee1ad47SJeff Kirsher #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 1310dee1ad47SJeff Kirsher #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ 1311dee1ad47SJeff Kirsher #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ 1312dee1ad47SJeff Kirsher #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 1313dee1ad47SJeff Kirsher #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ 1314dee1ad47SJeff Kirsher 1315dee1ad47SJeff Kirsher /* MSRWD bit masks */ 1316dee1ad47SJeff Kirsher #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 1317dee1ad47SJeff Kirsher #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 1318dee1ad47SJeff Kirsher #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 1319dee1ad47SJeff Kirsher #define IXGBE_MSRWD_READ_DATA_SHIFT 16 1320dee1ad47SJeff Kirsher 1321dee1ad47SJeff Kirsher /* Atlas registers */ 1322dee1ad47SJeff Kirsher #define IXGBE_ATLAS_PDN_LPBK 0x24 1323dee1ad47SJeff Kirsher #define IXGBE_ATLAS_PDN_10G 0xB 1324dee1ad47SJeff Kirsher #define IXGBE_ATLAS_PDN_1G 0xC 1325dee1ad47SJeff Kirsher #define IXGBE_ATLAS_PDN_AN 0xD 1326dee1ad47SJeff Kirsher 1327dee1ad47SJeff Kirsher /* Atlas bit masks */ 1328dee1ad47SJeff Kirsher #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 1329dee1ad47SJeff Kirsher #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 1330dee1ad47SJeff Kirsher #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 1331dee1ad47SJeff Kirsher #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 1332dee1ad47SJeff Kirsher #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 1333dee1ad47SJeff Kirsher 1334dee1ad47SJeff Kirsher /* Omer bit masks */ 1335dee1ad47SJeff Kirsher #define IXGBE_CORECTL_WRITE_CMD 0x00010000 1336dee1ad47SJeff Kirsher 1337dee1ad47SJeff Kirsher /* MDIO definitions */ 1338dee1ad47SJeff Kirsher 13392d40cd17SMark Rustad #define IXGBE_MDIO_ZERO_DEV_TYPE 0x0 13406a14ee0cSDon Skidmore #define IXGBE_MDIO_PCS_DEV_TYPE 0x3 13416a14ee0cSDon Skidmore #define IXGBE_TWINAX_DEV 1 13426a14ee0cSDon Skidmore 1343dee1ad47SJeff Kirsher #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1344dee1ad47SJeff Kirsher 1345dee1ad47SJeff Kirsher #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1346dee1ad47SJeff Kirsher #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ 1347dee1ad47SJeff Kirsher #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1348dee1ad47SJeff Kirsher #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1349dee1ad47SJeff Kirsher 13506a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */ 13516ac74394SDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */ 1352c3dc4c09SDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */ 1353c3dc4c09SDon Skidmore #define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */ 13546a14ee0cSDon Skidmore #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */ 13556a14ee0cSDon Skidmore 1356961fac88SDon Skidmore #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ 13576ac74394SDon Skidmore #define IXGBE_AUTO_NEG_LP_STATUS 0xE820 /* AUTO NEG Rx LP Status Reg */ 13586ac74394SDon Skidmore #define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000 /* AUTO NEG Rx LP 1000BaseT */ 13596a14ee0cSDon Skidmore #define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */ 13606a14ee0cSDon Skidmore #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */ 13616a14ee0cSDon Skidmore #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */ 13626a14ee0cSDon Skidmore #define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */ 1363c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00 /* int std mask */ 1364c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00 /* chip std int flag */ 1365c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01 /* int chip-wide mask */ 1366c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01 /* int chip-wide mask */ 1367c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00 /* Global alarm 1 */ 136883a9fb20SMark Rustad #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010 /* device fault */ 1369c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000 /* high temp failure */ 137083a9fb20SMark Rustad #define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* global fault msg */ 137183a9fb20SMark Rustad #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */ 1372c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */ 1373c3dc4c09SDon Skidmore /* autoneg vendor alarm int enable */ 1374c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 1375c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */ 1376c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */ 1377c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */ 1378c3dc4c09SDon Skidmore #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */ 137983a9fb20SMark Rustad #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /*int dev fault enable */ 13806a14ee0cSDon Skidmore 1381dee1ad47SJeff Kirsher #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1382dee1ad47SJeff Kirsher #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 13836a14ee0cSDon Skidmore #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Stat Reg */ 1384c3dc4c09SDon Skidmore #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */ 1385c3dc4c09SDon Skidmore #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */ 13866a14ee0cSDon Skidmore #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Tx Dis Reg */ 13876a14ee0cSDon Skidmore #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Tx Dis */ 1388dee1ad47SJeff Kirsher 1389dee1ad47SJeff Kirsher /* MII clause 22/28 definitions */ 1390dee1ad47SJeff Kirsher #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1391dee1ad47SJeff Kirsher #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1392dee1ad47SJeff Kirsher #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1393dee1ad47SJeff Kirsher #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1394dee1ad47SJeff Kirsher #define IXGBE_MII_AUTONEG_REG 0x0 1395dee1ad47SJeff Kirsher 1396dee1ad47SJeff Kirsher #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1397dee1ad47SJeff Kirsher #define IXGBE_MAX_PHY_ADDR 32 1398dee1ad47SJeff Kirsher 1399dee1ad47SJeff Kirsher /* PHY IDs*/ 1400dee1ad47SJeff Kirsher #define TN1010_PHY_ID 0x00A19410 1401dee1ad47SJeff Kirsher #define TNX_FW_REV 0xB 1402dee1ad47SJeff Kirsher #define X540_PHY_ID 0x01540200 14035f1c3589SDon Skidmore #define X550_PHY_ID2 0x01540223 14045f1c3589SDon Skidmore #define X550_PHY_ID3 0x01540221 1405c2c78d5cSDon Skidmore #define X557_PHY_ID 0x01540240 1406470739b5SDon Skidmore #define X557_PHY_ID2 0x01540250 1407dee1ad47SJeff Kirsher #define QT2022_PHY_ID 0x0043A400 1408dee1ad47SJeff Kirsher #define ATH_PHY_ID 0x03429050 1409dee1ad47SJeff Kirsher #define AQ_FW_REV 0x20 141047222864SJostar Yang #define BCM54616S_E_PHY_ID 0x03625D10 1411dee1ad47SJeff Kirsher 1412dee1ad47SJeff Kirsher /* Special PHY Init Routine */ 1413dee1ad47SJeff Kirsher #define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1414dee1ad47SJeff Kirsher #define IXGBE_PHY_INIT_END_NL 0xFFFF 1415dee1ad47SJeff Kirsher #define IXGBE_CONTROL_MASK_NL 0xF000 1416dee1ad47SJeff Kirsher #define IXGBE_DATA_MASK_NL 0x0FFF 1417dee1ad47SJeff Kirsher #define IXGBE_CONTROL_SHIFT_NL 12 1418dee1ad47SJeff Kirsher #define IXGBE_DELAY_NL 0 1419dee1ad47SJeff Kirsher #define IXGBE_DATA_NL 1 1420dee1ad47SJeff Kirsher #define IXGBE_CONTROL_NL 0x000F 1421dee1ad47SJeff Kirsher #define IXGBE_CONTROL_EOL_NL 0x0FFF 1422dee1ad47SJeff Kirsher #define IXGBE_CONTROL_SOL_NL 0x0000 1423dee1ad47SJeff Kirsher 1424dee1ad47SJeff Kirsher /* General purpose Interrupt Enable */ 14259a900ecaSDon Skidmore #define IXGBE_SDP0_GPIEN_8259X 0x00000001 /* SDP0 */ 14269a900ecaSDon Skidmore #define IXGBE_SDP1_GPIEN_8259X 0x00000002 /* SDP1 */ 14279a900ecaSDon Skidmore #define IXGBE_SDP2_GPIEN_8259X 0x00000004 /* SDP2 */ 14289a900ecaSDon Skidmore #define IXGBE_SDP0_GPIEN_X540 0x00000002 /* SDP0 on X540 and X550 */ 14299a900ecaSDon Skidmore #define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */ 14309a900ecaSDon Skidmore #define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */ 14319a900ecaSDon Skidmore #define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540 14329a900ecaSDon Skidmore #define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540 14339a900ecaSDon Skidmore #define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540 14349a900ecaSDon Skidmore #define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540 14359a900ecaSDon Skidmore #define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540 14369a900ecaSDon Skidmore #define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540 14379a900ecaSDon Skidmore #define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540 14389a900ecaSDon Skidmore #define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540 14399a900ecaSDon Skidmore #define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540 14409a900ecaSDon Skidmore #define IXGBE_SDP0_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN) 14419a900ecaSDon Skidmore #define IXGBE_SDP1_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN) 14429a900ecaSDon Skidmore #define IXGBE_SDP2_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN) 14439a900ecaSDon Skidmore 1444dee1ad47SJeff Kirsher #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1445dee1ad47SJeff Kirsher #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1446dee1ad47SJeff Kirsher #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1447dee1ad47SJeff Kirsher #define IXGBE_GPIE_EIAME 0x40000000 1448dee1ad47SJeff Kirsher #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1449dee1ad47SJeff Kirsher #define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1450dee1ad47SJeff Kirsher #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1451dee1ad47SJeff Kirsher #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1452dee1ad47SJeff Kirsher #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1453dee1ad47SJeff Kirsher #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1454dee1ad47SJeff Kirsher 1455dee1ad47SJeff Kirsher /* Packet Buffer Initialization */ 1456dee1ad47SJeff Kirsher #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 1457dee1ad47SJeff Kirsher #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 1458dee1ad47SJeff Kirsher #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 1459dee1ad47SJeff Kirsher #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 1460dee1ad47SJeff Kirsher #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 1461dee1ad47SJeff Kirsher #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 1462dee1ad47SJeff Kirsher #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/ 1463dee1ad47SJeff Kirsher #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/ 1464dee1ad47SJeff Kirsher 1465dee1ad47SJeff Kirsher #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 1466dee1ad47SJeff Kirsher #define IXGBE_MAX_PB 8 1467dee1ad47SJeff Kirsher 1468dee1ad47SJeff Kirsher /* Packet buffer allocation strategies */ 1469dee1ad47SJeff Kirsher enum { 1470dee1ad47SJeff Kirsher PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 1471dee1ad47SJeff Kirsher #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 1472dee1ad47SJeff Kirsher PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 1473dee1ad47SJeff Kirsher #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 1474dee1ad47SJeff Kirsher }; 1475dee1ad47SJeff Kirsher 1476dee1ad47SJeff Kirsher /* Transmit Flow Control status */ 1477dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF 0x00000001 1478dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF0 0x00000100 1479dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF1 0x00000200 1480dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF2 0x00000400 1481dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF3 0x00000800 1482dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF4 0x00001000 1483dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF5 0x00002000 1484dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF6 0x00004000 1485dee1ad47SJeff Kirsher #define IXGBE_TFCS_TXOFF7 0x00008000 1486dee1ad47SJeff Kirsher 1487dee1ad47SJeff Kirsher /* TCP Timer */ 1488dee1ad47SJeff Kirsher #define IXGBE_TCPTIMER_KS 0x00000100 1489dee1ad47SJeff Kirsher #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1490dee1ad47SJeff Kirsher #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1491dee1ad47SJeff Kirsher #define IXGBE_TCPTIMER_LOOP 0x00000800 1492dee1ad47SJeff Kirsher #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1493dee1ad47SJeff Kirsher 1494dee1ad47SJeff Kirsher /* HLREG0 Bit Masks */ 1495dee1ad47SJeff Kirsher #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1496dee1ad47SJeff Kirsher #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1497dee1ad47SJeff Kirsher #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1498dee1ad47SJeff Kirsher #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1499dee1ad47SJeff Kirsher #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1500dee1ad47SJeff Kirsher #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1501dee1ad47SJeff Kirsher #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1502dee1ad47SJeff Kirsher #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1503dee1ad47SJeff Kirsher #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1504dee1ad47SJeff Kirsher #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1505dee1ad47SJeff Kirsher #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1506dee1ad47SJeff Kirsher #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1507dee1ad47SJeff Kirsher #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1508dee1ad47SJeff Kirsher #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1509dee1ad47SJeff Kirsher #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1510dee1ad47SJeff Kirsher 1511dee1ad47SJeff Kirsher /* VMD_CTL bitmasks */ 1512dee1ad47SJeff Kirsher #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1513dee1ad47SJeff Kirsher #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1514dee1ad47SJeff Kirsher 1515dee1ad47SJeff Kirsher /* VT_CTL bitmasks */ 1516dee1ad47SJeff Kirsher #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1517dee1ad47SJeff Kirsher #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1518dee1ad47SJeff Kirsher #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1519dee1ad47SJeff Kirsher #define IXGBE_VT_CTL_POOL_SHIFT 7 1520dee1ad47SJeff Kirsher #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1521dee1ad47SJeff Kirsher 1522dee1ad47SJeff Kirsher /* VMOLR bitmasks */ 152307eea570SDon Skidmore #define IXGBE_VMOLR_UPE 0x00400000 /* unicast promiscuous */ 152407eea570SDon Skidmore #define IXGBE_VMOLR_VPE 0x00800000 /* VLAN promiscuous */ 1525dee1ad47SJeff Kirsher #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1526dee1ad47SJeff Kirsher #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1527dee1ad47SJeff Kirsher #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1528dee1ad47SJeff Kirsher #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1529dee1ad47SJeff Kirsher #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1530dee1ad47SJeff Kirsher 1531dee1ad47SJeff Kirsher /* VFRE bitmask */ 1532dee1ad47SJeff Kirsher #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1533dee1ad47SJeff Kirsher 1534dee1ad47SJeff Kirsher #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1535dee1ad47SJeff Kirsher 1536dee1ad47SJeff Kirsher /* RDHMPN and TDHMPN bitmasks */ 1537dee1ad47SJeff Kirsher #define IXGBE_RDHMPN_RDICADDR 0x007FF800 1538dee1ad47SJeff Kirsher #define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1539dee1ad47SJeff Kirsher #define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1540dee1ad47SJeff Kirsher #define IXGBE_TDHMPN_TDICADDR 0x003FF800 1541dee1ad47SJeff Kirsher #define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1542dee1ad47SJeff Kirsher #define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1543dee1ad47SJeff Kirsher 1544dee1ad47SJeff Kirsher #define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1545dee1ad47SJeff Kirsher #define IXGBE_RDMAM_DWORD_SHIFT 9 1546dee1ad47SJeff Kirsher #define IXGBE_RDMAM_DESC_COMP_FIFO 1 1547dee1ad47SJeff Kirsher #define IXGBE_RDMAM_DFC_CMD_FIFO 2 1548dee1ad47SJeff Kirsher #define IXGBE_RDMAM_TCN_STATUS_RAM 4 1549dee1ad47SJeff Kirsher #define IXGBE_RDMAM_WB_COLL_FIFO 5 1550dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_CNT_RAM 6 1551dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1552dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1553dee1ad47SJeff Kirsher #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1554dee1ad47SJeff Kirsher #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1555dee1ad47SJeff Kirsher #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1556dee1ad47SJeff Kirsher #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1557dee1ad47SJeff Kirsher #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1558dee1ad47SJeff Kirsher #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1559dee1ad47SJeff Kirsher #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1560dee1ad47SJeff Kirsher #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1561dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1562dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1563dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1564dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1565dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1566dee1ad47SJeff Kirsher #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1567dee1ad47SJeff Kirsher 1568dee1ad47SJeff Kirsher #define IXGBE_TXDESCIC_READY 0x80000000 1569dee1ad47SJeff Kirsher 1570dee1ad47SJeff Kirsher /* Receive Checksum Control */ 1571dee1ad47SJeff Kirsher #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1572dee1ad47SJeff Kirsher #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1573dee1ad47SJeff Kirsher 1574dee1ad47SJeff Kirsher /* FCRTL Bit Masks */ 1575dee1ad47SJeff Kirsher #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1576dee1ad47SJeff Kirsher #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1577dee1ad47SJeff Kirsher 1578dee1ad47SJeff Kirsher /* PAP bit masks*/ 1579dee1ad47SJeff Kirsher #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1580dee1ad47SJeff Kirsher 1581dee1ad47SJeff Kirsher /* RMCS Bit Masks */ 1582dee1ad47SJeff Kirsher #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ 1583dee1ad47SJeff Kirsher /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1584dee1ad47SJeff Kirsher #define IXGBE_RMCS_RAC 0x00000004 1585dee1ad47SJeff Kirsher #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 1586dee1ad47SJeff Kirsher #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1587dee1ad47SJeff Kirsher #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1588dee1ad47SJeff Kirsher #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1589dee1ad47SJeff Kirsher 1590dee1ad47SJeff Kirsher /* FCCFG Bit Masks */ 1591dee1ad47SJeff Kirsher #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1592dee1ad47SJeff Kirsher #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1593dee1ad47SJeff Kirsher 1594dee1ad47SJeff Kirsher /* Interrupt register bitmasks */ 1595dee1ad47SJeff Kirsher 1596dee1ad47SJeff Kirsher /* Extended Interrupt Cause Read */ 1597dee1ad47SJeff Kirsher #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1598dee1ad47SJeff Kirsher #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1599dee1ad47SJeff Kirsher #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1600dee1ad47SJeff Kirsher #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1601dee1ad47SJeff Kirsher #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1602dee1ad47SJeff Kirsher #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1603dee1ad47SJeff Kirsher #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1604dee1ad47SJeff Kirsher #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 16054f51bf70SJacob Keller #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 1606681ae1adSJacob E Keller #define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ 16079a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP0_8259X 0x01000000 /* Gen Purpose INT on SDP0 */ 16089a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP1_8259X 0x02000000 /* Gen Purpose INT on SDP1 */ 16099a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP2_8259X 0x04000000 /* Gen Purpose INT on SDP2 */ 16109a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP0_X540 0x02000000 16119a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP1_X540 0x04000000 16129a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP2_X540 0x08000000 16139a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540 16149a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540 16159a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540 16169a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540 16179a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540 16189a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540 16199a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540 16209a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540 16219a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540 16229a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP0(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0) 16239a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP1(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1) 16249a900ecaSDon Skidmore #define IXGBE_EICR_GPI_SDP2(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2) 16259a900ecaSDon Skidmore 1626dee1ad47SJeff Kirsher #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1627dee1ad47SJeff Kirsher #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1628dee1ad47SJeff Kirsher #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1629dee1ad47SJeff Kirsher #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1630dee1ad47SJeff Kirsher #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1631dee1ad47SJeff Kirsher 1632dee1ad47SJeff Kirsher /* Extended Interrupt Cause Set */ 1633dee1ad47SJeff Kirsher #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1634dee1ad47SJeff Kirsher #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1635dee1ad47SJeff Kirsher #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1636dee1ad47SJeff Kirsher #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1637dee1ad47SJeff Kirsher #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1638dee1ad47SJeff Kirsher #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1639dee1ad47SJeff Kirsher #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1640681ae1adSJacob E Keller #define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 16419a900ecaSDon Skidmore #define IXGBE_EICS_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw) 16429a900ecaSDon Skidmore #define IXGBE_EICS_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw) 16439a900ecaSDon Skidmore #define IXGBE_EICS_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw) 1644dee1ad47SJeff Kirsher #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1645dee1ad47SJeff Kirsher #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1646dee1ad47SJeff Kirsher #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1647dee1ad47SJeff Kirsher #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1648dee1ad47SJeff Kirsher #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1649dee1ad47SJeff Kirsher 1650dee1ad47SJeff Kirsher /* Extended Interrupt Mask Set */ 1651dee1ad47SJeff Kirsher #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1652dee1ad47SJeff Kirsher #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1653dee1ad47SJeff Kirsher #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1654dee1ad47SJeff Kirsher #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1655dee1ad47SJeff Kirsher #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1656dee1ad47SJeff Kirsher #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1657dee1ad47SJeff Kirsher #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 16584f51bf70SJacob Keller #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */ 1659681ae1adSJacob E Keller #define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 16609a900ecaSDon Skidmore #define IXGBE_EIMS_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw) 16619a900ecaSDon Skidmore #define IXGBE_EIMS_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw) 16629a900ecaSDon Skidmore #define IXGBE_EIMS_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw) 1663dee1ad47SJeff Kirsher #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1664dee1ad47SJeff Kirsher #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1665dee1ad47SJeff Kirsher #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1666dee1ad47SJeff Kirsher #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1667dee1ad47SJeff Kirsher #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1668dee1ad47SJeff Kirsher 1669dee1ad47SJeff Kirsher /* Extended Interrupt Mask Clear */ 1670dee1ad47SJeff Kirsher #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1671dee1ad47SJeff Kirsher #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1672dee1ad47SJeff Kirsher #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1673dee1ad47SJeff Kirsher #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 1674dee1ad47SJeff Kirsher #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1675dee1ad47SJeff Kirsher #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1676dee1ad47SJeff Kirsher #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1677681ae1adSJacob E Keller #define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 16789a900ecaSDon Skidmore #define IXGBE_EIMC_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw) 16799a900ecaSDon Skidmore #define IXGBE_EIMC_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw) 16809a900ecaSDon Skidmore #define IXGBE_EIMC_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw) 1681dee1ad47SJeff Kirsher #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1682dee1ad47SJeff Kirsher #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1683dee1ad47SJeff Kirsher #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1684dee1ad47SJeff Kirsher #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1685dee1ad47SJeff Kirsher #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1686dee1ad47SJeff Kirsher 1687dee1ad47SJeff Kirsher #define IXGBE_EIMS_ENABLE_MASK ( \ 1688dee1ad47SJeff Kirsher IXGBE_EIMS_RTX_QUEUE | \ 1689dee1ad47SJeff Kirsher IXGBE_EIMS_LSC | \ 1690dee1ad47SJeff Kirsher IXGBE_EIMS_TCP_TIMER | \ 1691dee1ad47SJeff Kirsher IXGBE_EIMS_OTHER) 1692dee1ad47SJeff Kirsher 1693dee1ad47SJeff Kirsher /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 1694dee1ad47SJeff Kirsher #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 1695dee1ad47SJeff Kirsher #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 1696dee1ad47SJeff Kirsher #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 1697dee1ad47SJeff Kirsher #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 1698dee1ad47SJeff Kirsher #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 1699dee1ad47SJeff Kirsher #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 1700dee1ad47SJeff Kirsher #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 1701dee1ad47SJeff Kirsher #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1702dee1ad47SJeff Kirsher #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1703dee1ad47SJeff Kirsher #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1704dee1ad47SJeff Kirsher #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 1705dee1ad47SJeff Kirsher #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 1706dee1ad47SJeff Kirsher #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 1707dee1ad47SJeff Kirsher #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 1708dee1ad47SJeff Kirsher #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 1709dee1ad47SJeff Kirsher #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 1710dee1ad47SJeff Kirsher #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 1711dee1ad47SJeff Kirsher #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */ 1712dee1ad47SJeff Kirsher #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 1713dee1ad47SJeff Kirsher #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 1714dee1ad47SJeff Kirsher #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 1715dee1ad47SJeff Kirsher #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 1716dee1ad47SJeff Kirsher #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 1717dee1ad47SJeff Kirsher 1718dee1ad47SJeff Kirsher #define IXGBE_MAX_FTQF_FILTERS 128 1719dee1ad47SJeff Kirsher #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 1720dee1ad47SJeff Kirsher #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 1721dee1ad47SJeff Kirsher #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 1722dee1ad47SJeff Kirsher #define IXGBE_FTQF_PROTOCOL_SCTP 2 1723dee1ad47SJeff Kirsher #define IXGBE_FTQF_PRIORITY_MASK 0x00000007 1724dee1ad47SJeff Kirsher #define IXGBE_FTQF_PRIORITY_SHIFT 2 1725dee1ad47SJeff Kirsher #define IXGBE_FTQF_POOL_MASK 0x0000003F 1726dee1ad47SJeff Kirsher #define IXGBE_FTQF_POOL_SHIFT 8 1727dee1ad47SJeff Kirsher #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 1728dee1ad47SJeff Kirsher #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 1729dee1ad47SJeff Kirsher #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 1730dee1ad47SJeff Kirsher #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 1731dee1ad47SJeff Kirsher #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 1732dee1ad47SJeff Kirsher #define IXGBE_FTQF_DEST_PORT_MASK 0x17 1733dee1ad47SJeff Kirsher #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 1734dee1ad47SJeff Kirsher #define IXGBE_FTQF_POOL_MASK_EN 0x40000000 1735dee1ad47SJeff Kirsher #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 1736dee1ad47SJeff Kirsher 1737dee1ad47SJeff Kirsher /* Interrupt clear mask */ 1738dee1ad47SJeff Kirsher #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1739dee1ad47SJeff Kirsher 1740dee1ad47SJeff Kirsher /* Interrupt Vector Allocation Registers */ 1741dee1ad47SJeff Kirsher #define IXGBE_IVAR_REG_NUM 25 1742dee1ad47SJeff Kirsher #define IXGBE_IVAR_REG_NUM_82599 64 1743dee1ad47SJeff Kirsher #define IXGBE_IVAR_TXRX_ENTRY 96 1744dee1ad47SJeff Kirsher #define IXGBE_IVAR_RX_ENTRY 64 1745dee1ad47SJeff Kirsher #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 1746dee1ad47SJeff Kirsher #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 1747dee1ad47SJeff Kirsher #define IXGBE_IVAR_TX_ENTRY 32 1748dee1ad47SJeff Kirsher 1749dee1ad47SJeff Kirsher #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 1750dee1ad47SJeff Kirsher #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 1751dee1ad47SJeff Kirsher 1752dee1ad47SJeff Kirsher #define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 1753dee1ad47SJeff Kirsher 1754dee1ad47SJeff Kirsher #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 1755dee1ad47SJeff Kirsher 1756dee1ad47SJeff Kirsher /* ETYPE Queue Filter/Select Bit Masks */ 1757dee1ad47SJeff Kirsher #define IXGBE_MAX_ETQF_FILTERS 8 1758dee1ad47SJeff Kirsher #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 1759dee1ad47SJeff Kirsher #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 17605b7f000fSDon Skidmore #define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */ 1761dee1ad47SJeff Kirsher #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 1762dee1ad47SJeff Kirsher #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 1763b4f47a48SJacob Keller #define IXGBE_ETQF_POOL_ENABLE BIT(26) /* bit 26 */ 176481faddefSAlexander Duyck #define IXGBE_ETQF_POOL_SHIFT 20 1765dee1ad47SJeff Kirsher 1766dee1ad47SJeff Kirsher #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 1767dee1ad47SJeff Kirsher #define IXGBE_ETQS_RX_QUEUE_SHIFT 16 1768dee1ad47SJeff Kirsher #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 1769dee1ad47SJeff Kirsher #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 1770dee1ad47SJeff Kirsher 1771dee1ad47SJeff Kirsher /* 1772dee1ad47SJeff Kirsher * ETQF filter list: one static filter per filter consumer. This is 1773dee1ad47SJeff Kirsher * to avoid filter collisions later. Add new filters 1774dee1ad47SJeff Kirsher * here!! 1775dee1ad47SJeff Kirsher * 1776dee1ad47SJeff Kirsher * Current filters: 1777dee1ad47SJeff Kirsher * EAPOL 802.1x (0x888e): Filter 0 1778dee1ad47SJeff Kirsher * FCoE (0x8906): Filter 2 1779dee1ad47SJeff Kirsher * 1588 (0x88f7): Filter 3 1780dee1ad47SJeff Kirsher * FIP (0x8914): Filter 4 1781f079fa00SEmil Tantilov * LLDP (0x88CC): Filter 5 1782f079fa00SEmil Tantilov * LACP (0x8809): Filter 6 1783f079fa00SEmil Tantilov * FC (0x8808): Filter 7 1784dee1ad47SJeff Kirsher */ 1785dee1ad47SJeff Kirsher #define IXGBE_ETQF_FILTER_EAPOL 0 1786dee1ad47SJeff Kirsher #define IXGBE_ETQF_FILTER_FCOE 2 1787dee1ad47SJeff Kirsher #define IXGBE_ETQF_FILTER_1588 3 1788dee1ad47SJeff Kirsher #define IXGBE_ETQF_FILTER_FIP 4 17895b7f000fSDon Skidmore #define IXGBE_ETQF_FILTER_LLDP 5 17905b7f000fSDon Skidmore #define IXGBE_ETQF_FILTER_LACP 6 1791f079fa00SEmil Tantilov #define IXGBE_ETQF_FILTER_FC 7 17925b7f000fSDon Skidmore 1793dee1ad47SJeff Kirsher /* VLAN Control Bit Masks */ 1794dee1ad47SJeff Kirsher #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1795dee1ad47SJeff Kirsher #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1796dee1ad47SJeff Kirsher #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 1797dee1ad47SJeff Kirsher #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 1798dee1ad47SJeff Kirsher #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 1799dee1ad47SJeff Kirsher 1800dee1ad47SJeff Kirsher /* VLAN pool filtering masks */ 1801dee1ad47SJeff Kirsher #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 1802dee1ad47SJeff Kirsher #define IXGBE_VLVF_ENTRIES 64 1803dee1ad47SJeff Kirsher #define IXGBE_VLVF_VLANID_MASK 0x00000FFF 1804dee1ad47SJeff Kirsher 1805dee1ad47SJeff Kirsher /* Per VF Port VLAN insertion rules */ 1806dee1ad47SJeff Kirsher #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 1807dee1ad47SJeff Kirsher #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 1808dee1ad47SJeff Kirsher 1809dee1ad47SJeff Kirsher #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 1810dee1ad47SJeff Kirsher 1811dee1ad47SJeff Kirsher /* STATUS Bit Masks */ 1812dee1ad47SJeff Kirsher #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 1813dee1ad47SJeff Kirsher #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 181493b067f1SPiotr Skajewski #define IXGBE_STATUS_GIO 0x00080000 /* GIO Primary Enable Status */ 1815dee1ad47SJeff Kirsher 1816dee1ad47SJeff Kirsher #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 1817dee1ad47SJeff Kirsher #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 1818dee1ad47SJeff Kirsher 1819dee1ad47SJeff Kirsher /* ESDP Bit Masks */ 1820dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 1821dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 1822dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 1823dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 1824dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 1825dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 1826dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 1827681ae1adSJacob E Keller #define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ 18288f58332bSDon Skidmore #define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ 1829dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 1830dee1ad47SJeff Kirsher #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 1831681ae1adSJacob E Keller #define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 Native Function */ 18328f58332bSDon Skidmore #define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ 1833dee1ad47SJeff Kirsher 1834dee1ad47SJeff Kirsher /* LEDCTL Bit Masks */ 1835dee1ad47SJeff Kirsher #define IXGBE_LED_IVRT_BASE 0x00000040 1836dee1ad47SJeff Kirsher #define IXGBE_LED_BLINK_BASE 0x00000080 1837dee1ad47SJeff Kirsher #define IXGBE_LED_MODE_MASK_BASE 0x0000000F 1838dee1ad47SJeff Kirsher #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 1839dee1ad47SJeff Kirsher #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i)) 1840dee1ad47SJeff Kirsher #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 1841dee1ad47SJeff Kirsher #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 1842dee1ad47SJeff Kirsher #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 1843a0ad55a3SDon Skidmore #define IXGBE_X557_LED_MANUAL_SET_MASK BIT(8) 1844a0ad55a3SDon Skidmore #define IXGBE_X557_MAX_LED_INDEX 3 1845a0ad55a3SDon Skidmore #define IXGBE_X557_LED_PROVISIONING 0xC430 1846dee1ad47SJeff Kirsher 1847dee1ad47SJeff Kirsher /* LED modes */ 1848dee1ad47SJeff Kirsher #define IXGBE_LED_LINK_UP 0x0 1849dee1ad47SJeff Kirsher #define IXGBE_LED_LINK_10G 0x1 1850dee1ad47SJeff Kirsher #define IXGBE_LED_MAC 0x2 1851dee1ad47SJeff Kirsher #define IXGBE_LED_FILTER 0x3 1852dee1ad47SJeff Kirsher #define IXGBE_LED_LINK_ACTIVE 0x4 1853dee1ad47SJeff Kirsher #define IXGBE_LED_LINK_1G 0x5 1854dee1ad47SJeff Kirsher #define IXGBE_LED_ON 0xE 1855dee1ad47SJeff Kirsher #define IXGBE_LED_OFF 0xF 1856dee1ad47SJeff Kirsher 1857dee1ad47SJeff Kirsher /* AUTOC Bit Masks */ 1858dee1ad47SJeff Kirsher #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 1859dee1ad47SJeff Kirsher #define IXGBE_AUTOC_KX4_SUPP 0x80000000 1860dee1ad47SJeff Kirsher #define IXGBE_AUTOC_KX_SUPP 0x40000000 1861dee1ad47SJeff Kirsher #define IXGBE_AUTOC_PAUSE 0x30000000 1862dee1ad47SJeff Kirsher #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 1863dee1ad47SJeff Kirsher #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 1864dee1ad47SJeff Kirsher #define IXGBE_AUTOC_RF 0x08000000 1865dee1ad47SJeff Kirsher #define IXGBE_AUTOC_PD_TMR 0x06000000 1866dee1ad47SJeff Kirsher #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 1867dee1ad47SJeff Kirsher #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 1868dee1ad47SJeff Kirsher #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 1869dee1ad47SJeff Kirsher #define IXGBE_AUTOC_FECA 0x00040000 1870dee1ad47SJeff Kirsher #define IXGBE_AUTOC_FECR 0x00020000 1871dee1ad47SJeff Kirsher #define IXGBE_AUTOC_KR_SUPP 0x00010000 1872dee1ad47SJeff Kirsher #define IXGBE_AUTOC_AN_RESTART 0x00001000 1873dee1ad47SJeff Kirsher #define IXGBE_AUTOC_FLU 0x00000001 1874dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_SHIFT 13 1875dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 1876dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1877dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 1878dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1879dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1880dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1881dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 1882dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 1883dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 1884dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 1885dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1886dee1ad47SJeff Kirsher #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1887dee1ad47SJeff Kirsher 1888dee1ad47SJeff Kirsher #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 1889dee1ad47SJeff Kirsher #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1890dee1ad47SJeff Kirsher #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 1891dee1ad47SJeff Kirsher #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1892b4f47a48SJacob Keller #define IXGBE_AUTOC_10G_XAUI (0u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1893b4f47a48SJacob Keller #define IXGBE_AUTOC_10G_KX4 (1u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1894b4f47a48SJacob Keller #define IXGBE_AUTOC_10G_CX4 (2u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1895b4f47a48SJacob Keller #define IXGBE_AUTOC_1G_BX (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1896b4f47a48SJacob Keller #define IXGBE_AUTOC_1G_KX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1897b4f47a48SJacob Keller #define IXGBE_AUTOC_1G_SFI (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1898b4f47a48SJacob Keller #define IXGBE_AUTOC_1G_KX_BX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1899dee1ad47SJeff Kirsher 1900dee1ad47SJeff Kirsher #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 1901dee1ad47SJeff Kirsher #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 1902dee1ad47SJeff Kirsher #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 1903b4f47a48SJacob Keller #define IXGBE_AUTOC2_10G_KR (0u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1904b4f47a48SJacob Keller #define IXGBE_AUTOC2_10G_XFI (1u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1905b4f47a48SJacob Keller #define IXGBE_AUTOC2_10G_SFI (2u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 1906f4f1040aSJacob Keller #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 190746d5ceddSEmil Tantilov #define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 1908dee1ad47SJeff Kirsher 1909dee1ad47SJeff Kirsher #define IXGBE_MACC_FLU 0x00000001 1910dee1ad47SJeff Kirsher #define IXGBE_MACC_FSV_10G 0x00030000 1911dee1ad47SJeff Kirsher #define IXGBE_MACC_FS 0x00040000 1912dee1ad47SJeff Kirsher #define IXGBE_MAC_RX2TX_LPBK 0x00000002 1913dee1ad47SJeff Kirsher 1914dbedd44eSJoe Perches /* Veto Bit definition */ 1915c97506abSDon Skidmore #define IXGBE_MMNGC_MNG_VETO 0x00000001 1916c97506abSDon Skidmore 1917dee1ad47SJeff Kirsher /* LINKS Bit Masks */ 1918dee1ad47SJeff Kirsher #define IXGBE_LINKS_KX_AN_COMP 0x80000000 1919dee1ad47SJeff Kirsher #define IXGBE_LINKS_UP 0x40000000 1920dee1ad47SJeff Kirsher #define IXGBE_LINKS_SPEED 0x20000000 1921dee1ad47SJeff Kirsher #define IXGBE_LINKS_MODE 0x18000000 1922dee1ad47SJeff Kirsher #define IXGBE_LINKS_RX_MODE 0x06000000 1923dee1ad47SJeff Kirsher #define IXGBE_LINKS_TX_MODE 0x01800000 1924dee1ad47SJeff Kirsher #define IXGBE_LINKS_XGXS_EN 0x00400000 1925dee1ad47SJeff Kirsher #define IXGBE_LINKS_SGMII_EN 0x02000000 1926dee1ad47SJeff Kirsher #define IXGBE_LINKS_PCS_1G_EN 0x00200000 1927dee1ad47SJeff Kirsher #define IXGBE_LINKS_1G_AN_EN 0x00100000 1928dee1ad47SJeff Kirsher #define IXGBE_LINKS_KX_AN_IDLE 0x00080000 1929dee1ad47SJeff Kirsher #define IXGBE_LINKS_1G_SYNC 0x00040000 1930dee1ad47SJeff Kirsher #define IXGBE_LINKS_10G_ALIGN 0x00020000 1931dee1ad47SJeff Kirsher #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 1932dee1ad47SJeff Kirsher #define IXGBE_LINKS_TL_FAULT 0x00001000 1933dee1ad47SJeff Kirsher #define IXGBE_LINKS_SIGNAL 0x00000F00 1934dee1ad47SJeff Kirsher 19359a75a1acSDon Skidmore #define IXGBE_LINKS_SPEED_NON_STD 0x08000000 1936dee1ad47SJeff Kirsher #define IXGBE_LINKS_SPEED_82599 0x30000000 1937dee1ad47SJeff Kirsher #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 1938dee1ad47SJeff Kirsher #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 1939dee1ad47SJeff Kirsher #define IXGBE_LINKS_SPEED_100_82599 0x10000000 1940b3eb4e18SMark Rustad #define IXGBE_LINKS_SPEED_10_X550EM_A 0 1941dee1ad47SJeff Kirsher #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1942dee1ad47SJeff Kirsher #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1943dee1ad47SJeff Kirsher 1944dee1ad47SJeff Kirsher #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 1945dee1ad47SJeff Kirsher 1946dee1ad47SJeff Kirsher /* PCS1GLSTA Bit Masks */ 1947dee1ad47SJeff Kirsher #define IXGBE_PCS1GLSTA_LINK_OK 1 1948dee1ad47SJeff Kirsher #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 1949dee1ad47SJeff Kirsher #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 1950dee1ad47SJeff Kirsher #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 1951dee1ad47SJeff Kirsher #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 1952dee1ad47SJeff Kirsher #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 1953dee1ad47SJeff Kirsher #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 1954dee1ad47SJeff Kirsher 1955dee1ad47SJeff Kirsher #define IXGBE_PCS1GANA_SYM_PAUSE 0x80 1956dee1ad47SJeff Kirsher #define IXGBE_PCS1GANA_ASM_PAUSE 0x100 1957dee1ad47SJeff Kirsher 1958dee1ad47SJeff Kirsher /* PCS1GLCTL Bit Masks */ 1959dee1ad47SJeff Kirsher #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 1960dee1ad47SJeff Kirsher #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 1961dee1ad47SJeff Kirsher #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 1962dee1ad47SJeff Kirsher #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 1963dee1ad47SJeff Kirsher #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 1964dee1ad47SJeff Kirsher #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 1965dee1ad47SJeff Kirsher 1966dee1ad47SJeff Kirsher /* ANLP1 Bit Masks */ 1967dee1ad47SJeff Kirsher #define IXGBE_ANLP1_PAUSE 0x0C00 1968dee1ad47SJeff Kirsher #define IXGBE_ANLP1_SYM_PAUSE 0x0400 1969dee1ad47SJeff Kirsher #define IXGBE_ANLP1_ASM_PAUSE 0x0800 1970dee1ad47SJeff Kirsher #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 1971dee1ad47SJeff Kirsher 1972dee1ad47SJeff Kirsher /* SW Semaphore Register bitmasks */ 1973dee1ad47SJeff Kirsher #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 1974dee1ad47SJeff Kirsher #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 1975dee1ad47SJeff Kirsher #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 1976dee1ad47SJeff Kirsher #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 1977dee1ad47SJeff Kirsher 1978dee1ad47SJeff Kirsher /* SW_FW_SYNC/GSSR definitions */ 1979dee1ad47SJeff Kirsher #define IXGBE_GSSR_EEP_SM 0x0001 1980dee1ad47SJeff Kirsher #define IXGBE_GSSR_PHY0_SM 0x0002 1981dee1ad47SJeff Kirsher #define IXGBE_GSSR_PHY1_SM 0x0004 1982dee1ad47SJeff Kirsher #define IXGBE_GSSR_MAC_CSR_SM 0x0008 1983dee1ad47SJeff Kirsher #define IXGBE_GSSR_FLASH_SM 0x0010 1984207969b9SMark Rustad #define IXGBE_GSSR_NVM_UPDATE_SM 0x0200 1985dee1ad47SJeff Kirsher #define IXGBE_GSSR_SW_MNG_SM 0x0400 1986207969b9SMark Rustad #define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */ 19876a14ee0cSDon Skidmore #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */ 19886a14ee0cSDon Skidmore #define IXGBE_GSSR_I2C_MASK 0x1800 1989449e21a9SMark Rustad #define IXGBE_GSSR_NVM_PHY_MASK 0xF 1990dee1ad47SJeff Kirsher 1991dee1ad47SJeff Kirsher /* FW Status register bitmask */ 1992dee1ad47SJeff Kirsher #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 1993dee1ad47SJeff Kirsher 1994dee1ad47SJeff Kirsher /* EEC Register */ 1995dee1ad47SJeff Kirsher #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 1996dee1ad47SJeff Kirsher #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 1997dee1ad47SJeff Kirsher #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 1998dee1ad47SJeff Kirsher #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 1999dee1ad47SJeff Kirsher #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 2000dee1ad47SJeff Kirsher #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 2001dee1ad47SJeff Kirsher #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 2002dee1ad47SJeff Kirsher #define IXGBE_EEC_FWE_SHIFT 4 2003dee1ad47SJeff Kirsher #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 2004dee1ad47SJeff Kirsher #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 2005dee1ad47SJeff Kirsher #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 2006dee1ad47SJeff Kirsher #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 2007dee1ad47SJeff Kirsher #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 2008dee1ad47SJeff Kirsher #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 2009dee1ad47SJeff Kirsher #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 2010dee1ad47SJeff Kirsher /* EEPROM Addressing bits based on type (0-small, 1-large) */ 2011dee1ad47SJeff Kirsher #define IXGBE_EEC_ADDR_SIZE 0x00000400 2012dee1ad47SJeff Kirsher #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 2013dee1ad47SJeff Kirsher #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ 2014dee1ad47SJeff Kirsher 2015dee1ad47SJeff Kirsher #define IXGBE_EEC_SIZE_SHIFT 11 2016dee1ad47SJeff Kirsher #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 2017dee1ad47SJeff Kirsher #define IXGBE_EEPROM_OPCODE_BITS 8 2018dee1ad47SJeff Kirsher 2019dee1ad47SJeff Kirsher /* Part Number String Length */ 2020dee1ad47SJeff Kirsher #define IXGBE_PBANUM_LENGTH 11 2021dee1ad47SJeff Kirsher 2022dee1ad47SJeff Kirsher /* Checksum and EEPROM pointers */ 2023dee1ad47SJeff Kirsher #define IXGBE_PBANUM_PTR_GUARD 0xFAFA 2024dee1ad47SJeff Kirsher #define IXGBE_EEPROM_CHECKSUM 0x3F 2025dee1ad47SJeff Kirsher #define IXGBE_EEPROM_SUM 0xBABA 2026c898fe28SMark Rustad #define IXGBE_EEPROM_CTRL_4 0x45 2027c898fe28SMark Rustad #define IXGBE_EE_CTRL_4_INST_ID 0x10 2028c898fe28SMark Rustad #define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4 2029dee1ad47SJeff Kirsher #define IXGBE_PCIE_ANALOG_PTR 0x03 2030dee1ad47SJeff Kirsher #define IXGBE_ATLAS0_CONFIG_PTR 0x04 2031dee1ad47SJeff Kirsher #define IXGBE_PHY_PTR 0x04 2032dee1ad47SJeff Kirsher #define IXGBE_ATLAS1_CONFIG_PTR 0x05 2033dee1ad47SJeff Kirsher #define IXGBE_OPTION_ROM_PTR 0x05 2034dee1ad47SJeff Kirsher #define IXGBE_PCIE_GENERAL_PTR 0x06 2035dee1ad47SJeff Kirsher #define IXGBE_PCIE_CONFIG0_PTR 0x07 2036dee1ad47SJeff Kirsher #define IXGBE_PCIE_CONFIG1_PTR 0x08 2037dee1ad47SJeff Kirsher #define IXGBE_CORE0_PTR 0x09 2038dee1ad47SJeff Kirsher #define IXGBE_CORE1_PTR 0x0A 2039dee1ad47SJeff Kirsher #define IXGBE_MAC0_PTR 0x0B 2040dee1ad47SJeff Kirsher #define IXGBE_MAC1_PTR 0x0C 2041dee1ad47SJeff Kirsher #define IXGBE_CSR0_CONFIG_PTR 0x0D 2042dee1ad47SJeff Kirsher #define IXGBE_CSR1_CONFIG_PTR 0x0E 20436a14ee0cSDon Skidmore #define IXGBE_PCIE_ANALOG_PTR_X550 0x02 20446a14ee0cSDon Skidmore #define IXGBE_SHADOW_RAM_SIZE_X550 0x4000 20456a14ee0cSDon Skidmore #define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24 20466a14ee0cSDon Skidmore #define IXGBE_PCIE_CONFIG_SIZE 0x08 20476a14ee0cSDon Skidmore #define IXGBE_EEPROM_LAST_WORD 0x41 2048dee1ad47SJeff Kirsher #define IXGBE_FW_PTR 0x0F 2049dee1ad47SJeff Kirsher #define IXGBE_PBANUM0_PTR 0x15 2050dee1ad47SJeff Kirsher #define IXGBE_PBANUM1_PTR 0x16 2051dee1ad47SJeff Kirsher #define IXGBE_FREE_SPACE_PTR 0X3E 2052e1ea9158SDon Skidmore 2053e1ea9158SDon Skidmore /* External Thermal Sensor Config */ 2054e1ea9158SDon Skidmore #define IXGBE_ETS_CFG 0x26 2055e1ea9158SDon Skidmore #define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0 2056e1ea9158SDon Skidmore #define IXGBE_ETS_LTHRES_DELTA_SHIFT 6 2057e1ea9158SDon Skidmore #define IXGBE_ETS_TYPE_MASK 0x0038 2058e1ea9158SDon Skidmore #define IXGBE_ETS_TYPE_SHIFT 3 2059e1ea9158SDon Skidmore #define IXGBE_ETS_TYPE_EMC 0x000 2060e1ea9158SDon Skidmore #define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000 2061e1ea9158SDon Skidmore #define IXGBE_ETS_NUM_SENSORS_MASK 0x0007 2062e1ea9158SDon Skidmore #define IXGBE_ETS_DATA_LOC_MASK 0x3C00 2063e1ea9158SDon Skidmore #define IXGBE_ETS_DATA_LOC_SHIFT 10 2064e1ea9158SDon Skidmore #define IXGBE_ETS_DATA_INDEX_MASK 0x0300 2065e1ea9158SDon Skidmore #define IXGBE_ETS_DATA_INDEX_SHIFT 8 2066e1ea9158SDon Skidmore #define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF 2067e1ea9158SDon Skidmore 2068dee1ad47SJeff Kirsher #define IXGBE_SAN_MAC_ADDR_PTR 0x28 2069dee1ad47SJeff Kirsher #define IXGBE_DEVICE_CAPS 0x2C 2070dee1ad47SJeff Kirsher #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 2071dee1ad47SJeff Kirsher #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 207271161302SEmil Tantilov #define IXGBE_MAX_MSIX_VECTORS_82599 0x40 2073dee1ad47SJeff Kirsher #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 207471161302SEmil Tantilov #define IXGBE_MAX_MSIX_VECTORS_82598 0x13 2075dee1ad47SJeff Kirsher 2076dee1ad47SJeff Kirsher /* MSI-X capability fields masks */ 2077dee1ad47SJeff Kirsher #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 2078dee1ad47SJeff Kirsher 2079dee1ad47SJeff Kirsher /* Legacy EEPROM word offsets */ 2080dee1ad47SJeff Kirsher #define IXGBE_ISCSI_BOOT_CAPS 0x0033 2081dee1ad47SJeff Kirsher #define IXGBE_ISCSI_SETUP_PORT_0 0x0030 2082dee1ad47SJeff Kirsher #define IXGBE_ISCSI_SETUP_PORT_1 0x0034 2083dee1ad47SJeff Kirsher 2084dee1ad47SJeff Kirsher /* EEPROM Commands - SPI */ 2085dee1ad47SJeff Kirsher #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 2086dee1ad47SJeff Kirsher #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 2087dee1ad47SJeff Kirsher #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2088dee1ad47SJeff Kirsher #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2089dee1ad47SJeff Kirsher #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 2090dee1ad47SJeff Kirsher #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 2091dee1ad47SJeff Kirsher /* EEPROM reset Write Enable latch */ 2092dee1ad47SJeff Kirsher #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 2093dee1ad47SJeff Kirsher #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 2094dee1ad47SJeff Kirsher #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 2095dee1ad47SJeff Kirsher #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2096dee1ad47SJeff Kirsher #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2097dee1ad47SJeff Kirsher #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2098dee1ad47SJeff Kirsher 2099dee1ad47SJeff Kirsher /* EEPROM Read Register */ 2100dee1ad47SJeff Kirsher #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 2101dee1ad47SJeff Kirsher #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 2102dee1ad47SJeff Kirsher #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 2103dee1ad47SJeff Kirsher #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 2104dee1ad47SJeff Kirsher #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 2105dee1ad47SJeff Kirsher #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */ 2106dee1ad47SJeff Kirsher 21076ac74394SDon Skidmore #define NVM_INIT_CTRL_3 0x38 21086ac74394SDon Skidmore #define NVM_INIT_CTRL_3_LPLU 0x8 21096ac74394SDon Skidmore #define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40 21106ac74394SDon Skidmore #define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100 21116ac74394SDon Skidmore 2112dee1ad47SJeff Kirsher #define IXGBE_EEPROM_PAGE_SIZE_MAX 128 2113dee1ad47SJeff Kirsher #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */ 2114dee1ad47SJeff Kirsher #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */ 2115dee1ad47SJeff Kirsher 2116f68bfdb1SJacob Keller #define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */ 2117f68bfdb1SJacob Keller #define IXGBE_EEPROM_CCD_BIT 2 /* EEPROM Core Clock Disable bit */ 2118f68bfdb1SJacob Keller 2119dee1ad47SJeff Kirsher #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 2120dee1ad47SJeff Kirsher #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 2121dee1ad47SJeff Kirsher #endif 2122dee1ad47SJeff Kirsher 2123dee1ad47SJeff Kirsher #ifndef IXGBE_EERD_EEWR_ATTEMPTS 2124dee1ad47SJeff Kirsher /* Number of 5 microseconds we wait for EERD read and 2125dee1ad47SJeff Kirsher * EERW write to complete */ 2126dee1ad47SJeff Kirsher #define IXGBE_EERD_EEWR_ATTEMPTS 100000 2127dee1ad47SJeff Kirsher #endif 2128dee1ad47SJeff Kirsher 2129dee1ad47SJeff Kirsher #ifndef IXGBE_FLUDONE_ATTEMPTS 2130dee1ad47SJeff Kirsher /* # attempts we wait for flush update to complete */ 2131dee1ad47SJeff Kirsher #define IXGBE_FLUDONE_ATTEMPTS 20000 2132dee1ad47SJeff Kirsher #endif 2133dee1ad47SJeff Kirsher 2134dee1ad47SJeff Kirsher #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 2135dee1ad47SJeff Kirsher #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 2136dee1ad47SJeff Kirsher #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 2137dee1ad47SJeff Kirsher #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 2138dee1ad47SJeff Kirsher 2139dee1ad47SJeff Kirsher #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 2140dee1ad47SJeff Kirsher #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 2141dee1ad47SJeff Kirsher #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 2142dee1ad47SJeff Kirsher #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 21434319a797SDon Skidmore #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR BIT(7) 2144dee1ad47SJeff Kirsher #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 2145dee1ad47SJeff Kirsher #define IXGBE_FW_LESM_STATE_1 0x1 2146dee1ad47SJeff Kirsher #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 2147dee1ad47SJeff Kirsher #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 2148dee1ad47SJeff Kirsher #define IXGBE_FW_PATCH_VERSION_4 0x7 2149dee1ad47SJeff Kirsher #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 2150dee1ad47SJeff Kirsher #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 2151dee1ad47SJeff Kirsher #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 2152dee1ad47SJeff Kirsher #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 2153dee1ad47SJeff Kirsher #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 2154dee1ad47SJeff Kirsher #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 2155dee1ad47SJeff Kirsher #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */ 2156dee1ad47SJeff Kirsher #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */ 2157dee1ad47SJeff Kirsher #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */ 2158dee1ad47SJeff Kirsher #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */ 2159dee1ad47SJeff Kirsher #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */ 2160dee1ad47SJeff Kirsher #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */ 2161dee1ad47SJeff Kirsher #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */ 2162dee1ad47SJeff Kirsher 2163c23f5b6bSEmil Tantilov #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 2164c23f5b6bSEmil Tantilov #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 2165c23f5b6bSEmil Tantilov #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 2166c23f5b6bSEmil Tantilov 2167dee1ad47SJeff Kirsher /* PCI Bus Info */ 2168dee1ad47SJeff Kirsher #define IXGBE_PCI_DEVICE_STATUS 0xAA 2169dee1ad47SJeff Kirsher #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 2170dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_STATUS 0xB2 2171dee1ad47SJeff Kirsher #define IXGBE_PCI_DEVICE_CONTROL2 0xC8 2172dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_WIDTH 0x3F0 2173dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_WIDTH_1 0x10 2174dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_WIDTH_2 0x20 2175dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_WIDTH_4 0x40 2176dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_WIDTH_8 0x80 2177dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_SPEED 0xF 2178dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_SPEED_2500 0x1 2179dee1ad47SJeff Kirsher #define IXGBE_PCI_LINK_SPEED_5000 0x2 2180e8710a5fSJacob Keller #define IXGBE_PCI_LINK_SPEED_8000 0x3 2181dee1ad47SJeff Kirsher #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 2182dee1ad47SJeff Kirsher #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 2183dee1ad47SJeff Kirsher #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 2184dee1ad47SJeff Kirsher 21851f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf 21861f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0 21871f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_50_100us 0x1 21881f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_1_2ms 0x2 21891f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_16_32ms 0x5 21901f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_65_130ms 0x6 21911f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_260_520ms 0x9 21921f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_1_2s 0xa 21931f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_4_8s 0xd 21941f86c983SDon Skidmore #define IXGBE_PCIDEVCTRL2_17_34s 0xe 21951f86c983SDon Skidmore 219693b067f1SPiotr Skajewski /* Number of 100 microseconds we wait for PCI Express primary disable */ 219793b067f1SPiotr Skajewski #define IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT 800 2198dee1ad47SJeff Kirsher 2199dee1ad47SJeff Kirsher /* RAH */ 2200dee1ad47SJeff Kirsher #define IXGBE_RAH_VIND_MASK 0x003C0000 2201dee1ad47SJeff Kirsher #define IXGBE_RAH_VIND_SHIFT 18 2202dee1ad47SJeff Kirsher #define IXGBE_RAH_AV 0x80000000 2203dee1ad47SJeff Kirsher #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 2204dee1ad47SJeff Kirsher 2205dee1ad47SJeff Kirsher /* Header split receive */ 2206dee1ad47SJeff Kirsher #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 2207dee1ad47SJeff Kirsher #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 2208dee1ad47SJeff Kirsher #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 22096dcc28b9SJacob Keller #define IXGBE_RFCTL_RSC_DIS 0x00000020 2210dee1ad47SJeff Kirsher #define IXGBE_RFCTL_NFSW_DIS 0x00000040 2211dee1ad47SJeff Kirsher #define IXGBE_RFCTL_NFSR_DIS 0x00000080 2212dee1ad47SJeff Kirsher #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 2213dee1ad47SJeff Kirsher #define IXGBE_RFCTL_NFS_VER_SHIFT 8 2214dee1ad47SJeff Kirsher #define IXGBE_RFCTL_NFS_VER_2 0 2215dee1ad47SJeff Kirsher #define IXGBE_RFCTL_NFS_VER_3 1 2216dee1ad47SJeff Kirsher #define IXGBE_RFCTL_NFS_VER_4 2 2217dee1ad47SJeff Kirsher #define IXGBE_RFCTL_IPV6_DIS 0x00000400 2218dee1ad47SJeff Kirsher #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 2219dee1ad47SJeff Kirsher #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 2220dee1ad47SJeff Kirsher #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 2221dee1ad47SJeff Kirsher #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 2222dee1ad47SJeff Kirsher 2223dee1ad47SJeff Kirsher /* Transmit Config masks */ 2224dee1ad47SJeff Kirsher #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 2225dee1ad47SJeff Kirsher #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 2226dee1ad47SJeff Kirsher #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 2227dee1ad47SJeff Kirsher /* Enable short packet padding to 64 bytes */ 2228dee1ad47SJeff Kirsher #define IXGBE_TX_PAD_ENABLE 0x00000400 2229dee1ad47SJeff Kirsher #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 2230dee1ad47SJeff Kirsher /* This allows for 16K packets + 4k for vlan */ 2231dee1ad47SJeff Kirsher #define IXGBE_MAX_FRAME_SZ 0x40040000 2232dee1ad47SJeff Kirsher 2233dee1ad47SJeff Kirsher #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 2234dee1ad47SJeff Kirsher #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 2235dee1ad47SJeff Kirsher 2236dee1ad47SJeff Kirsher /* Receive Config masks */ 2237dee1ad47SJeff Kirsher #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 2238dee1ad47SJeff Kirsher #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 2239dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 2240ff9d1a5aSEmil Tantilov #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 2241dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ 2242dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_RLPML_EN 0x00008000 2243dee1ad47SJeff Kirsher #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 2244dee1ad47SJeff Kirsher 2245681ae1adSJacob E Keller #define IXGBE_TSAUXC_EN_CLK 0x00000004 2246681ae1adSJacob E Keller #define IXGBE_TSAUXC_SYNCLK 0x00000008 2247681ae1adSJacob E Keller #define IXGBE_TSAUXC_SDP0_INT 0x00000040 2248cd458320SJacob Keller #define IXGBE_TSAUXC_EN_TT0 0x00000001 2249cd458320SJacob Keller #define IXGBE_TSAUXC_EN_TT1 0x00000002 2250cd458320SJacob Keller #define IXGBE_TSAUXC_ST0 0x00000010 2251a9763f3cSMark Rustad #define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000 2252681ae1adSJacob E Keller 2253cd458320SJacob Keller #define IXGBE_TSSDP_TS_SDP0_SEL_MASK 0x000000C0 2254cd458320SJacob Keller #define IXGBE_TSSDP_TS_SDP0_CLK0 0x00000080 2255cd458320SJacob Keller #define IXGBE_TSSDP_TS_SDP0_EN 0x00000100 2256cd458320SJacob Keller 22573a6a4edaSJacob Keller #define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 22583a6a4edaSJacob Keller #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ 22593a6a4edaSJacob Keller 22603a6a4edaSJacob Keller #define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 22613a6a4edaSJacob Keller #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 22623a6a4edaSJacob Keller #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 22633a6a4edaSJacob Keller #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 22643a6a4edaSJacob Keller #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 2265a9763f3cSMark Rustad #define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08 22663a6a4edaSJacob Keller #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 22673a6a4edaSJacob Keller #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ 2268a9763f3cSMark Rustad #define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000 /* Rx Timestamp in Packet */ 2269a9763f3cSMark Rustad 2270a9763f3cSMark Rustad #define IXGBE_TSIM_TXTS 0x00000002 22713a6a4edaSJacob Keller 22723a6a4edaSJacob Keller #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF 22733a6a4edaSJacob Keller #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 22743a6a4edaSJacob Keller #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 22753a6a4edaSJacob Keller #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 22763a6a4edaSJacob Keller #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 22773a6a4edaSJacob Keller #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 22783a6a4edaSJacob Keller 22793a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 22803a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 22813a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 22823a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 22833a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 22843a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 22853a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 22863a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 22873a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 22883a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00 22893a6a4edaSJacob Keller #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 22903a6a4edaSJacob Keller 2291dee1ad47SJeff Kirsher #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 2292dee1ad47SJeff Kirsher #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 2293dee1ad47SJeff Kirsher #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 2294dee1ad47SJeff Kirsher #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 2295dee1ad47SJeff Kirsher #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 2296dee1ad47SJeff Kirsher #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 2297dee1ad47SJeff Kirsher /* Receive Priority Flow Control Enable */ 2298dee1ad47SJeff Kirsher #define IXGBE_FCTRL_RPFCE 0x00004000 2299dee1ad47SJeff Kirsher #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 2300dee1ad47SJeff Kirsher #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 2301dee1ad47SJeff Kirsher #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 2302dee1ad47SJeff Kirsher #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 2303dee1ad47SJeff Kirsher #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 2304041441d0SAlexander Duyck #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Receive FC Mask */ 2305dee1ad47SJeff Kirsher 2306dee1ad47SJeff Kirsher #define IXGBE_MFLCN_RPFCE_SHIFT 4 2307dee1ad47SJeff Kirsher 2308dee1ad47SJeff Kirsher /* Multiple Receive Queue Control */ 2309dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 2310dee1ad47SJeff Kirsher #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 2311dee1ad47SJeff Kirsher #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 2312dee1ad47SJeff Kirsher #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 2313dee1ad47SJeff Kirsher #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 2314dee1ad47SJeff Kirsher #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 2315dee1ad47SJeff Kirsher #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 2316dee1ad47SJeff Kirsher #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 2317dee1ad47SJeff Kirsher #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 2318dee1ad47SJeff Kirsher #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 2319dee1ad47SJeff Kirsher #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 2320dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 2321dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2322dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 2323dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 2324dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2325dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 2326dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2327dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2328dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2329dee1ad47SJeff Kirsher #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 23300f9b232bSDon Skidmore #define IXGBE_MRQC_MULTIPLE_RSS 0x00002000 2331dee1ad47SJeff Kirsher #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 2332dee1ad47SJeff Kirsher 2333cb6d0f5eSJacob Keller #define IXGBE_FWSM_TS_ENABLED 0x1 2334cb6d0f5eSJacob Keller 2335dee1ad47SJeff Kirsher /* Queue Drop Enable */ 2336dee1ad47SJeff Kirsher #define IXGBE_QDE_ENABLE 0x00000001 23379a75a1acSDon Skidmore #define IXGBE_QDE_HIDE_VLAN 0x00000002 2338dee1ad47SJeff Kirsher #define IXGBE_QDE_IDX_MASK 0x00007F00 2339dee1ad47SJeff Kirsher #define IXGBE_QDE_IDX_SHIFT 8 234087397379SAlexander Duyck #define IXGBE_QDE_WRITE 0x00010000 2341dee1ad47SJeff Kirsher 2342dee1ad47SJeff Kirsher #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 2343dee1ad47SJeff Kirsher #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 2344dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 2345dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 2346dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 2347dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 2348dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 2349dee1ad47SJeff Kirsher #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 2350dee1ad47SJeff Kirsher #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 2351dee1ad47SJeff Kirsher 2352dee1ad47SJeff Kirsher /* Multiple Transmit Queue Command Register */ 2353dee1ad47SJeff Kirsher #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 2354dee1ad47SJeff Kirsher #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 2355dee1ad47SJeff Kirsher #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 2356dee1ad47SJeff Kirsher #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 2357dee1ad47SJeff Kirsher #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 2358dee1ad47SJeff Kirsher #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 2359dee1ad47SJeff Kirsher #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */ 2360dee1ad47SJeff Kirsher 2361dee1ad47SJeff Kirsher /* Receive Descriptor bit definitions */ 2362dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 2363dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 2364dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 2365dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 2366dee1ad47SJeff Kirsher #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 2367dee1ad47SJeff Kirsher #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 2368dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 2369dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 2370dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 2371dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 2372dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 23733f207800SDon Skidmore #define IXGBE_RXD_STAT_OUTERIPCS 0x100 /* Cloud IP xsum calculated */ 2374dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 2375dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 2376dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 2377dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 2378a9763f3cSMark Rustad #define IXGBE_RXD_STAT_TSIP 0x08000 /* Time Stamp in packet buffer */ 2379dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 2380dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 2381dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 2382dee1ad47SJeff Kirsher #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 2383dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 2384dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 2385dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 2386dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 2387dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 2388dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 2389dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 2390dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 2391dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 23923f207800SDon Skidmore #define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000 /* CRC IP Header error */ 2393dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ 2394dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 2395dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 2396dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 2397dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 2398dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 2399dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 2400dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 2401dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 2402dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 2403beca8154SShannon Nelson #define IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL 0x08000000 /* overlap ERR_PE */ 2404beca8154SShannon Nelson #define IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH 0x10000000 /* overlap ERR_OSE */ 2405beca8154SShannon Nelson #define IXGBE_RXDADV_ERR_IPSEC_AUTH_FAILED 0x18000000 2406dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 2407dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 2408dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 2409dee1ad47SJeff Kirsher #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 2410dee1ad47SJeff Kirsher #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 2411dee1ad47SJeff Kirsher #define IXGBE_RXD_PRI_SHIFT 13 2412dee1ad47SJeff Kirsher #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 2413dee1ad47SJeff Kirsher #define IXGBE_RXD_CFI_SHIFT 12 2414dee1ad47SJeff Kirsher 2415dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 2416dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 2417dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 2418dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 2419dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 2420dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 2421dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 2422dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 2423dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 2424dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 2425dee1ad47SJeff Kirsher #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 24263a6a4edaSJacob Keller #define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE 1588 Time Stamp */ 2427beca8154SShannon Nelson #define IXGBE_RXDADV_STAT_SECP 0x00020000 /* IPsec/MACsec pkt found */ 2428dee1ad47SJeff Kirsher 2429dee1ad47SJeff Kirsher /* PSRTYPE bit definitions */ 2430dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_TCPHDR 0x00000010 2431dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_UDPHDR 0x00000020 2432dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 2433dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 2434dee1ad47SJeff Kirsher #define IXGBE_PSRTYPE_L2HDR 0x00001000 2435dee1ad47SJeff Kirsher 2436dee1ad47SJeff Kirsher /* SRRCTL bit definitions */ 2437dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 2438dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_RDMTS_SHIFT 22 2439dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 2440dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DROP_EN 0x10000000 2441dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 2442dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 2443dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 2444dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 2445dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 2446dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 2447dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 2448dee1ad47SJeff Kirsher #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 2449dee1ad47SJeff Kirsher 2450dee1ad47SJeff Kirsher #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 2451dee1ad47SJeff Kirsher #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 2452dee1ad47SJeff Kirsher 2453dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 2454dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 2455dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 2456dee1ad47SJeff Kirsher #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 2457dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 2458dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSCCNT_SHIFT 17 2459dee1ad47SJeff Kirsher #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 2460dee1ad47SJeff Kirsher #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 2461dee1ad47SJeff Kirsher #define IXGBE_RXDADV_SPH 0x8000 2462dee1ad47SJeff Kirsher 2463dee1ad47SJeff Kirsher /* RSS Hash results */ 2464dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 2465dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 2466dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 2467dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 2468dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 2469dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 2470dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 2471dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 2472dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 2473dee1ad47SJeff Kirsher #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 2474dee1ad47SJeff Kirsher 2475dee1ad47SJeff Kirsher /* RSS Packet Types as indicated in the receive descriptor. */ 2476dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 2477dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 2478dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 2479dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 2480dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 2481dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 2482dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 2483dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 2484dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 24853f207800SDon Skidmore #define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */ 24863f207800SDon Skidmore #define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */ 2487dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 2488dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 2489dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 2490dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 2491dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 2492dee1ad47SJeff Kirsher #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 2493dee1ad47SJeff Kirsher 2494dee1ad47SJeff Kirsher /* Masks to determine if packets should be dropped due to frame errors */ 2495dee1ad47SJeff Kirsher #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 2496dee1ad47SJeff Kirsher IXGBE_RXD_ERR_CE | \ 2497dee1ad47SJeff Kirsher IXGBE_RXD_ERR_LE | \ 2498dee1ad47SJeff Kirsher IXGBE_RXD_ERR_PE | \ 2499dee1ad47SJeff Kirsher IXGBE_RXD_ERR_OSE | \ 2500dee1ad47SJeff Kirsher IXGBE_RXD_ERR_USE) 2501dee1ad47SJeff Kirsher 2502dee1ad47SJeff Kirsher #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 2503dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_CE | \ 2504dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_LE | \ 2505dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_PE | \ 2506dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_OSE | \ 2507beca8154SShannon Nelson IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL | \ 2508beca8154SShannon Nelson IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH | \ 2509dee1ad47SJeff Kirsher IXGBE_RXDADV_ERR_USE) 2510dee1ad47SJeff Kirsher 2511dee1ad47SJeff Kirsher /* Multicast bit mask */ 2512dee1ad47SJeff Kirsher #define IXGBE_MCSTCTRL_MFE 0x4 2513dee1ad47SJeff Kirsher 2514dee1ad47SJeff Kirsher /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2515dee1ad47SJeff Kirsher #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 2516dee1ad47SJeff Kirsher #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 2517dee1ad47SJeff Kirsher #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 2518dee1ad47SJeff Kirsher 2519dee1ad47SJeff Kirsher /* Vlan-specific macros */ 2520dee1ad47SJeff Kirsher #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 2521dee1ad47SJeff Kirsher #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 2522dee1ad47SJeff Kirsher #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 2523dee1ad47SJeff Kirsher #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 2524dee1ad47SJeff Kirsher 2525dee1ad47SJeff Kirsher /* SR-IOV specific macros */ 2526dee1ad47SJeff Kirsher #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 2527795be954SAlexander Duyck #define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) 2528795be954SAlexander Duyck #define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600)) 2529795be954SAlexander Duyck #define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) 2530dbf231afSAlexander Duyck /* Translated register #defines */ 253107923c17SEmil Tantilov #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) 253207923c17SEmil Tantilov #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) 2533939b701aSSebastian Basierski #define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P))) 2534dbf231afSAlexander Duyck #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) 2535dbf231afSAlexander Duyck #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) 253637530030SMaximilian Heyne #define IXGBE_PVFGPRC(x) (0x0101C + (0x40 * (x))) 253737530030SMaximilian Heyne #define IXGBE_PVFGPTC(x) (0x08300 + (0x04 * (x))) 253837530030SMaximilian Heyne #define IXGBE_PVFGORC_LSB(x) (0x01020 + (0x40 * (x))) 253937530030SMaximilian Heyne #define IXGBE_PVFGORC_MSB(x) (0x0D020 + (0x40 * (x))) 254037530030SMaximilian Heyne #define IXGBE_PVFGOTC_LSB(x) (0x08400 + (0x08 * (x))) 254137530030SMaximilian Heyne #define IXGBE_PVFGOTC_MSB(x) (0x08404 + (0x08 * (x))) 254237530030SMaximilian Heyne #define IXGBE_PVFMPRC(x) (0x0D01C + (0x40 * (x))) 2543dbf231afSAlexander Duyck 2544dbf231afSAlexander Duyck #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \ 2545dbf231afSAlexander Duyck (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index))) 2546dbf231afSAlexander Duyck #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \ 2547dbf231afSAlexander Duyck (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index))) 2548dee1ad47SJeff Kirsher 254907923c17SEmil Tantilov #define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \ 255007923c17SEmil Tantilov (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index))) 255107923c17SEmil Tantilov #define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \ 255207923c17SEmil Tantilov (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index))) 255307923c17SEmil Tantilov 2554dee1ad47SJeff Kirsher enum ixgbe_fdir_pballoc_type { 2555dee1ad47SJeff Kirsher IXGBE_FDIR_PBALLOC_NONE = 0, 2556dee1ad47SJeff Kirsher IXGBE_FDIR_PBALLOC_64K = 1, 2557dee1ad47SJeff Kirsher IXGBE_FDIR_PBALLOC_128K = 2, 2558dee1ad47SJeff Kirsher IXGBE_FDIR_PBALLOC_256K = 3, 2559dee1ad47SJeff Kirsher }; 2560dee1ad47SJeff Kirsher #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16 2561dee1ad47SJeff Kirsher 2562dee1ad47SJeff Kirsher /* Flow Director register values */ 2563dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 2564dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 2565dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 2566dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 2567dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 2568dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 2569dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 2570dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 2571dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_FLEX_SHIFT 16 2572207969b9SMark Rustad #define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000 2573207969b9SMark Rustad #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21 2574207969b9SMark Rustad #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */ 2575207969b9SMark Rustad #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */ 2576dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 2577dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 2578dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 2579dee1ad47SJeff Kirsher #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 2580dee1ad47SJeff Kirsher 2581dee1ad47SJeff Kirsher #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 2582dee1ad47SJeff Kirsher #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 2583dee1ad47SJeff Kirsher #define IXGBE_FDIRIP6M_DIPM_SHIFT 16 2584dee1ad47SJeff Kirsher #define IXGBE_FDIRM_VLANID 0x00000001 2585dee1ad47SJeff Kirsher #define IXGBE_FDIRM_VLANP 0x00000002 2586dee1ad47SJeff Kirsher #define IXGBE_FDIRM_POOL 0x00000004 2587dee1ad47SJeff Kirsher #define IXGBE_FDIRM_L4P 0x00000008 2588dee1ad47SJeff Kirsher #define IXGBE_FDIRM_FLEX 0x00000010 2589dee1ad47SJeff Kirsher #define IXGBE_FDIRM_DIPv6 0x00000020 2590dee1ad47SJeff Kirsher 2591dee1ad47SJeff Kirsher #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 2592dee1ad47SJeff Kirsher #define IXGBE_FDIRFREE_FREE_SHIFT 0 2593dee1ad47SJeff Kirsher #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 2594dee1ad47SJeff Kirsher #define IXGBE_FDIRFREE_COLL_SHIFT 16 2595dee1ad47SJeff Kirsher #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 2596dee1ad47SJeff Kirsher #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 2597dee1ad47SJeff Kirsher #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 2598dee1ad47SJeff Kirsher #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 2599dee1ad47SJeff Kirsher #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 2600dee1ad47SJeff Kirsher #define IXGBE_FDIRUSTAT_ADD_SHIFT 0 2601dee1ad47SJeff Kirsher #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 2602dee1ad47SJeff Kirsher #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 2603dee1ad47SJeff Kirsher #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 2604dee1ad47SJeff Kirsher #define IXGBE_FDIRFSTAT_FADD_SHIFT 0 2605dee1ad47SJeff Kirsher #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 2606dee1ad47SJeff Kirsher #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 2607dee1ad47SJeff Kirsher #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 2608dee1ad47SJeff Kirsher #define IXGBE_FDIRVLAN_FLEX_SHIFT 16 2609dee1ad47SJeff Kirsher #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 2610dee1ad47SJeff Kirsher #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 2611dee1ad47SJeff Kirsher 2612dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_CMD_MASK 0x00000003 2613dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2614dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2615dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2616dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 2617dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2618dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2619dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2620dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 2621dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 2622dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_IPV6 0x00000080 2623dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_CLEARHT 0x00000100 2624dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_DROP 0x00000200 2625dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_INT 0x00000400 2626dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_LAST 0x00000800 2627dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_COLLISION 0x00001000 2628dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 2629dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 2630dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 263167359c3cSMark Rustad #define IXGBE_FDIRCMD_RX_TUNNEL_FILTER_SHIFT 23 2632dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 2633dee1ad47SJeff Kirsher #define IXGBE_FDIR_INIT_DONE_POLL 10 2634dee1ad47SJeff Kirsher #define IXGBE_FDIRCMD_CMD_POLL 10 263567359c3cSMark Rustad #define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000 2636dee1ad47SJeff Kirsher 2637dee1ad47SJeff Kirsher #define IXGBE_FDIR_DROP_QUEUE 127 2638dee1ad47SJeff Kirsher 2639dee1ad47SJeff Kirsher /* Manageablility Host Interface defines */ 2640dee1ad47SJeff Kirsher #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 2641dee1ad47SJeff Kirsher #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 2642dee1ad47SJeff Kirsher #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 2643b48e4aa3SDon Skidmore #define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000 /* Process Erase command limit */ 2644b48e4aa3SDon Skidmore #define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ 2645b48e4aa3SDon Skidmore #define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */ 2646dee1ad47SJeff Kirsher 2647dee1ad47SJeff Kirsher /* CEM Support */ 2648dee1ad47SJeff Kirsher #define FW_CEM_HDR_LEN 0x4 2649dee1ad47SJeff Kirsher #define FW_CEM_CMD_DRIVER_INFO 0xDD 2650dee1ad47SJeff Kirsher #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 2651dee1ad47SJeff Kirsher #define FW_CEM_CMD_RESERVED 0x0 2652dee1ad47SJeff Kirsher #define FW_CEM_UNUSED_VER 0x0 2653dee1ad47SJeff Kirsher #define FW_CEM_MAX_RETRIES 3 2654dee1ad47SJeff Kirsher #define FW_CEM_RESP_STATUS_SUCCESS 0x1 2655cb8e0514STony Nguyen #define FW_CEM_DRIVER_VERSION_SIZE 39 /* +9 would send 48 bytes to fw */ 26566a14ee0cSDon Skidmore #define FW_READ_SHADOW_RAM_CMD 0x31 26576a14ee0cSDon Skidmore #define FW_READ_SHADOW_RAM_LEN 0x6 26586a14ee0cSDon Skidmore #define FW_WRITE_SHADOW_RAM_CMD 0x33 26596a14ee0cSDon Skidmore #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 26606a14ee0cSDon Skidmore #define FW_SHADOW_RAM_DUMP_CMD 0x36 26616a14ee0cSDon Skidmore #define FW_SHADOW_RAM_DUMP_LEN 0 26626a14ee0cSDon Skidmore #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 26636a14ee0cSDon Skidmore #define FW_NVM_DATA_OFFSET 3 26646a14ee0cSDon Skidmore #define FW_MAX_READ_BUFFER_SIZE 1024 26656a14ee0cSDon Skidmore #define FW_DISABLE_RXEN_CMD 0xDE 26666a14ee0cSDon Skidmore #define FW_DISABLE_RXEN_LEN 0x1 266749425dfcSMark Rustad #define FW_PHY_MGMT_REQ_CMD 0x20 266849425dfcSMark Rustad #define FW_PHY_TOKEN_REQ_CMD 0x0A 266949425dfcSMark Rustad #define FW_PHY_TOKEN_REQ_LEN 2 267049425dfcSMark Rustad #define FW_PHY_TOKEN_REQ 0 267149425dfcSMark Rustad #define FW_PHY_TOKEN_REL 1 267249425dfcSMark Rustad #define FW_PHY_TOKEN_OK 1 267349425dfcSMark Rustad #define FW_PHY_TOKEN_RETRY 0x80 267449425dfcSMark Rustad #define FW_PHY_TOKEN_DELAY 5 /* milliseconds */ 267549425dfcSMark Rustad #define FW_PHY_TOKEN_WAIT 5 /* seconds */ 267649425dfcSMark Rustad #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY) 267749425dfcSMark Rustad #define FW_INT_PHY_REQ_CMD 0xB 267849425dfcSMark Rustad #define FW_INT_PHY_REQ_LEN 10 267949425dfcSMark Rustad #define FW_INT_PHY_REQ_READ 0 268049425dfcSMark Rustad #define FW_INT_PHY_REQ_WRITE 1 268112c78ef0SMark Rustad #define FW_PHY_ACT_REQ_CMD 5 268212c78ef0SMark Rustad #define FW_PHY_ACT_DATA_COUNT 4 268312c78ef0SMark Rustad #define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT) 268412c78ef0SMark Rustad #define FW_PHY_ACT_INIT_PHY 1 268512c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK 2 268612c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_10 BIT(0) 268712c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_100 BIT(1) 268812c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_1G BIT(2) 268912c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_2_5G BIT(3) 269012c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_5G BIT(4) 269112c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_10G BIT(5) 269212c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_20G BIT(6) 269312c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_25G BIT(7) 269412c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_40G BIT(8) 269512c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_50G BIT(9) 269612c78ef0SMark Rustad #define FW_PHY_ACT_LINK_SPEED_100G BIT(10) 269712c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16 269812c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3 << \ 269912c78ef0SMark Rustad HW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT) 270012c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u 270112c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u 270212c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u 270312c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u 270412c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_LP BIT(18) 270512c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_HP BIT(19) 270612c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_EEE BIT(20) 270712c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_AN BIT(22) 270812c78ef0SMark Rustad #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN BIT(0) 270912c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO 3 271012c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO_EEE BIT(19) 271112c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO_FC_TX BIT(20) 271212c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO_FC_RX BIT(21) 271312c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO_POWER BIT(22) 271412c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE BIT(24) 271512c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO_TEMP BIT(25) 271612c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX BIT(28) 271712c78ef0SMark Rustad #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX BIT(29) 271812c78ef0SMark Rustad #define FW_PHY_ACT_FORCE_LINK_DOWN 4 271912c78ef0SMark Rustad #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF BIT(0) 272012c78ef0SMark Rustad #define FW_PHY_ACT_PHY_SW_RESET 5 272112c78ef0SMark Rustad #define FW_PHY_ACT_PHY_HW_RESET 6 272212c78ef0SMark Rustad #define FW_PHY_ACT_GET_PHY_INFO 7 272312c78ef0SMark Rustad #define FW_PHY_ACT_UD_2 0x1002 272412c78ef0SMark Rustad #define FW_PHY_ACT_UD_2_10G_KR_EEE BIT(6) 272512c78ef0SMark Rustad #define FW_PHY_ACT_UD_2_10G_KX4_EEE BIT(5) 272612c78ef0SMark Rustad #define FW_PHY_ACT_UD_2_1G_KX_EEE BIT(4) 272712c78ef0SMark Rustad #define FW_PHY_ACT_UD_2_10G_T_EEE BIT(3) 272812c78ef0SMark Rustad #define FW_PHY_ACT_UD_2_1G_T_EEE BIT(2) 272912c78ef0SMark Rustad #define FW_PHY_ACT_UD_2_100M_TX_EEE BIT(1) 273012c78ef0SMark Rustad #define FW_PHY_ACT_RETRIES 50 273112c78ef0SMark Rustad #define FW_PHY_INFO_SPEED_MASK 0xFFFu 273212c78ef0SMark Rustad #define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u 273312c78ef0SMark Rustad #define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu 2734dee1ad47SJeff Kirsher 2735dee1ad47SJeff Kirsher /* Host Interface Command Structures */ 2736dee1ad47SJeff Kirsher struct ixgbe_hic_hdr { 2737dee1ad47SJeff Kirsher u8 cmd; 2738dee1ad47SJeff Kirsher u8 buf_len; 2739dee1ad47SJeff Kirsher union { 2740dee1ad47SJeff Kirsher u8 cmd_resv; 2741dee1ad47SJeff Kirsher u8 ret_status; 2742dee1ad47SJeff Kirsher } cmd_or_resp; 2743dee1ad47SJeff Kirsher u8 checksum; 2744dee1ad47SJeff Kirsher }; 2745dee1ad47SJeff Kirsher 27466a14ee0cSDon Skidmore struct ixgbe_hic_hdr2_req { 27476a14ee0cSDon Skidmore u8 cmd; 27486a14ee0cSDon Skidmore u8 buf_lenh; 27496a14ee0cSDon Skidmore u8 buf_lenl; 27506a14ee0cSDon Skidmore u8 checksum; 27516a14ee0cSDon Skidmore }; 27526a14ee0cSDon Skidmore 27536a14ee0cSDon Skidmore struct ixgbe_hic_hdr2_rsp { 27546a14ee0cSDon Skidmore u8 cmd; 27556a14ee0cSDon Skidmore u8 buf_lenl; 27566a14ee0cSDon Skidmore u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 27576a14ee0cSDon Skidmore u8 checksum; 27586a14ee0cSDon Skidmore }; 27596a14ee0cSDon Skidmore 27606a14ee0cSDon Skidmore union ixgbe_hic_hdr2 { 27616a14ee0cSDon Skidmore struct ixgbe_hic_hdr2_req req; 27626a14ee0cSDon Skidmore struct ixgbe_hic_hdr2_rsp rsp; 27636a14ee0cSDon Skidmore }; 27646a14ee0cSDon Skidmore 2765dee1ad47SJeff Kirsher struct ixgbe_hic_drv_info { 2766dee1ad47SJeff Kirsher struct ixgbe_hic_hdr hdr; 2767dee1ad47SJeff Kirsher u8 port_num; 2768dee1ad47SJeff Kirsher u8 ver_sub; 2769dee1ad47SJeff Kirsher u8 ver_build; 2770dee1ad47SJeff Kirsher u8 ver_min; 2771dee1ad47SJeff Kirsher u8 ver_maj; 2772dee1ad47SJeff Kirsher u8 pad; /* end spacing to ensure length is mult. of dword */ 2773dee1ad47SJeff Kirsher u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 2774dee1ad47SJeff Kirsher }; 2775dee1ad47SJeff Kirsher 2776cb8e0514STony Nguyen struct ixgbe_hic_drv_info2 { 2777cb8e0514STony Nguyen struct ixgbe_hic_hdr hdr; 2778cb8e0514STony Nguyen u8 port_num; 2779cb8e0514STony Nguyen u8 ver_sub; 2780cb8e0514STony Nguyen u8 ver_build; 2781cb8e0514STony Nguyen u8 ver_min; 2782cb8e0514STony Nguyen u8 ver_maj; 2783cb8e0514STony Nguyen char driver_string[FW_CEM_DRIVER_VERSION_SIZE]; 2784cb8e0514STony Nguyen }; 2785cb8e0514STony Nguyen 27866a14ee0cSDon Skidmore /* These need to be dword aligned */ 27876a14ee0cSDon Skidmore struct ixgbe_hic_read_shadow_ram { 27886a14ee0cSDon Skidmore union ixgbe_hic_hdr2 hdr; 27896a14ee0cSDon Skidmore u32 address; 27906a14ee0cSDon Skidmore u16 length; 27916a14ee0cSDon Skidmore u16 pad2; 27926a14ee0cSDon Skidmore u16 data; 27936a14ee0cSDon Skidmore u16 pad3; 27946a14ee0cSDon Skidmore }; 27956a14ee0cSDon Skidmore 27966a14ee0cSDon Skidmore struct ixgbe_hic_write_shadow_ram { 27976a14ee0cSDon Skidmore union ixgbe_hic_hdr2 hdr; 2798ef5398bbSDon Skidmore __be32 address; 2799ef5398bbSDon Skidmore __be16 length; 28006a14ee0cSDon Skidmore u16 pad2; 28016a14ee0cSDon Skidmore u16 data; 28026a14ee0cSDon Skidmore u16 pad3; 28036a14ee0cSDon Skidmore }; 28046a14ee0cSDon Skidmore 28056a14ee0cSDon Skidmore struct ixgbe_hic_disable_rxen { 28066a14ee0cSDon Skidmore struct ixgbe_hic_hdr hdr; 28076a14ee0cSDon Skidmore u8 port_number; 28086a14ee0cSDon Skidmore u8 pad2; 28096a14ee0cSDon Skidmore u16 pad3; 28106a14ee0cSDon Skidmore }; 28116a14ee0cSDon Skidmore 281249425dfcSMark Rustad struct ixgbe_hic_phy_token_req { 281349425dfcSMark Rustad struct ixgbe_hic_hdr hdr; 281449425dfcSMark Rustad u8 port_number; 281549425dfcSMark Rustad u8 command_type; 281649425dfcSMark Rustad u16 pad; 281749425dfcSMark Rustad }; 281849425dfcSMark Rustad 281949425dfcSMark Rustad struct ixgbe_hic_internal_phy_req { 282049425dfcSMark Rustad struct ixgbe_hic_hdr hdr; 282149425dfcSMark Rustad u8 port_number; 282249425dfcSMark Rustad u8 command_type; 282349425dfcSMark Rustad __be16 address; 282449425dfcSMark Rustad u16 rsv1; 282549425dfcSMark Rustad __be32 write_data; 282649425dfcSMark Rustad u16 pad; 282749425dfcSMark Rustad } __packed; 282849425dfcSMark Rustad 282949425dfcSMark Rustad struct ixgbe_hic_internal_phy_resp { 283049425dfcSMark Rustad struct ixgbe_hic_hdr hdr; 283149425dfcSMark Rustad __be32 read_data; 283249425dfcSMark Rustad }; 283349425dfcSMark Rustad 283412c78ef0SMark Rustad struct ixgbe_hic_phy_activity_req { 283512c78ef0SMark Rustad struct ixgbe_hic_hdr hdr; 283612c78ef0SMark Rustad u8 port_number; 283712c78ef0SMark Rustad u8 pad; 283812c78ef0SMark Rustad __le16 activity_id; 283912c78ef0SMark Rustad __be32 data[FW_PHY_ACT_DATA_COUNT]; 284012c78ef0SMark Rustad }; 284112c78ef0SMark Rustad 284212c78ef0SMark Rustad struct ixgbe_hic_phy_activity_resp { 284312c78ef0SMark Rustad struct ixgbe_hic_hdr hdr; 284412c78ef0SMark Rustad __be32 data[FW_PHY_ACT_DATA_COUNT]; 284512c78ef0SMark Rustad }; 284612c78ef0SMark Rustad 2847dee1ad47SJeff Kirsher /* Transmit Descriptor - Advanced */ 2848dee1ad47SJeff Kirsher union ixgbe_adv_tx_desc { 2849dee1ad47SJeff Kirsher struct { 2850dee1ad47SJeff Kirsher __le64 buffer_addr; /* Address of descriptor's data buf */ 2851dee1ad47SJeff Kirsher __le32 cmd_type_len; 2852dee1ad47SJeff Kirsher __le32 olinfo_status; 2853dee1ad47SJeff Kirsher } read; 2854dee1ad47SJeff Kirsher struct { 2855dee1ad47SJeff Kirsher __le64 rsvd; /* Reserved */ 2856dee1ad47SJeff Kirsher __le32 nxtseq_seed; 2857dee1ad47SJeff Kirsher __le32 status; 2858dee1ad47SJeff Kirsher } wb; 2859dee1ad47SJeff Kirsher }; 2860dee1ad47SJeff Kirsher 2861dee1ad47SJeff Kirsher /* Receive Descriptor - Advanced */ 2862dee1ad47SJeff Kirsher union ixgbe_adv_rx_desc { 2863dee1ad47SJeff Kirsher struct { 2864dee1ad47SJeff Kirsher __le64 pkt_addr; /* Packet buffer address */ 2865dee1ad47SJeff Kirsher __le64 hdr_addr; /* Header buffer address */ 2866dee1ad47SJeff Kirsher } read; 2867dee1ad47SJeff Kirsher struct { 2868dee1ad47SJeff Kirsher struct { 2869dee1ad47SJeff Kirsher union { 2870dee1ad47SJeff Kirsher __le32 data; 2871dee1ad47SJeff Kirsher struct { 2872dee1ad47SJeff Kirsher __le16 pkt_info; /* RSS, Pkt type */ 2873dee1ad47SJeff Kirsher __le16 hdr_info; /* Splithdr, hdrlen */ 2874dee1ad47SJeff Kirsher } hs_rss; 2875dee1ad47SJeff Kirsher } lo_dword; 2876dee1ad47SJeff Kirsher union { 2877dee1ad47SJeff Kirsher __le32 rss; /* RSS Hash */ 2878dee1ad47SJeff Kirsher struct { 2879dee1ad47SJeff Kirsher __le16 ip_id; /* IP id */ 2880dee1ad47SJeff Kirsher __le16 csum; /* Packet Checksum */ 2881dee1ad47SJeff Kirsher } csum_ip; 2882dee1ad47SJeff Kirsher } hi_dword; 2883dee1ad47SJeff Kirsher } lower; 2884dee1ad47SJeff Kirsher struct { 2885dee1ad47SJeff Kirsher __le32 status_error; /* ext status/error */ 2886dee1ad47SJeff Kirsher __le16 length; /* Packet length */ 2887dee1ad47SJeff Kirsher __le16 vlan; /* VLAN tag */ 2888dee1ad47SJeff Kirsher } upper; 2889dee1ad47SJeff Kirsher } wb; /* writeback */ 2890dee1ad47SJeff Kirsher }; 2891dee1ad47SJeff Kirsher 2892dee1ad47SJeff Kirsher /* Context descriptors */ 2893dee1ad47SJeff Kirsher struct ixgbe_adv_tx_context_desc { 2894dee1ad47SJeff Kirsher __le32 vlan_macip_lens; 289559259470SShannon Nelson __le32 fceof_saidx; 2896dee1ad47SJeff Kirsher __le32 type_tucmd_mlhl; 2897dee1ad47SJeff Kirsher __le32 mss_l4len_idx; 2898dee1ad47SJeff Kirsher }; 2899dee1ad47SJeff Kirsher 2900dee1ad47SJeff Kirsher /* Adv Transmit Descriptor Config Masks */ 2901dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 2902dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 29033a6a4edaSJacob Keller #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE 1588 Time Stamp */ 2904dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 2905dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 2906dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 2907dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 2908dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 2909dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 2910dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 2911dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 2912dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 2913dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 2914dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 2915dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 2916dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 2917dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 2918dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 2919dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 2920dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 2921dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 2922dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 2923dee1ad47SJeff Kirsher IXGBE_ADVTXD_POPTS_SHIFT) 2924dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 2925dee1ad47SJeff Kirsher IXGBE_ADVTXD_POPTS_SHIFT) 2926beca8154SShannon Nelson #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 2927dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 2928dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 2929dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 2930dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ 2931dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 2932dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 2933dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 2934dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 2935dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 2936dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 2937dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 2938dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 2939dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 29408b75451bSNeerav Parikh #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* RSV L4 Packet TYPE */ 2941dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ 2942dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 2943dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 2944dee1ad47SJeff Kirsher #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 2945b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_SOF (BIT(2) << 10) /* FC SOF index */ 2946b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_PARINC (BIT(3) << 10) /* Rel_Off in F_CTL */ 2947b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_ORIE (BIT(4) << 10) /* Orientation: End */ 2948b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_ORIS (BIT(5) << 10) /* Orientation: Start */ 2949b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_EOF_N (0u << 10) /* 00: EOFn */ 2950b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_EOF_T (1u << 10) /* 01: EOFt */ 2951b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_EOF_NI (2u << 10) /* 10: EOFni */ 2952b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_EOF_A (3u << 10) /* 11: EOFa */ 2953b4f47a48SJacob Keller #define IXGBE_ADVTXD_FCOEF_EOF_MASK (3u << 10) /* FC EOF index */ 2954dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2955dee1ad47SJeff Kirsher #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2956dee1ad47SJeff Kirsher 2957dee1ad47SJeff Kirsher /* Autonegotiation advertised speeds */ 2958dee1ad47SJeff Kirsher typedef u32 ixgbe_autoneg_advertised; 2959dee1ad47SJeff Kirsher /* Link speed */ 2960dee1ad47SJeff Kirsher typedef u32 ixgbe_link_speed; 2961dee1ad47SJeff Kirsher #define IXGBE_LINK_SPEED_UNKNOWN 0 2962b3eb4e18SMark Rustad #define IXGBE_LINK_SPEED_10_FULL 0x0002 2963dee1ad47SJeff Kirsher #define IXGBE_LINK_SPEED_100_FULL 0x0008 2964dee1ad47SJeff Kirsher #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 29659a75a1acSDon Skidmore #define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400 29669a75a1acSDon Skidmore #define IXGBE_LINK_SPEED_5GB_FULL 0x0800 2967dee1ad47SJeff Kirsher #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 2968dee1ad47SJeff Kirsher #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 2969dee1ad47SJeff Kirsher IXGBE_LINK_SPEED_10GB_FULL) 2970dee1ad47SJeff Kirsher #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 2971dee1ad47SJeff Kirsher IXGBE_LINK_SPEED_1GB_FULL | \ 2972dee1ad47SJeff Kirsher IXGBE_LINK_SPEED_10GB_FULL) 2973dee1ad47SJeff Kirsher 29749da712d2SJohn Fastabend /* Flow Control Data Sheet defined values 29759da712d2SJohn Fastabend * Calculation and defines taken from 802.1bb Annex O 29769da712d2SJohn Fastabend */ 2977dee1ad47SJeff Kirsher 29789da712d2SJohn Fastabend /* BitTimes (BT) conversion */ 29794f8a91adSJohn Fastabend #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 29809da712d2SJohn Fastabend #define IXGBE_B2BT(BT) (BT * 8) 29819da712d2SJohn Fastabend 29829da712d2SJohn Fastabend /* Calculate Delay to respond to PFC */ 29839da712d2SJohn Fastabend #define IXGBE_PFC_D 672 29849da712d2SJohn Fastabend 29859da712d2SJohn Fastabend /* Calculate Cable Delay */ 29869da712d2SJohn Fastabend #define IXGBE_CABLE_DC 5556 /* Delay Copper */ 29879da712d2SJohn Fastabend #define IXGBE_CABLE_DO 5000 /* Delay Optical */ 29889da712d2SJohn Fastabend 29899da712d2SJohn Fastabend /* Calculate Interface Delay X540 */ 29909da712d2SJohn Fastabend #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 29919da712d2SJohn Fastabend #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 29929da712d2SJohn Fastabend #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 29939da712d2SJohn Fastabend 29949da712d2SJohn Fastabend #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 29959da712d2SJohn Fastabend 29969da712d2SJohn Fastabend /* Calculate Interface Delay 82598, 82599 */ 29979da712d2SJohn Fastabend #define IXGBE_PHY_D 12800 29989da712d2SJohn Fastabend #define IXGBE_MAC_D 4096 29999da712d2SJohn Fastabend #define IXGBE_XAUI_D (2 * 1024) 30009da712d2SJohn Fastabend 30019da712d2SJohn Fastabend #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 30029da712d2SJohn Fastabend 30039da712d2SJohn Fastabend /* Calculate Delay incurred from higher layer */ 30049da712d2SJohn Fastabend #define IXGBE_HD 6144 30059da712d2SJohn Fastabend 30069da712d2SJohn Fastabend /* Calculate PCI Bus delay for low thresholds */ 30079da712d2SJohn Fastabend #define IXGBE_PCI_DELAY 10000 30089da712d2SJohn Fastabend 30099da712d2SJohn Fastabend /* Calculate X540 delay value in bit times */ 30104f8a91adSJohn Fastabend #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ 30114f8a91adSJohn Fastabend ((36 * \ 30124f8a91adSJohn Fastabend (IXGBE_B2BT(_max_frame_link) + \ 30134f8a91adSJohn Fastabend IXGBE_PFC_D + \ 30149da712d2SJohn Fastabend (2 * IXGBE_CABLE_DC) + \ 30159da712d2SJohn Fastabend (2 * IXGBE_ID_X540) + \ 30164f8a91adSJohn Fastabend IXGBE_HD) / 25 + 1) + \ 30174f8a91adSJohn Fastabend 2 * IXGBE_B2BT(_max_frame_tc)) 30189da712d2SJohn Fastabend 30199da712d2SJohn Fastabend /* Calculate 82599, 82598 delay value in bit times */ 30204f8a91adSJohn Fastabend #define IXGBE_DV(_max_frame_link, _max_frame_tc) \ 30214f8a91adSJohn Fastabend ((36 * \ 30224f8a91adSJohn Fastabend (IXGBE_B2BT(_max_frame_link) + \ 30234f8a91adSJohn Fastabend IXGBE_PFC_D + \ 30244f8a91adSJohn Fastabend (2 * IXGBE_CABLE_DC) + \ 30254f8a91adSJohn Fastabend (2 * IXGBE_ID) + \ 30264f8a91adSJohn Fastabend IXGBE_HD) / 25 + 1) + \ 30274f8a91adSJohn Fastabend 2 * IXGBE_B2BT(_max_frame_tc)) 30289da712d2SJohn Fastabend 30299da712d2SJohn Fastabend /* Calculate low threshold delay values */ 30304f8a91adSJohn Fastabend #define IXGBE_LOW_DV_X540(_max_frame_tc) \ 30314f8a91adSJohn Fastabend (2 * IXGBE_B2BT(_max_frame_tc) + \ 30324f8a91adSJohn Fastabend (36 * IXGBE_PCI_DELAY / 25) + 1) 30334f8a91adSJohn Fastabend #define IXGBE_LOW_DV(_max_frame_tc) \ 30344f8a91adSJohn Fastabend (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) 3035dee1ad47SJeff Kirsher 3036dee1ad47SJeff Kirsher /* Software ATR hash keys */ 3037dee1ad47SJeff Kirsher #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 3038dee1ad47SJeff Kirsher #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 3039dee1ad47SJeff Kirsher 3040dee1ad47SJeff Kirsher /* Software ATR input stream values and masks */ 3041dee1ad47SJeff Kirsher #define IXGBE_ATR_HASH_MASK 0x7fff 3042dee1ad47SJeff Kirsher #define IXGBE_ATR_L4TYPE_MASK 0x3 3043dee1ad47SJeff Kirsher #define IXGBE_ATR_L4TYPE_UDP 0x1 3044dee1ad47SJeff Kirsher #define IXGBE_ATR_L4TYPE_TCP 0x2 3045dee1ad47SJeff Kirsher #define IXGBE_ATR_L4TYPE_SCTP 0x3 3046dee1ad47SJeff Kirsher #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 304767359c3cSMark Rustad #define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10 3048dee1ad47SJeff Kirsher enum ixgbe_atr_flow_type { 3049dee1ad47SJeff Kirsher IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 3050dee1ad47SJeff Kirsher IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 3051dee1ad47SJeff Kirsher IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 3052dee1ad47SJeff Kirsher IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 3053dee1ad47SJeff Kirsher IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 3054dee1ad47SJeff Kirsher IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 3055dee1ad47SJeff Kirsher IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 3056dee1ad47SJeff Kirsher IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 3057dee1ad47SJeff Kirsher }; 3058dee1ad47SJeff Kirsher 3059dee1ad47SJeff Kirsher /* Flow Director ATR input struct. */ 3060dee1ad47SJeff Kirsher union ixgbe_atr_input { 3061dee1ad47SJeff Kirsher /* 3062dee1ad47SJeff Kirsher * Byte layout in order, all values with MSB first: 3063dee1ad47SJeff Kirsher * 3064dee1ad47SJeff Kirsher * vm_pool - 1 byte 3065dee1ad47SJeff Kirsher * flow_type - 1 byte 3066dee1ad47SJeff Kirsher * vlan_id - 2 bytes 3067dee1ad47SJeff Kirsher * src_ip - 16 bytes 3068dee1ad47SJeff Kirsher * dst_ip - 16 bytes 3069dee1ad47SJeff Kirsher * src_port - 2 bytes 3070dee1ad47SJeff Kirsher * dst_port - 2 bytes 3071dee1ad47SJeff Kirsher * flex_bytes - 2 bytes 3072dee1ad47SJeff Kirsher * bkt_hash - 2 bytes 3073dee1ad47SJeff Kirsher */ 3074dee1ad47SJeff Kirsher struct { 3075dee1ad47SJeff Kirsher u8 vm_pool; 3076dee1ad47SJeff Kirsher u8 flow_type; 3077dee1ad47SJeff Kirsher __be16 vlan_id; 3078dee1ad47SJeff Kirsher __be32 dst_ip[4]; 3079dee1ad47SJeff Kirsher __be32 src_ip[4]; 3080dee1ad47SJeff Kirsher __be16 src_port; 3081dee1ad47SJeff Kirsher __be16 dst_port; 3082dee1ad47SJeff Kirsher __be16 flex_bytes; 3083dee1ad47SJeff Kirsher __be16 bkt_hash; 3084dee1ad47SJeff Kirsher } formatted; 3085dee1ad47SJeff Kirsher __be32 dword_stream[11]; 3086dee1ad47SJeff Kirsher }; 3087dee1ad47SJeff Kirsher 3088dee1ad47SJeff Kirsher /* Flow Director compressed ATR hash input struct */ 3089dee1ad47SJeff Kirsher union ixgbe_atr_hash_dword { 3090dee1ad47SJeff Kirsher struct { 3091dee1ad47SJeff Kirsher u8 vm_pool; 3092dee1ad47SJeff Kirsher u8 flow_type; 3093dee1ad47SJeff Kirsher __be16 vlan_id; 3094dee1ad47SJeff Kirsher } formatted; 3095dee1ad47SJeff Kirsher __be32 ip; 3096dee1ad47SJeff Kirsher struct { 3097dee1ad47SJeff Kirsher __be16 src; 3098dee1ad47SJeff Kirsher __be16 dst; 3099dee1ad47SJeff Kirsher } port; 3100dee1ad47SJeff Kirsher __be16 flex_bytes; 3101dee1ad47SJeff Kirsher __be32 dword; 3102dee1ad47SJeff Kirsher }; 3103dee1ad47SJeff Kirsher 31049a900ecaSDon Skidmore #define IXGBE_MVALS_INIT(m) \ 31059a900ecaSDon Skidmore IXGBE_CAT(EEC, m), \ 31069a900ecaSDon Skidmore IXGBE_CAT(FLA, m), \ 31079a900ecaSDon Skidmore IXGBE_CAT(GRC, m), \ 31089a900ecaSDon Skidmore IXGBE_CAT(FACTPS, m), \ 31099a900ecaSDon Skidmore IXGBE_CAT(SWSM, m), \ 31109a900ecaSDon Skidmore IXGBE_CAT(SWFW_SYNC, m), \ 31119a900ecaSDon Skidmore IXGBE_CAT(FWSM, m), \ 31129a900ecaSDon Skidmore IXGBE_CAT(SDP0_GPIEN, m), \ 31139a900ecaSDon Skidmore IXGBE_CAT(SDP1_GPIEN, m), \ 31149a900ecaSDon Skidmore IXGBE_CAT(SDP2_GPIEN, m), \ 31159a900ecaSDon Skidmore IXGBE_CAT(EICR_GPI_SDP0, m), \ 31169a900ecaSDon Skidmore IXGBE_CAT(EICR_GPI_SDP1, m), \ 31179a900ecaSDon Skidmore IXGBE_CAT(EICR_GPI_SDP2, m), \ 31189a900ecaSDon Skidmore IXGBE_CAT(CIAA, m), \ 31199a900ecaSDon Skidmore IXGBE_CAT(CIAD, m), \ 31209a900ecaSDon Skidmore IXGBE_CAT(I2C_CLK_IN, m), \ 31219a900ecaSDon Skidmore IXGBE_CAT(I2C_CLK_OUT, m), \ 31229a900ecaSDon Skidmore IXGBE_CAT(I2C_DATA_IN, m), \ 31239a900ecaSDon Skidmore IXGBE_CAT(I2C_DATA_OUT, m), \ 31249a900ecaSDon Skidmore IXGBE_CAT(I2C_DATA_OE_N_EN, m), \ 31259a900ecaSDon Skidmore IXGBE_CAT(I2C_BB_EN, m), \ 31269a900ecaSDon Skidmore IXGBE_CAT(I2C_CLK_OE_N_EN, m), \ 31279a900ecaSDon Skidmore IXGBE_CAT(I2CCTL, m) 31289a900ecaSDon Skidmore 31299a900ecaSDon Skidmore enum ixgbe_mvals { 31309a900ecaSDon Skidmore IXGBE_MVALS_INIT(IDX), 31319a900ecaSDon Skidmore IXGBE_MVALS_IDX_LIMIT 31329a900ecaSDon Skidmore }; 31339a900ecaSDon Skidmore 3134dee1ad47SJeff Kirsher enum ixgbe_eeprom_type { 3135dee1ad47SJeff Kirsher ixgbe_eeprom_uninitialized = 0, 3136dee1ad47SJeff Kirsher ixgbe_eeprom_spi, 3137dee1ad47SJeff Kirsher ixgbe_flash, 3138dee1ad47SJeff Kirsher ixgbe_eeprom_none /* No NVM support */ 3139dee1ad47SJeff Kirsher }; 3140dee1ad47SJeff Kirsher 3141dee1ad47SJeff Kirsher enum ixgbe_mac_type { 3142dee1ad47SJeff Kirsher ixgbe_mac_unknown = 0, 3143dee1ad47SJeff Kirsher ixgbe_mac_82598EB, 3144dee1ad47SJeff Kirsher ixgbe_mac_82599EB, 3145dee1ad47SJeff Kirsher ixgbe_mac_X540, 31469a75a1acSDon Skidmore ixgbe_mac_X550, 31479a75a1acSDon Skidmore ixgbe_mac_X550EM_x, 3148207969b9SMark Rustad ixgbe_mac_x550em_a, 3149dee1ad47SJeff Kirsher ixgbe_num_macs 3150dee1ad47SJeff Kirsher }; 3151dee1ad47SJeff Kirsher 3152dee1ad47SJeff Kirsher enum ixgbe_phy_type { 3153dee1ad47SJeff Kirsher ixgbe_phy_unknown = 0, 3154dee1ad47SJeff Kirsher ixgbe_phy_none, 3155dee1ad47SJeff Kirsher ixgbe_phy_tn, 3156dee1ad47SJeff Kirsher ixgbe_phy_aq, 31576a14ee0cSDon Skidmore ixgbe_phy_x550em_kr, 31586a14ee0cSDon Skidmore ixgbe_phy_x550em_kx4, 315918e01ee7SDon Skidmore ixgbe_phy_x550em_xfi, 31606a14ee0cSDon Skidmore ixgbe_phy_x550em_ext_t, 31618dc963e1SPaul Greenwalt ixgbe_phy_ext_1g_t, 3162dee1ad47SJeff Kirsher ixgbe_phy_cu_unknown, 3163dee1ad47SJeff Kirsher ixgbe_phy_qt, 3164dee1ad47SJeff Kirsher ixgbe_phy_xaui, 3165dee1ad47SJeff Kirsher ixgbe_phy_nl, 3166dee1ad47SJeff Kirsher ixgbe_phy_sfp_passive_tyco, 3167dee1ad47SJeff Kirsher ixgbe_phy_sfp_passive_unknown, 3168dee1ad47SJeff Kirsher ixgbe_phy_sfp_active_unknown, 3169dee1ad47SJeff Kirsher ixgbe_phy_sfp_avago, 3170dee1ad47SJeff Kirsher ixgbe_phy_sfp_ftl, 3171dee1ad47SJeff Kirsher ixgbe_phy_sfp_ftl_active, 3172dee1ad47SJeff Kirsher ixgbe_phy_sfp_unknown, 3173dee1ad47SJeff Kirsher ixgbe_phy_sfp_intel, 31748f58332bSDon Skidmore ixgbe_phy_qsfp_passive_unknown, 31758f58332bSDon Skidmore ixgbe_phy_qsfp_active_unknown, 31768f58332bSDon Skidmore ixgbe_phy_qsfp_intel, 31778f58332bSDon Skidmore ixgbe_phy_qsfp_unknown, 3178dee1ad47SJeff Kirsher ixgbe_phy_sfp_unsupported, 3179200157c2SMark Rustad ixgbe_phy_sgmii, 3180b3eb4e18SMark Rustad ixgbe_phy_fw, 3181dee1ad47SJeff Kirsher ixgbe_phy_generic 3182dee1ad47SJeff Kirsher }; 3183dee1ad47SJeff Kirsher 3184dee1ad47SJeff Kirsher /* 3185dee1ad47SJeff Kirsher * SFP+ module type IDs: 3186dee1ad47SJeff Kirsher * 3187dee1ad47SJeff Kirsher * ID Module Type 3188dee1ad47SJeff Kirsher * ============= 3189dee1ad47SJeff Kirsher * 0 SFP_DA_CU 3190dee1ad47SJeff Kirsher * 1 SFP_SR 3191dee1ad47SJeff Kirsher * 2 SFP_LR 3192dee1ad47SJeff Kirsher * 3 SFP_DA_CU_CORE0 - 82599-specific 3193dee1ad47SJeff Kirsher * 4 SFP_DA_CU_CORE1 - 82599-specific 3194dee1ad47SJeff Kirsher * 5 SFP_SR/LR_CORE0 - 82599-specific 3195dee1ad47SJeff Kirsher * 6 SFP_SR/LR_CORE1 - 82599-specific 3196dee1ad47SJeff Kirsher */ 3197dee1ad47SJeff Kirsher enum ixgbe_sfp_type { 3198dee1ad47SJeff Kirsher ixgbe_sfp_type_da_cu = 0, 3199dee1ad47SJeff Kirsher ixgbe_sfp_type_sr = 1, 3200dee1ad47SJeff Kirsher ixgbe_sfp_type_lr = 2, 3201dee1ad47SJeff Kirsher ixgbe_sfp_type_da_cu_core0 = 3, 3202dee1ad47SJeff Kirsher ixgbe_sfp_type_da_cu_core1 = 4, 3203dee1ad47SJeff Kirsher ixgbe_sfp_type_srlr_core0 = 5, 3204dee1ad47SJeff Kirsher ixgbe_sfp_type_srlr_core1 = 6, 3205dee1ad47SJeff Kirsher ixgbe_sfp_type_da_act_lmt_core0 = 7, 3206dee1ad47SJeff Kirsher ixgbe_sfp_type_da_act_lmt_core1 = 8, 3207dee1ad47SJeff Kirsher ixgbe_sfp_type_1g_cu_core0 = 9, 3208dee1ad47SJeff Kirsher ixgbe_sfp_type_1g_cu_core1 = 10, 3209a49fda3eSJacob Keller ixgbe_sfp_type_1g_sx_core0 = 11, 3210a49fda3eSJacob Keller ixgbe_sfp_type_1g_sx_core1 = 12, 3211345be204SDon Skidmore ixgbe_sfp_type_1g_lx_core0 = 13, 3212345be204SDon Skidmore ixgbe_sfp_type_1g_lx_core1 = 14, 3213dee1ad47SJeff Kirsher ixgbe_sfp_type_not_present = 0xFFFE, 3214dee1ad47SJeff Kirsher ixgbe_sfp_type_unknown = 0xFFFF 3215dee1ad47SJeff Kirsher }; 3216dee1ad47SJeff Kirsher 3217dee1ad47SJeff Kirsher enum ixgbe_media_type { 3218dee1ad47SJeff Kirsher ixgbe_media_type_unknown = 0, 3219dee1ad47SJeff Kirsher ixgbe_media_type_fiber, 32208f58332bSDon Skidmore ixgbe_media_type_fiber_qsfp, 3221dee1ad47SJeff Kirsher ixgbe_media_type_fiber_lco, 3222dee1ad47SJeff Kirsher ixgbe_media_type_copper, 3223dee1ad47SJeff Kirsher ixgbe_media_type_backplane, 3224dee1ad47SJeff Kirsher ixgbe_media_type_cx4, 3225dee1ad47SJeff Kirsher ixgbe_media_type_virtual 3226dee1ad47SJeff Kirsher }; 3227dee1ad47SJeff Kirsher 3228dee1ad47SJeff Kirsher /* Flow Control Settings */ 3229dee1ad47SJeff Kirsher enum ixgbe_fc_mode { 3230dee1ad47SJeff Kirsher ixgbe_fc_none = 0, 3231dee1ad47SJeff Kirsher ixgbe_fc_rx_pause, 3232dee1ad47SJeff Kirsher ixgbe_fc_tx_pause, 3233dee1ad47SJeff Kirsher ixgbe_fc_full, 3234dee1ad47SJeff Kirsher ixgbe_fc_default 3235dee1ad47SJeff Kirsher }; 3236dee1ad47SJeff Kirsher 3237dee1ad47SJeff Kirsher /* Smart Speed Settings */ 3238dee1ad47SJeff Kirsher #define IXGBE_SMARTSPEED_MAX_RETRIES 3 3239dee1ad47SJeff Kirsher enum ixgbe_smart_speed { 3240dee1ad47SJeff Kirsher ixgbe_smart_speed_auto = 0, 3241dee1ad47SJeff Kirsher ixgbe_smart_speed_on, 3242dee1ad47SJeff Kirsher ixgbe_smart_speed_off 3243dee1ad47SJeff Kirsher }; 3244dee1ad47SJeff Kirsher 3245dee1ad47SJeff Kirsher /* PCI bus types */ 3246dee1ad47SJeff Kirsher enum ixgbe_bus_type { 3247dee1ad47SJeff Kirsher ixgbe_bus_type_unknown = 0, 3248dee1ad47SJeff Kirsher ixgbe_bus_type_pci_express, 3249f9328bc6SDon Skidmore ixgbe_bus_type_internal, 3250dee1ad47SJeff Kirsher ixgbe_bus_type_reserved 3251dee1ad47SJeff Kirsher }; 3252dee1ad47SJeff Kirsher 3253dee1ad47SJeff Kirsher /* PCI bus speeds */ 3254dee1ad47SJeff Kirsher enum ixgbe_bus_speed { 3255dee1ad47SJeff Kirsher ixgbe_bus_speed_unknown = 0, 3256dee1ad47SJeff Kirsher ixgbe_bus_speed_33 = 33, 3257dee1ad47SJeff Kirsher ixgbe_bus_speed_66 = 66, 3258dee1ad47SJeff Kirsher ixgbe_bus_speed_100 = 100, 3259dee1ad47SJeff Kirsher ixgbe_bus_speed_120 = 120, 3260dee1ad47SJeff Kirsher ixgbe_bus_speed_133 = 133, 3261dee1ad47SJeff Kirsher ixgbe_bus_speed_2500 = 2500, 3262dee1ad47SJeff Kirsher ixgbe_bus_speed_5000 = 5000, 3263e8710a5fSJacob Keller ixgbe_bus_speed_8000 = 8000, 3264dee1ad47SJeff Kirsher ixgbe_bus_speed_reserved 3265dee1ad47SJeff Kirsher }; 3266dee1ad47SJeff Kirsher 3267dee1ad47SJeff Kirsher /* PCI bus widths */ 3268dee1ad47SJeff Kirsher enum ixgbe_bus_width { 3269dee1ad47SJeff Kirsher ixgbe_bus_width_unknown = 0, 3270dee1ad47SJeff Kirsher ixgbe_bus_width_pcie_x1 = 1, 3271dee1ad47SJeff Kirsher ixgbe_bus_width_pcie_x2 = 2, 3272dee1ad47SJeff Kirsher ixgbe_bus_width_pcie_x4 = 4, 3273dee1ad47SJeff Kirsher ixgbe_bus_width_pcie_x8 = 8, 3274dee1ad47SJeff Kirsher ixgbe_bus_width_32 = 32, 3275dee1ad47SJeff Kirsher ixgbe_bus_width_64 = 64, 3276dee1ad47SJeff Kirsher ixgbe_bus_width_reserved 3277dee1ad47SJeff Kirsher }; 3278dee1ad47SJeff Kirsher 3279dee1ad47SJeff Kirsher struct ixgbe_addr_filter_info { 3280dee1ad47SJeff Kirsher u32 num_mc_addrs; 3281dee1ad47SJeff Kirsher u32 rar_used_count; 3282dee1ad47SJeff Kirsher u32 mta_in_use; 3283dee1ad47SJeff Kirsher u32 overflow_promisc; 3284dee1ad47SJeff Kirsher bool uc_set_promisc; 3285dee1ad47SJeff Kirsher bool user_set_promisc; 3286dee1ad47SJeff Kirsher }; 3287dee1ad47SJeff Kirsher 3288dee1ad47SJeff Kirsher /* Bus parameters */ 3289dee1ad47SJeff Kirsher struct ixgbe_bus_info { 3290dee1ad47SJeff Kirsher enum ixgbe_bus_speed speed; 3291dee1ad47SJeff Kirsher enum ixgbe_bus_width width; 3292dee1ad47SJeff Kirsher enum ixgbe_bus_type type; 3293dee1ad47SJeff Kirsher 32943775b814SMark Rustad u8 func; 32953775b814SMark Rustad u8 lan_id; 3296c898fe28SMark Rustad u8 instance_id; 3297dee1ad47SJeff Kirsher }; 3298dee1ad47SJeff Kirsher 3299dee1ad47SJeff Kirsher /* Flow control parameters */ 3300dee1ad47SJeff Kirsher struct ixgbe_fc_info { 33019da712d2SJohn Fastabend u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */ 3302e5776620SJacob Keller u32 low_water[MAX_TRAFFIC_CLASS]; /* Flow Control Low-water */ 3303dee1ad47SJeff Kirsher u16 pause_time; /* Flow Control Pause timer */ 3304dee1ad47SJeff Kirsher bool send_xon; /* Flow control send XON */ 3305dee1ad47SJeff Kirsher bool strict_ieee; /* Strict IEEE mode */ 3306dee1ad47SJeff Kirsher bool disable_fc_autoneg; /* Do not autonegotiate FC */ 3307dee1ad47SJeff Kirsher bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 3308dee1ad47SJeff Kirsher enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 3309dee1ad47SJeff Kirsher enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 3310dee1ad47SJeff Kirsher }; 3311dee1ad47SJeff Kirsher 3312dee1ad47SJeff Kirsher /* Statistics counters collected by the MAC */ 3313dee1ad47SJeff Kirsher struct ixgbe_hw_stats { 3314dee1ad47SJeff Kirsher u64 crcerrs; 3315dee1ad47SJeff Kirsher u64 illerrc; 3316dee1ad47SJeff Kirsher u64 errbc; 3317dee1ad47SJeff Kirsher u64 mspdc; 3318dee1ad47SJeff Kirsher u64 mpctotal; 3319dee1ad47SJeff Kirsher u64 mpc[8]; 3320dee1ad47SJeff Kirsher u64 mlfc; 3321dee1ad47SJeff Kirsher u64 mrfc; 3322dee1ad47SJeff Kirsher u64 rlec; 3323dee1ad47SJeff Kirsher u64 lxontxc; 3324dee1ad47SJeff Kirsher u64 lxonrxc; 3325dee1ad47SJeff Kirsher u64 lxofftxc; 3326dee1ad47SJeff Kirsher u64 lxoffrxc; 3327dee1ad47SJeff Kirsher u64 pxontxc[8]; 3328dee1ad47SJeff Kirsher u64 pxonrxc[8]; 3329dee1ad47SJeff Kirsher u64 pxofftxc[8]; 3330dee1ad47SJeff Kirsher u64 pxoffrxc[8]; 3331dee1ad47SJeff Kirsher u64 prc64; 3332dee1ad47SJeff Kirsher u64 prc127; 3333dee1ad47SJeff Kirsher u64 prc255; 3334dee1ad47SJeff Kirsher u64 prc511; 3335dee1ad47SJeff Kirsher u64 prc1023; 3336dee1ad47SJeff Kirsher u64 prc1522; 3337dee1ad47SJeff Kirsher u64 gprc; 3338dee1ad47SJeff Kirsher u64 bprc; 3339dee1ad47SJeff Kirsher u64 mprc; 3340dee1ad47SJeff Kirsher u64 gptc; 3341dee1ad47SJeff Kirsher u64 gorc; 3342dee1ad47SJeff Kirsher u64 gotc; 3343dee1ad47SJeff Kirsher u64 rnbc[8]; 3344dee1ad47SJeff Kirsher u64 ruc; 3345dee1ad47SJeff Kirsher u64 rfc; 3346dee1ad47SJeff Kirsher u64 roc; 3347dee1ad47SJeff Kirsher u64 rjc; 3348dee1ad47SJeff Kirsher u64 mngprc; 3349dee1ad47SJeff Kirsher u64 mngpdc; 3350dee1ad47SJeff Kirsher u64 mngptc; 3351dee1ad47SJeff Kirsher u64 tor; 3352dee1ad47SJeff Kirsher u64 tpr; 3353dee1ad47SJeff Kirsher u64 tpt; 3354dee1ad47SJeff Kirsher u64 ptc64; 3355dee1ad47SJeff Kirsher u64 ptc127; 3356dee1ad47SJeff Kirsher u64 ptc255; 3357dee1ad47SJeff Kirsher u64 ptc511; 3358dee1ad47SJeff Kirsher u64 ptc1023; 3359dee1ad47SJeff Kirsher u64 ptc1522; 3360dee1ad47SJeff Kirsher u64 mptc; 3361dee1ad47SJeff Kirsher u64 bptc; 3362dee1ad47SJeff Kirsher u64 xec; 3363dee1ad47SJeff Kirsher u64 rqsmr[16]; 3364dee1ad47SJeff Kirsher u64 tqsmr[8]; 3365dee1ad47SJeff Kirsher u64 qprc[16]; 3366dee1ad47SJeff Kirsher u64 qptc[16]; 3367dee1ad47SJeff Kirsher u64 qbrc[16]; 3368dee1ad47SJeff Kirsher u64 qbtc[16]; 3369dee1ad47SJeff Kirsher u64 qprdc[16]; 3370dee1ad47SJeff Kirsher u64 pxon2offc[8]; 3371dee1ad47SJeff Kirsher u64 fdirustat_add; 3372dee1ad47SJeff Kirsher u64 fdirustat_remove; 3373dee1ad47SJeff Kirsher u64 fdirfstat_fadd; 3374dee1ad47SJeff Kirsher u64 fdirfstat_fremove; 3375dee1ad47SJeff Kirsher u64 fdirmatch; 3376dee1ad47SJeff Kirsher u64 fdirmiss; 3377dee1ad47SJeff Kirsher u64 fccrc; 3378dee1ad47SJeff Kirsher u64 fcoerpdc; 3379dee1ad47SJeff Kirsher u64 fcoeprc; 3380dee1ad47SJeff Kirsher u64 fcoeptc; 3381dee1ad47SJeff Kirsher u64 fcoedwrc; 3382dee1ad47SJeff Kirsher u64 fcoedwtc; 33837b859ebcSAmir Hanania u64 fcoe_noddp; 33847b859ebcSAmir Hanania u64 fcoe_noddp_ext_buff; 3385dee1ad47SJeff Kirsher u64 b2ospc; 3386dee1ad47SJeff Kirsher u64 b2ogprc; 3387dee1ad47SJeff Kirsher u64 o2bgptc; 3388dee1ad47SJeff Kirsher u64 o2bspc; 3389dee1ad47SJeff Kirsher }; 3390dee1ad47SJeff Kirsher 3391dee1ad47SJeff Kirsher /* forward declaration */ 3392dee1ad47SJeff Kirsher struct ixgbe_hw; 3393dee1ad47SJeff Kirsher 3394dee1ad47SJeff Kirsher /* Function pointer table */ 3395dee1ad47SJeff Kirsher struct ixgbe_eeprom_operations { 3396dee1ad47SJeff Kirsher s32 (*init_params)(struct ixgbe_hw *); 3397dee1ad47SJeff Kirsher s32 (*read)(struct ixgbe_hw *, u16, u16 *); 3398dee1ad47SJeff Kirsher s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3399dee1ad47SJeff Kirsher s32 (*write)(struct ixgbe_hw *, u16, u16); 3400dee1ad47SJeff Kirsher s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3401dee1ad47SJeff Kirsher s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 3402dee1ad47SJeff Kirsher s32 (*update_checksum)(struct ixgbe_hw *); 3403735c35afSDon Skidmore s32 (*calc_checksum)(struct ixgbe_hw *); 3404dee1ad47SJeff Kirsher }; 3405dee1ad47SJeff Kirsher 3406dee1ad47SJeff Kirsher struct ixgbe_mac_operations { 3407dee1ad47SJeff Kirsher s32 (*init_hw)(struct ixgbe_hw *); 3408dee1ad47SJeff Kirsher s32 (*reset_hw)(struct ixgbe_hw *); 3409dee1ad47SJeff Kirsher s32 (*start_hw)(struct ixgbe_hw *); 3410dee1ad47SJeff Kirsher s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 3411dee1ad47SJeff Kirsher enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 3412dee1ad47SJeff Kirsher s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 3413dee1ad47SJeff Kirsher s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 3414dee1ad47SJeff Kirsher s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 3415dee1ad47SJeff Kirsher s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 3416dee1ad47SJeff Kirsher s32 (*stop_adapter)(struct ixgbe_hw *); 3417dee1ad47SJeff Kirsher s32 (*get_bus_info)(struct ixgbe_hw *); 3418dee1ad47SJeff Kirsher void (*set_lan_id)(struct ixgbe_hw *); 3419dee1ad47SJeff Kirsher s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 3420dee1ad47SJeff Kirsher s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 3421dee1ad47SJeff Kirsher s32 (*setup_sfp)(struct ixgbe_hw *); 3422d2f5e7f3SAtita Shirwaikar s32 (*disable_rx_buff)(struct ixgbe_hw *); 3423d2f5e7f3SAtita Shirwaikar s32 (*enable_rx_buff)(struct ixgbe_hw *); 3424dee1ad47SJeff Kirsher s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 3425030eaeceSDon Skidmore s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32); 3426030eaeceSDon Skidmore void (*release_swfw_sync)(struct ixgbe_hw *, u32); 3427dbd15b8fSDon Skidmore void (*init_swfw_sync)(struct ixgbe_hw *); 3428429d6a3bSDon Skidmore s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *); 3429429d6a3bSDon Skidmore s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool); 3430dee1ad47SJeff Kirsher 3431dee1ad47SJeff Kirsher /* Link */ 3432dee1ad47SJeff Kirsher void (*disable_tx_laser)(struct ixgbe_hw *); 3433dee1ad47SJeff Kirsher void (*enable_tx_laser)(struct ixgbe_hw *); 3434dee1ad47SJeff Kirsher void (*flap_tx_laser)(struct ixgbe_hw *); 3435f4f1040aSJacob Keller void (*stop_link_on_d3)(struct ixgbe_hw *); 3436fd0326f2SJosh Hay s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 34376d373a1bSMark Rustad s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3438dee1ad47SJeff Kirsher s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 3439dee1ad47SJeff Kirsher s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 3440dee1ad47SJeff Kirsher bool *); 34416d373a1bSMark Rustad void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed); 3442dee1ad47SJeff Kirsher 3443dee1ad47SJeff Kirsher /* Packet Buffer Manipulation */ 3444dee1ad47SJeff Kirsher void (*set_rxpba)(struct ixgbe_hw *, int, u32, int); 3445dee1ad47SJeff Kirsher 3446dee1ad47SJeff Kirsher /* LED */ 3447dee1ad47SJeff Kirsher s32 (*led_on)(struct ixgbe_hw *, u32); 3448dee1ad47SJeff Kirsher s32 (*led_off)(struct ixgbe_hw *, u32); 3449dee1ad47SJeff Kirsher s32 (*blink_led_start)(struct ixgbe_hw *, u32); 3450dee1ad47SJeff Kirsher s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 3451805cedd6SDon Skidmore s32 (*init_led_link_act)(struct ixgbe_hw *); 3452dee1ad47SJeff Kirsher 3453dee1ad47SJeff Kirsher /* RAR, Multicast, VLAN */ 3454dee1ad47SJeff Kirsher s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 3455dee1ad47SJeff Kirsher s32 (*clear_rar)(struct ixgbe_hw *, u32); 3456dee1ad47SJeff Kirsher s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 34577fa7c9dcSAlexander Duyck s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); 3458dee1ad47SJeff Kirsher s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 3459dee1ad47SJeff Kirsher s32 (*init_rx_addrs)(struct ixgbe_hw *); 3460dee1ad47SJeff Kirsher s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *); 3461dee1ad47SJeff Kirsher s32 (*enable_mc)(struct ixgbe_hw *); 3462dee1ad47SJeff Kirsher s32 (*disable_mc)(struct ixgbe_hw *); 3463dee1ad47SJeff Kirsher s32 (*clear_vfta)(struct ixgbe_hw *); 3464b6488b66SAlexander Duyck s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool); 3465dee1ad47SJeff Kirsher s32 (*init_uta_tables)(struct ixgbe_hw *); 3466dee1ad47SJeff Kirsher void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 3467dee1ad47SJeff Kirsher void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 3468dee1ad47SJeff Kirsher 3469dee1ad47SJeff Kirsher /* Flow Control */ 3470041441d0SAlexander Duyck s32 (*fc_enable)(struct ixgbe_hw *); 3471afdc71e4SMark Rustad s32 (*setup_fc)(struct ixgbe_hw *); 34722916500dSDon Skidmore void (*fc_autoneg)(struct ixgbe_hw *); 3473dee1ad47SJeff Kirsher 3474dee1ad47SJeff Kirsher /* Manageability interface */ 3475cb8e0514STony Nguyen s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16, 3476cb8e0514STony Nguyen const char *); 3477e1ea9158SDon Skidmore s32 (*get_thermal_sensor_data)(struct ixgbe_hw *); 3478e1ea9158SDon Skidmore s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw); 347959dd45d5SSebastian Basierski bool (*fw_recovery_mode)(struct ixgbe_hw *hw); 34801f9ac57cSDon Skidmore void (*disable_rx)(struct ixgbe_hw *hw); 34811f9ac57cSDon Skidmore void (*enable_rx)(struct ixgbe_hw *hw); 34826d4c96adSDon Skidmore void (*set_source_address_pruning)(struct ixgbe_hw *, bool, 34836d4c96adSDon Skidmore unsigned int); 34845b7f000fSDon Skidmore void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int); 34856a14ee0cSDon Skidmore 34866a14ee0cSDon Skidmore /* DMA Coalescing */ 34876a14ee0cSDon Skidmore s32 (*dmac_config)(struct ixgbe_hw *hw); 34886a14ee0cSDon Skidmore s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); 34896a14ee0cSDon Skidmore s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); 34909a5c27e6SMark Rustad s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *); 34919a5c27e6SMark Rustad s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32); 3492dee1ad47SJeff Kirsher }; 3493dee1ad47SJeff Kirsher 3494dee1ad47SJeff Kirsher struct ixgbe_phy_operations { 3495dee1ad47SJeff Kirsher s32 (*identify)(struct ixgbe_hw *); 3496dee1ad47SJeff Kirsher s32 (*identify_sfp)(struct ixgbe_hw *); 3497dee1ad47SJeff Kirsher s32 (*init)(struct ixgbe_hw *); 3498dee1ad47SJeff Kirsher s32 (*reset)(struct ixgbe_hw *); 3499dee1ad47SJeff Kirsher s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 3500dee1ad47SJeff Kirsher s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 35013dcc2f41SEmil Tantilov s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *); 35023dcc2f41SEmil Tantilov s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16); 3503dee1ad47SJeff Kirsher s32 (*setup_link)(struct ixgbe_hw *); 35046a14ee0cSDon Skidmore s32 (*setup_internal_link)(struct ixgbe_hw *); 350599b76642SJosh Hay s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3506dee1ad47SJeff Kirsher s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 3507dee1ad47SJeff Kirsher s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 3508dee1ad47SJeff Kirsher s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 350907ce870bSEmil Tantilov s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); 3510dee1ad47SJeff Kirsher s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 3511dee1ad47SJeff Kirsher s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 3512*09943985SJedrzej Jagielski bool (*check_overtemp)(struct ixgbe_hw *); 3513961fac88SDon Skidmore s32 (*set_phy_power)(struct ixgbe_hw *, bool on); 35146ac74394SDon Skidmore s32 (*enter_lplu)(struct ixgbe_hw *); 3515*09943985SJedrzej Jagielski s32 (*handle_lasi)(struct ixgbe_hw *hw, bool *); 3516b71f6c40SEmil Tantilov s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, 3517b71f6c40SEmil Tantilov u8 *value); 3518b71f6c40SEmil Tantilov s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, 3519b71f6c40SEmil Tantilov u8 value); 3520b71f6c40SEmil Tantilov }; 3521b71f6c40SEmil Tantilov 3522b71f6c40SEmil Tantilov struct ixgbe_link_operations { 3523b71f6c40SEmil Tantilov s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val); 3524b71f6c40SEmil Tantilov s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, 3525b71f6c40SEmil Tantilov u16 *val); 3526b71f6c40SEmil Tantilov s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val); 3527b71f6c40SEmil Tantilov s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, 3528b71f6c40SEmil Tantilov u16 val); 3529b71f6c40SEmil Tantilov }; 3530b71f6c40SEmil Tantilov 3531b71f6c40SEmil Tantilov struct ixgbe_link_info { 3532b71f6c40SEmil Tantilov struct ixgbe_link_operations ops; 3533b71f6c40SEmil Tantilov u8 addr; 3534dee1ad47SJeff Kirsher }; 3535dee1ad47SJeff Kirsher 3536dee1ad47SJeff Kirsher struct ixgbe_eeprom_info { 3537dee1ad47SJeff Kirsher struct ixgbe_eeprom_operations ops; 3538dee1ad47SJeff Kirsher enum ixgbe_eeprom_type type; 3539dee1ad47SJeff Kirsher u32 semaphore_delay; 3540dee1ad47SJeff Kirsher u16 word_size; 3541dee1ad47SJeff Kirsher u16 address_bits; 3542dee1ad47SJeff Kirsher u16 word_page_size; 35436ac74394SDon Skidmore u16 ctrl_word_3; 3544dee1ad47SJeff Kirsher }; 3545dee1ad47SJeff Kirsher 3546dee1ad47SJeff Kirsher #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 3547dee1ad47SJeff Kirsher struct ixgbe_mac_info { 3548dee1ad47SJeff Kirsher struct ixgbe_mac_operations ops; 3549dee1ad47SJeff Kirsher enum ixgbe_mac_type type; 3550ea99d832SJoe Perches u8 addr[ETH_ALEN]; 3551ea99d832SJoe Perches u8 perm_addr[ETH_ALEN]; 3552ea99d832SJoe Perches u8 san_addr[ETH_ALEN]; 3553dee1ad47SJeff Kirsher /* prefix for World Wide Node Name (WWNN) */ 3554dee1ad47SJeff Kirsher u16 wwnn_prefix; 3555dee1ad47SJeff Kirsher /* prefix for World Wide Port Name (WWPN) */ 3556dee1ad47SJeff Kirsher u16 wwpn_prefix; 355771161302SEmil Tantilov u16 max_msix_vectors; 3558dee1ad47SJeff Kirsher #define IXGBE_MAX_MTA 128 3559dee1ad47SJeff Kirsher u32 mta_shadow[IXGBE_MAX_MTA]; 3560dee1ad47SJeff Kirsher s32 mc_filter_type; 3561dee1ad47SJeff Kirsher u32 mcft_size; 3562dee1ad47SJeff Kirsher u32 vft_size; 3563dee1ad47SJeff Kirsher u32 num_rar_entries; 3564dee1ad47SJeff Kirsher u32 rar_highwater; 3565dee1ad47SJeff Kirsher u32 rx_pb_size; 3566dee1ad47SJeff Kirsher u32 max_tx_queues; 3567dee1ad47SJeff Kirsher u32 max_rx_queues; 3568dee1ad47SJeff Kirsher u32 orig_autoc; 3569dee1ad47SJeff Kirsher u32 orig_autoc2; 3570dee1ad47SJeff Kirsher bool orig_link_settings_stored; 3571dee1ad47SJeff Kirsher bool autotry_restart; 3572dee1ad47SJeff Kirsher u8 flags; 35737fa7c9dcSAlexander Duyck u8 san_mac_rar_index; 3574e1ea9158SDon Skidmore struct ixgbe_thermal_sensor_data thermal_sensor_data; 35751f9ac57cSDon Skidmore bool set_lben; 3576805cedd6SDon Skidmore u8 led_link_act; 3577dee1ad47SJeff Kirsher }; 3578dee1ad47SJeff Kirsher 3579dee1ad47SJeff Kirsher struct ixgbe_phy_info { 3580dee1ad47SJeff Kirsher struct ixgbe_phy_operations ops; 3581dee1ad47SJeff Kirsher struct mdio_if_info mdio; 3582dee1ad47SJeff Kirsher enum ixgbe_phy_type type; 3583dee1ad47SJeff Kirsher u32 id; 3584dee1ad47SJeff Kirsher enum ixgbe_sfp_type sfp_type; 3585dee1ad47SJeff Kirsher bool sfp_setup_needed; 3586dee1ad47SJeff Kirsher u32 revision; 3587dee1ad47SJeff Kirsher enum ixgbe_media_type media_type; 3588030eaeceSDon Skidmore u32 phy_semaphore_mask; 3589dee1ad47SJeff Kirsher bool reset_disable; 3590dee1ad47SJeff Kirsher ixgbe_autoneg_advertised autoneg_advertised; 3591ae8140aaSMark Rustad ixgbe_link_speed speeds_supported; 3592b3eb4e18SMark Rustad ixgbe_link_speed eee_speeds_supported; 3593b3eb4e18SMark Rustad ixgbe_link_speed eee_speeds_advertised; 3594dee1ad47SJeff Kirsher enum ixgbe_smart_speed smart_speed; 3595dee1ad47SJeff Kirsher bool smart_speed_active; 3596dee1ad47SJeff Kirsher bool multispeed_fiber; 3597dee1ad47SJeff Kirsher bool reset_if_overtemp; 35988f58332bSDon Skidmore bool qsfp_shared_i2c_bus; 3599c3dc4c09SDon Skidmore u32 nw_mng_if_sel; 3600dee1ad47SJeff Kirsher }; 3601dee1ad47SJeff Kirsher 3602dee1ad47SJeff Kirsher #include "ixgbe_mbx.h" 3603dee1ad47SJeff Kirsher 3604dee1ad47SJeff Kirsher struct ixgbe_mbx_operations { 3605dee1ad47SJeff Kirsher s32 (*init_params)(struct ixgbe_hw *hw); 3606dee1ad47SJeff Kirsher s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); 3607dee1ad47SJeff Kirsher s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); 3608dee1ad47SJeff Kirsher s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3609dee1ad47SJeff Kirsher s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); 3610dee1ad47SJeff Kirsher s32 (*check_for_msg)(struct ixgbe_hw *, u16); 3611dee1ad47SJeff Kirsher s32 (*check_for_ack)(struct ixgbe_hw *, u16); 3612dee1ad47SJeff Kirsher s32 (*check_for_rst)(struct ixgbe_hw *, u16); 3613dee1ad47SJeff Kirsher }; 3614dee1ad47SJeff Kirsher 3615dee1ad47SJeff Kirsher struct ixgbe_mbx_stats { 3616dee1ad47SJeff Kirsher u32 msgs_tx; 3617dee1ad47SJeff Kirsher u32 msgs_rx; 3618dee1ad47SJeff Kirsher 3619dee1ad47SJeff Kirsher u32 acks; 3620dee1ad47SJeff Kirsher u32 reqs; 3621dee1ad47SJeff Kirsher u32 rsts; 3622dee1ad47SJeff Kirsher }; 3623dee1ad47SJeff Kirsher 3624dee1ad47SJeff Kirsher struct ixgbe_mbx_info { 362537689010SMark Rustad const struct ixgbe_mbx_operations *ops; 3626dee1ad47SJeff Kirsher struct ixgbe_mbx_stats stats; 3627dee1ad47SJeff Kirsher u32 timeout; 3628dee1ad47SJeff Kirsher u32 usec_delay; 3629dee1ad47SJeff Kirsher u32 v2p_mailbox; 3630dee1ad47SJeff Kirsher u16 size; 3631dee1ad47SJeff Kirsher }; 3632dee1ad47SJeff Kirsher 3633dee1ad47SJeff Kirsher struct ixgbe_hw { 3634dee1ad47SJeff Kirsher u8 __iomem *hw_addr; 3635dee1ad47SJeff Kirsher void *back; 3636dee1ad47SJeff Kirsher struct ixgbe_mac_info mac; 3637dee1ad47SJeff Kirsher struct ixgbe_addr_filter_info addr_ctrl; 3638dee1ad47SJeff Kirsher struct ixgbe_fc_info fc; 3639dee1ad47SJeff Kirsher struct ixgbe_phy_info phy; 3640b71f6c40SEmil Tantilov struct ixgbe_link_info link; 3641dee1ad47SJeff Kirsher struct ixgbe_eeprom_info eeprom; 3642dee1ad47SJeff Kirsher struct ixgbe_bus_info bus; 3643dee1ad47SJeff Kirsher struct ixgbe_mbx_info mbx; 36449a900ecaSDon Skidmore const u32 *mvals; 3645dee1ad47SJeff Kirsher u16 device_id; 3646dee1ad47SJeff Kirsher u16 vendor_id; 3647dee1ad47SJeff Kirsher u16 subsystem_device_id; 3648dee1ad47SJeff Kirsher u16 subsystem_vendor_id; 3649dee1ad47SJeff Kirsher u8 revision_id; 3650dee1ad47SJeff Kirsher bool adapter_stopped; 3651dee1ad47SJeff Kirsher bool force_full_reset; 36528ef78adcSPeter P Waskiewicz Jr bool allow_unsupported_sfp; 36536b92b0baSJacob Keller bool wol_enabled; 3654aac9e053SDon Skidmore bool need_crosstalk_fix; 3655dee1ad47SJeff Kirsher }; 3656dee1ad47SJeff Kirsher 3657dee1ad47SJeff Kirsher struct ixgbe_info { 3658dee1ad47SJeff Kirsher enum ixgbe_mac_type mac; 3659dee1ad47SJeff Kirsher s32 (*get_invariants)(struct ixgbe_hw *); 366037689010SMark Rustad const struct ixgbe_mac_operations *mac_ops; 366137689010SMark Rustad const struct ixgbe_eeprom_operations *eeprom_ops; 366237689010SMark Rustad const struct ixgbe_phy_operations *phy_ops; 366337689010SMark Rustad const struct ixgbe_mbx_operations *mbx_ops; 3664b71f6c40SEmil Tantilov const struct ixgbe_link_operations *link_ops; 36659a900ecaSDon Skidmore const u32 *mvals; 3666dee1ad47SJeff Kirsher }; 3667dee1ad47SJeff Kirsher 36686ac74394SDon Skidmore #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) 36696ac74394SDon Skidmore #define IXGBE_FUSES0_300MHZ BIT(5) 3670b4f47a48SJacob Keller #define IXGBE_FUSES0_REV_MASK (3u << 6) 36716ac74394SDon Skidmore 3672d147329bSMark Rustad #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) 36732916500dSDon Skidmore #define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200) 3674d147329bSMark Rustad #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) 3675afdc71e4SMark Rustad #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) 367656573604SJeff Daly #define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238) 36772d40cd17SMark Rustad #define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248) 367856573604SJeff Daly #define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918) 3679200157c2SMark Rustad #define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0) 36802916500dSDon Skidmore #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C) 3681d147329bSMark Rustad #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634) 3682d147329bSMark Rustad #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638) 3683d147329bSMark Rustad #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00) 3684d147329bSMark Rustad #define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00) 3685470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054) 3686d147329bSMark Rustad #define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520) 3687d147329bSMark Rustad #define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00) 368856573604SJeff Daly #define IXGBE_KRM_FLX_TMRS_CTRL_ST31(P) ((P) ? 0x9180 : 0x5180) 36896a14ee0cSDon Skidmore 3690470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20) 3691470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR BIT(20) 3692470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20) 3693470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN BIT(25) 3694470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN BIT(26) 3695470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN BIT(27) 3696470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28) 3697470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M BIT(28) 3698470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28) 3699470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28) 3700470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28) 3701470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28) 3702470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28) 3703470739b5SDon Skidmore #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART BIT(31) 3704470739b5SDon Skidmore 3705b4f47a48SJacob Keller #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B BIT(9) 3706b4f47a48SJacob Keller #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS BIT(11) 37076a14ee0cSDon Skidmore 3708b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (7u << 8) 3709b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2u << 8) 3710b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4u << 8) 3711200157c2SMark Rustad #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN BIT(12) 3712200157c2SMark Rustad #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN BIT(13) 3713b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ BIT(14) 3714b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC BIT(15) 3715b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX BIT(16) 3716b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR BIT(18) 3717b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX BIT(24) 3718b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR BIT(26) 37192916500dSDon Skidmore #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE BIT(28) 3720b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE BIT(29) 3721b4f47a48SJacob Keller #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART BIT(31) 37226a14ee0cSDon Skidmore 3723b4f47a48SJacob Keller #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE BIT(28) 3724b4f47a48SJacob Keller #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE BIT(29) 3725afdc71e4SMark Rustad 37262d40cd17SMark Rustad #define IXGBE_KRM_AN_CNTL_8_LINEAR BIT(0) 37272d40cd17SMark Rustad #define IXGBE_KRM_AN_CNTL_8_LIMITING BIT(1) 37282d40cd17SMark Rustad 37292916500dSDon Skidmore #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE BIT(10) 37302916500dSDon Skidmore #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE BIT(11) 3731200157c2SMark Rustad #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D BIT(12) 3732200157c2SMark Rustad #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D BIT(19) 3733200157c2SMark Rustad 3734b4f47a48SJacob Keller #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN BIT(6) 3735b4f47a48SJacob Keller #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN BIT(15) 3736b4f47a48SJacob Keller #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN BIT(16) 37376a14ee0cSDon Skidmore 3738b4f47a48SJacob Keller #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL BIT(4) 3739b4f47a48SJacob Keller #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS BIT(2) 37406a14ee0cSDon Skidmore 3741b4f47a48SJacob Keller #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (3u << 16) 37426a14ee0cSDon Skidmore 3743b4f47a48SJacob Keller #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN BIT(1) 3744b4f47a48SJacob Keller #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN BIT(2) 3745b4f47a48SJacob Keller #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN BIT(3) 3746b4f47a48SJacob Keller #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN BIT(31) 37476a14ee0cSDon Skidmore 37486a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 37496a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 37506a14ee0cSDon Skidmore 37516a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0 37526a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF 37536a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18 37546a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \ 37556a14ee0cSDon Skidmore (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT) 37566a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20 37576a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \ 37586a14ee0cSDon Skidmore (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT) 37596a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 37606a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 37616a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 3762b4f47a48SJacob Keller #define IXGBE_SB_IOSF_CTRL_BUSY BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) 37636a14ee0cSDon Skidmore #define IXGBE_SB_IOSF_TARGET_KR_PHY 0 37646a14ee0cSDon Skidmore 3765c3dc4c09SDon Skidmore #define IXGBE_NW_MNG_IF_SEL 0x00011178 3766537cc5dfSMark Rustad #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT BIT(1) 37678e5c9c53SDon Skidmore #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M BIT(17) 37688e5c9c53SDon Skidmore #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M BIT(18) 37698e5c9c53SDon Skidmore #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G BIT(19) 37708e5c9c53SDon Skidmore #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G BIT(20) 37718e5c9c53SDon Skidmore #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G BIT(21) 377248301cf2STony Nguyen #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE BIT(25) 377348301cf2STony Nguyen #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE BIT(24) /* X552 only */ 3774537cc5dfSMark Rustad #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3 3775537cc5dfSMark Rustad #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \ 3776537cc5dfSMark Rustad (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT) 3777dee1ad47SJeff Kirsher #endif /* _IXGBE_TYPE_H_ */ 3778