1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
3 *
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
6 *
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
8 * integrated PHYs for the user facing ports, and an extension interface which
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
10 * RGMII. The switch is configured via the Realtek Simple Management Interface
11 * (SMI), which uses the MDIO/MDC lines.
12 *
13 * Below is a simplified block diagram of the chip and its relevant interfaces.
14 *
15 * .-----------------------------------.
16 * | |
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC |
21 * | |
22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension |
23 * | interface 1 GMAC 1 |
24 * | |
25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ |
26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ |
27 * | ~RTL8365MB ~~~ |
28 * | ~GXXXC TAIWAN~ |
29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ |
30 * | |
31 * Interrupt <----------> Link UP/DOWN events |
32 * controller | |
33 * '-----------------------------------'
34 *
35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the
36 * kernel. Netdevices are created for the user ports, as are PHY devices for
37 * their integrated PHYs. The device tree firmware should also specify the link
38 * partner of the extension port - either via a fixed-link or other phy-handle.
39 * See the device tree bindings for more detailed information. Note that the
40 * driver has only been tested with a fixed-link, but in principle it should not
41 * matter.
42 *
43 * NOTE: Currently, only the RGMII interface is implemented in this driver.
44 *
45 * The interrupt line is asserted on link UP/DOWN events. The driver creates a
46 * custom irqchip to handle this interrupt and demultiplex the events by reading
47 * the status registers via SMI. Interrupts are then propagated to the relevant
48 * PHY device.
49 *
50 * The EEPROM contains initial register values which the chip will read over I2C
51 * upon hardware reset. It is also possible to omit the EEPROM. In both cases,
52 * the driver will manually reprogram some registers using jam tables to reach
53 * an initial state defined by the vendor driver.
54 *
55 * This Linux driver is written based on an OS-agnostic vendor driver from
56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt
57 * source tree under the name rtl8367c. The vendor driver claims to support a
58 * number of similar switch controllers from Realtek, but the only hardware we
59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under
60 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of
61 * common hardware revision, there exist examples of chips with the suffix -VC
62 * which are explicitly not supported by the rtl8367c driver and which instead
63 * require the rtl8367d vendor driver. With all this uncertainty, the driver has
64 * been modestly named rtl8365mb. Future implementors may wish to rename things
65 * accordingly.
66 *
67 * In the same family of chips, some carry up to 8 user ports and up to 2
68 * extension ports. Where possible this driver tries to make things generic, but
69 * more work must be done to support these configurations. According to
70 * documentation from Realtek, the family should include the following chips:
71 *
72 * - RTL8363NB
73 * - RTL8363NB-VB
74 * - RTL8363SC
75 * - RTL8363SC-VB
76 * - RTL8364NB
77 * - RTL8364NB-VB
78 * - RTL8365MB-VC
79 * - RTL8366SC
80 * - RTL8367RB-VB
81 * - RTL8367SB
82 * - RTL8367S
83 * - RTL8370MB
84 * - RTL8310SR
85 *
86 * Some of the register logic for these additional chips has been skipped over
87 * while implementing this driver. It is therefore not possible to assume that
88 * things will work out-of-the-box for other chips, and a careful review of the
89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be
90 * one of the simpler chips.
91 */
92
93 #include <linux/bitfield.h>
94 #include <linux/bitops.h>
95 #include <linux/interrupt.h>
96 #include <linux/irqdomain.h>
97 #include <linux/mutex.h>
98 #include <linux/of_irq.h>
99 #include <linux/regmap.h>
100 #include <linux/if_bridge.h>
101 #include <linux/if_vlan.h>
102
103 #include "realtek.h"
104
105 /* Family-specific data and limits */
106 #define RTL8365MB_PHYADDRMAX 7
107 #define RTL8365MB_NUM_PHYREGS 32
108 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
109 #define RTL8365MB_MAX_NUM_PORTS 11
110 #define RTL8365MB_MAX_NUM_EXTINTS 3
111 #define RTL8365MB_LEARN_LIMIT_MAX 2112
112
113 /* Chip identification registers */
114 #define RTL8365MB_CHIP_ID_REG 0x1300
115
116 #define RTL8365MB_CHIP_VER_REG 0x1301
117
118 #define RTL8365MB_MAGIC_REG 0x13C2
119 #define RTL8365MB_MAGIC_VALUE 0x0249
120
121 /* Chip reset register */
122 #define RTL8365MB_CHIP_RESET_REG 0x1322
123 #define RTL8365MB_CHIP_RESET_SW_MASK 0x0002
124 #define RTL8365MB_CHIP_RESET_HW_MASK 0x0001
125
126 /* Interrupt polarity register */
127 #define RTL8365MB_INTR_POLARITY_REG 0x1100
128 #define RTL8365MB_INTR_POLARITY_MASK 0x0001
129 #define RTL8365MB_INTR_POLARITY_HIGH 0
130 #define RTL8365MB_INTR_POLARITY_LOW 1
131
132 /* Interrupt control/status register - enable/check specific interrupt types */
133 #define RTL8365MB_INTR_CTRL_REG 0x1101
134 #define RTL8365MB_INTR_STATUS_REG 0x1102
135 #define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000
136 #define RTL8365MB_INTR_SLIENT_START_MASK 0x0800
137 #define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200
138 #define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100
139 #define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080
140 #define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040
141 #define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020
142 #define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010
143 #define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008
144 #define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004
145 #define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002
146 #define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001
147 #define RTL8365MB_INTR_ALL_MASK \
148 (RTL8365MB_INTR_SLIENT_START_2_MASK | \
149 RTL8365MB_INTR_SLIENT_START_MASK | \
150 RTL8365MB_INTR_ACL_ACTION_MASK | \
151 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \
152 RTL8365MB_INTR_INTERRUPT_8051_MASK | \
153 RTL8365MB_INTR_LOOP_DETECTION_MASK | \
154 RTL8365MB_INTR_GREEN_TIMER_MASK | \
155 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \
156 RTL8365MB_INTR_SPEED_CHANGE_MASK | \
157 RTL8365MB_INTR_LEARN_OVER_MASK | \
158 RTL8365MB_INTR_METER_EXCEEDED_MASK | \
159 RTL8365MB_INTR_LINK_CHANGE_MASK)
160
161 /* Per-port interrupt type status registers */
162 #define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106
163 #define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF
164
165 #define RTL8365MB_PORT_LINKUP_IND_REG 0x1107
166 #define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF
167
168 /* PHY indirect access registers */
169 #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00
170 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002
171 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0
172 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1
173 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001
174 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1
175 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01
176 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02
177 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0)
178 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5)
179 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8)
180 #define RTL8365MB_PHY_BASE 0x2000
181 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03
182 #define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04
183
184 /* PHY OCP address prefix register */
185 #define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15
186 #define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0
187 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00
188
189 /* The PHY OCP addresses of PHY registers 0~31 start here */
190 #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400
191
192 /* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */
193 #define RTL8365MB_EXT_PORT_MODE_DISABLE 0
194 #define RTL8365MB_EXT_PORT_MODE_RGMII 1
195 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2
196 #define RTL8365MB_EXT_PORT_MODE_MII_PHY 3
197 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4
198 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5
199 #define RTL8365MB_EXT_PORT_MODE_GMII 6
200 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7
201 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8
202 #define RTL8365MB_EXT_PORT_MODE_SGMII 9
203 #define RTL8365MB_EXT_PORT_MODE_HSGMII 10
204 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11
205 #define RTL8365MB_EXT_PORT_MODE_1000X 12
206 #define RTL8365MB_EXT_PORT_MODE_100FX 13
207
208 /* External interface mode configuration registers 0~1 */
209 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT1 */
210 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */
211 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \
212 ((_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \
213 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \
214 0x0)
215 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \
216 (0xF << (((_extint) % 2)))
217 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \
218 (((_extint) % 2) * 4)
219
220 /* External interface RGMII TX/RX delay configuration registers 0~2 */
221 #define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */
222 #define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */
223 #define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */
224 #define RTL8365MB_EXT_RGMXF_REG(_extint) \
225 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \
226 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \
227 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \
228 0x0)
229 #define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007
230 #define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008
231
232 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */
233 #define RTL8365MB_PORT_SPEED_10M 0
234 #define RTL8365MB_PORT_SPEED_100M 1
235 #define RTL8365MB_PORT_SPEED_1000M 2
236
237 /* External interface force configuration registers 0~2 */
238 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */
239 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */
240 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */
241 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \
242 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \
243 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \
244 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \
245 0x0)
246 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000
247 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080
248 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040
249 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020
250 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010
251 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004
252 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003
253
254 /* CPU port mask register - controls which ports are treated as CPU ports */
255 #define RTL8365MB_CPU_PORT_MASK_REG 0x1219
256 #define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF
257
258 /* CPU control register */
259 #define RTL8365MB_CPU_CTRL_REG 0x121A
260 #define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400
261 #define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200
262 #define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080
263 #define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040
264 #define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038
265 #define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006
266 #define RTL8365MB_CPU_CTRL_EN_MASK 0x0001
267
268 /* Maximum packet length register */
269 #define RTL8365MB_CFG0_MAX_LEN_REG 0x088C
270 #define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF
271 #define RTL8365MB_CFG0_MAX_LEN_MAX 0x3FFF
272
273 /* Port learning limit registers */
274 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20
275 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \
276 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport))
277
278 /* Port isolation (forwarding mask) registers */
279 #define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2
280 #define RTL8365MB_PORT_ISOLATION_REG(_physport) \
281 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport))
282 #define RTL8365MB_PORT_ISOLATION_MASK 0x07FF
283
284 /* MSTP port state registers - indexed by tree instance */
285 #define RTL8365MB_MSTI_CTRL_BASE 0x0A00
286 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \
287 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3))
288 #define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1)
289 #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \
290 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))
291
292 /* MIB counter value registers */
293 #define RTL8365MB_MIB_COUNTER_BASE 0x1000
294 #define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x))
295
296 /* MIB counter address register */
297 #define RTL8365MB_MIB_ADDRESS_REG 0x1004
298 #define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C
299 #define RTL8365MB_MIB_ADDRESS(_p, _x) \
300 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2)
301
302 #define RTL8365MB_MIB_CTRL0_REG 0x1005
303 #define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002
304 #define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001
305
306 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed
307 * to block. On the other hand, accessing MIB counters absolutely requires us to
308 * block. The solution is thus to schedule work which polls the MIB counters
309 * asynchronously and updates some private data, which the callback can then
310 * fetch atomically. Three seconds should be a good enough polling interval.
311 */
312 #define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ)
313
314 enum rtl8365mb_mib_counter_index {
315 RTL8365MB_MIB_ifInOctets,
316 RTL8365MB_MIB_dot3StatsFCSErrors,
317 RTL8365MB_MIB_dot3StatsSymbolErrors,
318 RTL8365MB_MIB_dot3InPauseFrames,
319 RTL8365MB_MIB_dot3ControlInUnknownOpcodes,
320 RTL8365MB_MIB_etherStatsFragments,
321 RTL8365MB_MIB_etherStatsJabbers,
322 RTL8365MB_MIB_ifInUcastPkts,
323 RTL8365MB_MIB_etherStatsDropEvents,
324 RTL8365MB_MIB_ifInMulticastPkts,
325 RTL8365MB_MIB_ifInBroadcastPkts,
326 RTL8365MB_MIB_inMldChecksumError,
327 RTL8365MB_MIB_inIgmpChecksumError,
328 RTL8365MB_MIB_inMldSpecificQuery,
329 RTL8365MB_MIB_inMldGeneralQuery,
330 RTL8365MB_MIB_inIgmpSpecificQuery,
331 RTL8365MB_MIB_inIgmpGeneralQuery,
332 RTL8365MB_MIB_inMldLeaves,
333 RTL8365MB_MIB_inIgmpLeaves,
334 RTL8365MB_MIB_etherStatsOctets,
335 RTL8365MB_MIB_etherStatsUnderSizePkts,
336 RTL8365MB_MIB_etherOversizeStats,
337 RTL8365MB_MIB_etherStatsPkts64Octets,
338 RTL8365MB_MIB_etherStatsPkts65to127Octets,
339 RTL8365MB_MIB_etherStatsPkts128to255Octets,
340 RTL8365MB_MIB_etherStatsPkts256to511Octets,
341 RTL8365MB_MIB_etherStatsPkts512to1023Octets,
342 RTL8365MB_MIB_etherStatsPkts1024to1518Octets,
343 RTL8365MB_MIB_ifOutOctets,
344 RTL8365MB_MIB_dot3StatsSingleCollisionFrames,
345 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames,
346 RTL8365MB_MIB_dot3StatsDeferredTransmissions,
347 RTL8365MB_MIB_dot3StatsLateCollisions,
348 RTL8365MB_MIB_etherStatsCollisions,
349 RTL8365MB_MIB_dot3StatsExcessiveCollisions,
350 RTL8365MB_MIB_dot3OutPauseFrames,
351 RTL8365MB_MIB_ifOutDiscards,
352 RTL8365MB_MIB_dot1dTpPortInDiscards,
353 RTL8365MB_MIB_ifOutUcastPkts,
354 RTL8365MB_MIB_ifOutMulticastPkts,
355 RTL8365MB_MIB_ifOutBroadcastPkts,
356 RTL8365MB_MIB_outOampduPkts,
357 RTL8365MB_MIB_inOampduPkts,
358 RTL8365MB_MIB_inIgmpJoinsSuccess,
359 RTL8365MB_MIB_inIgmpJoinsFail,
360 RTL8365MB_MIB_inMldJoinsSuccess,
361 RTL8365MB_MIB_inMldJoinsFail,
362 RTL8365MB_MIB_inReportSuppressionDrop,
363 RTL8365MB_MIB_inLeaveSuppressionDrop,
364 RTL8365MB_MIB_outIgmpReports,
365 RTL8365MB_MIB_outIgmpLeaves,
366 RTL8365MB_MIB_outIgmpGeneralQuery,
367 RTL8365MB_MIB_outIgmpSpecificQuery,
368 RTL8365MB_MIB_outMldReports,
369 RTL8365MB_MIB_outMldLeaves,
370 RTL8365MB_MIB_outMldGeneralQuery,
371 RTL8365MB_MIB_outMldSpecificQuery,
372 RTL8365MB_MIB_inKnownMulticastPkts,
373 RTL8365MB_MIB_END,
374 };
375
376 struct rtl8365mb_mib_counter {
377 u32 offset;
378 u32 length;
379 const char *name;
380 };
381
382 #define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \
383 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name }
384
385 static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = {
386 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets),
387 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors),
388 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors),
389 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames),
390 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes),
391 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments),
392 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers),
393 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts),
394 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents),
395 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts),
396 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts),
397 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError),
398 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError),
399 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery),
400 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery),
401 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery),
402 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery),
403 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves),
404 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves),
405 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets),
406 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts),
407 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats),
408 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets),
409 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets),
410 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets),
411 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets),
412 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets),
413 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets),
414 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets),
415 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames),
416 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames),
417 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions),
418 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions),
419 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions),
420 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions),
421 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames),
422 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards),
423 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards),
424 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts),
425 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts),
426 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts),
427 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts),
428 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts),
429 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess),
430 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail),
431 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess),
432 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail),
433 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop),
434 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop),
435 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports),
436 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves),
437 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery),
438 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery),
439 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports),
440 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves),
441 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery),
442 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery),
443 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts),
444 };
445
446 static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END);
447
448 struct rtl8365mb_jam_tbl_entry {
449 u16 reg;
450 u16 val;
451 };
452
453 /* Lifted from the vendor driver sources */
454 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = {
455 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 },
456 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA },
457 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 },
458 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F },
459 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 },
460 { 0x13F0, 0x0000 },
461 };
462
463 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = {
464 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 },
465 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E },
466 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 },
467 { 0x1D32, 0x0002 },
468 };
469
470 enum rtl8365mb_phy_interface_mode {
471 RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0,
472 RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0),
473 RTL8365MB_PHY_INTERFACE_MODE_MII = BIT(1),
474 RTL8365MB_PHY_INTERFACE_MODE_TMII = BIT(2),
475 RTL8365MB_PHY_INTERFACE_MODE_RMII = BIT(3),
476 RTL8365MB_PHY_INTERFACE_MODE_RGMII = BIT(4),
477 RTL8365MB_PHY_INTERFACE_MODE_SGMII = BIT(5),
478 RTL8365MB_PHY_INTERFACE_MODE_HSGMII = BIT(6),
479 };
480
481 /**
482 * struct rtl8365mb_extint - external interface info
483 * @port: the port with an external interface
484 * @id: the external interface ID, which is either 0, 1, or 2
485 * @supported_interfaces: a bitmask of supported PHY interface modes
486 *
487 * Represents a mapping: port -> { id, supported_interfaces }. To be embedded
488 * in &struct rtl8365mb_chip_info for every port with an external interface.
489 */
490 struct rtl8365mb_extint {
491 int port;
492 int id;
493 unsigned int supported_interfaces;
494 };
495
496 /**
497 * struct rtl8365mb_chip_info - static chip-specific info
498 * @name: human-readable chip name
499 * @chip_id: chip identifier
500 * @chip_ver: chip silicon revision
501 * @extints: available external interfaces
502 * @jam_table: chip-specific initialization jam table
503 * @jam_size: size of the chip's jam table
504 *
505 * These data are specific to a given chip in the family of switches supported
506 * by this driver. When adding support for another chip in the family, a new
507 * chip info should be added to the rtl8365mb_chip_infos array.
508 */
509 struct rtl8365mb_chip_info {
510 const char *name;
511 u32 chip_id;
512 u32 chip_ver;
513 const struct rtl8365mb_extint extints[RTL8365MB_MAX_NUM_EXTINTS];
514 const struct rtl8365mb_jam_tbl_entry *jam_table;
515 size_t jam_size;
516 };
517
518 /* Chip info for each supported switch in the family */
519 #define PHY_INTF(_mode) (RTL8365MB_PHY_INTERFACE_MODE_ ## _mode)
520 static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {
521 {
522 .name = "RTL8365MB-VC",
523 .chip_id = 0x6367,
524 .chip_ver = 0x0040,
525 .extints = {
526 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
527 PHY_INTF(RMII) | PHY_INTF(RGMII) },
528 },
529 .jam_table = rtl8365mb_init_jam_8365mb_vc,
530 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
531 },
532 {
533 .name = "RTL8367S",
534 .chip_id = 0x6367,
535 .chip_ver = 0x00A0,
536 .extints = {
537 { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) },
538 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) |
539 PHY_INTF(RMII) | PHY_INTF(RGMII) },
540 },
541 .jam_table = rtl8365mb_init_jam_8365mb_vc,
542 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
543 },
544 {
545 .name = "RTL8367RB-VB",
546 .chip_id = 0x6367,
547 .chip_ver = 0x0020,
548 .extints = {
549 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
550 PHY_INTF(RMII) | PHY_INTF(RGMII) },
551 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) |
552 PHY_INTF(RMII) | PHY_INTF(RGMII) },
553 },
554 .jam_table = rtl8365mb_init_jam_8365mb_vc,
555 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
556 },
557 };
558
559 enum rtl8365mb_stp_state {
560 RTL8365MB_STP_STATE_DISABLED = 0,
561 RTL8365MB_STP_STATE_BLOCKING = 1,
562 RTL8365MB_STP_STATE_LEARNING = 2,
563 RTL8365MB_STP_STATE_FORWARDING = 3,
564 };
565
566 enum rtl8365mb_cpu_insert {
567 RTL8365MB_CPU_INSERT_TO_ALL = 0,
568 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1,
569 RTL8365MB_CPU_INSERT_TO_NONE = 2,
570 };
571
572 enum rtl8365mb_cpu_position {
573 RTL8365MB_CPU_POS_AFTER_SA = 0,
574 RTL8365MB_CPU_POS_BEFORE_CRC = 1,
575 };
576
577 enum rtl8365mb_cpu_format {
578 RTL8365MB_CPU_FORMAT_8BYTES = 0,
579 RTL8365MB_CPU_FORMAT_4BYTES = 1,
580 };
581
582 enum rtl8365mb_cpu_rxlen {
583 RTL8365MB_CPU_RXLEN_72BYTES = 0,
584 RTL8365MB_CPU_RXLEN_64BYTES = 1,
585 };
586
587 /**
588 * struct rtl8365mb_cpu - CPU port configuration
589 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames
590 * @mask: port mask of ports that parse should parse CPU tags
591 * @trap_port: forward trapped frames to this port
592 * @insert: CPU tag insertion mode in switch->CPU frames
593 * @position: position of CPU tag in frame
594 * @rx_length: minimum CPU RX length
595 * @format: CPU tag format
596 *
597 * Represents the CPU tagging and CPU port configuration of the switch. These
598 * settings are configurable at runtime.
599 */
600 struct rtl8365mb_cpu {
601 bool enable;
602 u32 mask;
603 u32 trap_port;
604 enum rtl8365mb_cpu_insert insert;
605 enum rtl8365mb_cpu_position position;
606 enum rtl8365mb_cpu_rxlen rx_length;
607 enum rtl8365mb_cpu_format format;
608 };
609
610 /**
611 * struct rtl8365mb_port - private per-port data
612 * @priv: pointer to parent realtek_priv data
613 * @index: DSA port index, same as dsa_port::index
614 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic
615 * access via rtl8365mb_get_stats64
616 * @stats_lock: protect the stats structure during read/update
617 * @mib_work: delayed work for polling MIB counters
618 */
619 struct rtl8365mb_port {
620 struct realtek_priv *priv;
621 unsigned int index;
622 struct rtnl_link_stats64 stats;
623 spinlock_t stats_lock;
624 struct delayed_work mib_work;
625 };
626
627 /**
628 * struct rtl8365mb - driver private data
629 * @priv: pointer to parent realtek_priv data
630 * @irq: registered IRQ or zero
631 * @chip_info: chip-specific info about the attached switch
632 * @cpu: CPU tagging and CPU port configuration for this chip
633 * @mib_lock: prevent concurrent reads of MIB counters
634 * @ports: per-port data
635 *
636 * Private data for this driver.
637 */
638 struct rtl8365mb {
639 struct realtek_priv *priv;
640 int irq;
641 const struct rtl8365mb_chip_info *chip_info;
642 struct rtl8365mb_cpu cpu;
643 struct mutex mib_lock;
644 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS];
645 };
646
rtl8365mb_phy_poll_busy(struct realtek_priv * priv)647 static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv)
648 {
649 u32 val;
650
651 return regmap_read_poll_timeout(priv->map_nolock,
652 RTL8365MB_INDIRECT_ACCESS_STATUS_REG,
653 val, !val, 10, 100);
654 }
655
rtl8365mb_phy_ocp_prepare(struct realtek_priv * priv,int phy,u32 ocp_addr)656 static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,
657 u32 ocp_addr)
658 {
659 u32 val;
660 int ret;
661
662 /* Set OCP prefix */
663 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr);
664 ret = regmap_update_bits(
665 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG,
666 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK,
667 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val));
668 if (ret)
669 return ret;
670
671 /* Set PHY register address */
672 val = RTL8365MB_PHY_BASE;
673 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy);
674 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK,
675 ocp_addr >> 1);
676 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK,
677 ocp_addr >> 6);
678 ret = regmap_write(priv->map_nolock,
679 RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val);
680 if (ret)
681 return ret;
682
683 return 0;
684 }
685
rtl8365mb_phy_ocp_read(struct realtek_priv * priv,int phy,u32 ocp_addr,u16 * data)686 static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,
687 u32 ocp_addr, u16 *data)
688 {
689 u32 val;
690 int ret;
691
692 mutex_lock(&priv->map_lock);
693
694 ret = rtl8365mb_phy_poll_busy(priv);
695 if (ret)
696 goto out;
697
698 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
699 if (ret)
700 goto out;
701
702 /* Execute read operation */
703 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
704 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
705 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
706 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ);
707 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
708 val);
709 if (ret)
710 goto out;
711
712 ret = rtl8365mb_phy_poll_busy(priv);
713 if (ret)
714 goto out;
715
716 /* Get PHY register data */
717 ret = regmap_read(priv->map_nolock,
718 RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val);
719 if (ret)
720 goto out;
721
722 *data = val & 0xFFFF;
723
724 out:
725 mutex_unlock(&priv->map_lock);
726
727 return ret;
728 }
729
rtl8365mb_phy_ocp_write(struct realtek_priv * priv,int phy,u32 ocp_addr,u16 data)730 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy,
731 u32 ocp_addr, u16 data)
732 {
733 u32 val;
734 int ret;
735
736 mutex_lock(&priv->map_lock);
737
738 ret = rtl8365mb_phy_poll_busy(priv);
739 if (ret)
740 goto out;
741
742 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
743 if (ret)
744 goto out;
745
746 /* Set PHY register data */
747 ret = regmap_write(priv->map_nolock,
748 RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data);
749 if (ret)
750 goto out;
751
752 /* Execute write operation */
753 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
754 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
755 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
756 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE);
757 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
758 val);
759 if (ret)
760 goto out;
761
762 ret = rtl8365mb_phy_poll_busy(priv);
763 if (ret)
764 goto out;
765
766 out:
767 mutex_unlock(&priv->map_lock);
768
769 return 0;
770 }
771
rtl8365mb_phy_read(struct realtek_priv * priv,int phy,int regnum)772 static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum)
773 {
774 u32 ocp_addr;
775 u16 val;
776 int ret;
777
778 if (phy > RTL8365MB_PHYADDRMAX)
779 return -EINVAL;
780
781 if (regnum > RTL8365MB_PHYREGMAX)
782 return -EINVAL;
783
784 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;
785
786 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val);
787 if (ret) {
788 dev_err(priv->dev,
789 "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy,
790 regnum, ocp_addr, ret);
791 return ret;
792 }
793
794 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n",
795 phy, regnum, ocp_addr, val);
796
797 return val;
798 }
799
rtl8365mb_phy_write(struct realtek_priv * priv,int phy,int regnum,u16 val)800 static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum,
801 u16 val)
802 {
803 u32 ocp_addr;
804 int ret;
805
806 if (phy > RTL8365MB_PHYADDRMAX)
807 return -EINVAL;
808
809 if (regnum > RTL8365MB_PHYREGMAX)
810 return -EINVAL;
811
812 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;
813
814 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val);
815 if (ret) {
816 dev_err(priv->dev,
817 "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy,
818 regnum, ocp_addr, ret);
819 return ret;
820 }
821
822 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n",
823 phy, regnum, ocp_addr, val);
824
825 return 0;
826 }
827
rtl8365mb_dsa_phy_read(struct dsa_switch * ds,int phy,int regnum)828 static int rtl8365mb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum)
829 {
830 return rtl8365mb_phy_read(ds->priv, phy, regnum);
831 }
832
rtl8365mb_dsa_phy_write(struct dsa_switch * ds,int phy,int regnum,u16 val)833 static int rtl8365mb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum,
834 u16 val)
835 {
836 return rtl8365mb_phy_write(ds->priv, phy, regnum, val);
837 }
838
839 static const struct rtl8365mb_extint *
rtl8365mb_get_port_extint(struct realtek_priv * priv,int port)840 rtl8365mb_get_port_extint(struct realtek_priv *priv, int port)
841 {
842 struct rtl8365mb *mb = priv->chip_data;
843 int i;
844
845 for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) {
846 const struct rtl8365mb_extint *extint =
847 &mb->chip_info->extints[i];
848
849 if (!extint->supported_interfaces)
850 continue;
851
852 if (extint->port == port)
853 return extint;
854 }
855
856 return NULL;
857 }
858
859 static enum dsa_tag_protocol
rtl8365mb_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)860 rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port,
861 enum dsa_tag_protocol mp)
862 {
863 struct realtek_priv *priv = ds->priv;
864 struct rtl8365mb_cpu *cpu;
865 struct rtl8365mb *mb;
866
867 mb = priv->chip_data;
868 cpu = &mb->cpu;
869
870 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC)
871 return DSA_TAG_PROTO_RTL8_4T;
872
873 return DSA_TAG_PROTO_RTL8_4;
874 }
875
rtl8365mb_ext_config_rgmii(struct realtek_priv * priv,int port,phy_interface_t interface)876 static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port,
877 phy_interface_t interface)
878 {
879 const struct rtl8365mb_extint *extint =
880 rtl8365mb_get_port_extint(priv, port);
881 struct device_node *dn;
882 struct dsa_port *dp;
883 int tx_delay = 0;
884 int rx_delay = 0;
885 u32 val;
886 int ret;
887
888 if (!extint)
889 return -ENODEV;
890
891 dp = dsa_to_port(priv->ds, port);
892 dn = dp->dn;
893
894 /* Set the RGMII TX/RX delay
895 *
896 * The Realtek vendor driver indicates the following possible
897 * configuration settings:
898 *
899 * TX delay:
900 * 0 = no delay, 1 = 2 ns delay
901 * RX delay:
902 * 0 = no delay, 7 = maximum delay
903 * Each step is approximately 0.3 ns, so the maximum delay is about
904 * 2.1 ns.
905 *
906 * The vendor driver also states that this must be configured *before*
907 * forcing the external interface into a particular mode, which is done
908 * in the rtl8365mb_phylink_mac_link_{up,down} functions.
909 *
910 * Only configure an RGMII TX (resp. RX) delay if the
911 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is
912 * specified. We ignore the detail of the RGMII interface mode
913 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only
914 * property.
915 */
916 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) {
917 val = val / 1000; /* convert to ns */
918
919 if (val == 0 || val == 2)
920 tx_delay = val / 2;
921 else
922 dev_warn(priv->dev,
923 "RGMII TX delay must be 0 or 2 ns\n");
924 }
925
926 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) {
927 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */
928
929 if (val <= 7)
930 rx_delay = val;
931 else
932 dev_warn(priv->dev,
933 "RGMII RX delay must be 0 to 2.1 ns\n");
934 }
935
936 ret = regmap_update_bits(
937 priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id),
938 RTL8365MB_EXT_RGMXF_TXDELAY_MASK |
939 RTL8365MB_EXT_RGMXF_RXDELAY_MASK,
940 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) |
941 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay));
942 if (ret)
943 return ret;
944
945 ret = regmap_update_bits(
946 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id),
947 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id),
948 RTL8365MB_EXT_PORT_MODE_RGMII
949 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(
950 extint->id));
951 if (ret)
952 return ret;
953
954 return 0;
955 }
956
rtl8365mb_ext_config_forcemode(struct realtek_priv * priv,int port,bool link,int speed,int duplex,bool tx_pause,bool rx_pause)957 static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port,
958 bool link, int speed, int duplex,
959 bool tx_pause, bool rx_pause)
960 {
961 const struct rtl8365mb_extint *extint =
962 rtl8365mb_get_port_extint(priv, port);
963 u32 r_tx_pause;
964 u32 r_rx_pause;
965 u32 r_duplex;
966 u32 r_speed;
967 u32 r_link;
968 int val;
969 int ret;
970
971 if (!extint)
972 return -ENODEV;
973
974 if (link) {
975 /* Force the link up with the desired configuration */
976 r_link = 1;
977 r_rx_pause = rx_pause ? 1 : 0;
978 r_tx_pause = tx_pause ? 1 : 0;
979
980 if (speed == SPEED_1000) {
981 r_speed = RTL8365MB_PORT_SPEED_1000M;
982 } else if (speed == SPEED_100) {
983 r_speed = RTL8365MB_PORT_SPEED_100M;
984 } else if (speed == SPEED_10) {
985 r_speed = RTL8365MB_PORT_SPEED_10M;
986 } else {
987 dev_err(priv->dev, "unsupported port speed %s\n",
988 phy_speed_to_str(speed));
989 return -EINVAL;
990 }
991
992 if (duplex == DUPLEX_FULL) {
993 r_duplex = 1;
994 } else if (duplex == DUPLEX_HALF) {
995 r_duplex = 0;
996 } else {
997 dev_err(priv->dev, "unsupported duplex %s\n",
998 phy_duplex_to_str(duplex));
999 return -EINVAL;
1000 }
1001 } else {
1002 /* Force the link down and reset any programmed configuration */
1003 r_link = 0;
1004 r_tx_pause = 0;
1005 r_rx_pause = 0;
1006 r_speed = 0;
1007 r_duplex = 0;
1008 }
1009
1010 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) |
1011 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK,
1012 r_tx_pause) |
1013 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK,
1014 r_rx_pause) |
1015 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) |
1016 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK,
1017 r_duplex) |
1018 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed);
1019 ret = regmap_write(priv->map,
1020 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id),
1021 val);
1022 if (ret)
1023 return ret;
1024
1025 return 0;
1026 }
1027
rtl8365mb_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1028 static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port,
1029 struct phylink_config *config)
1030 {
1031 const struct rtl8365mb_extint *extint =
1032 rtl8365mb_get_port_extint(ds->priv, port);
1033
1034 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
1035 MAC_10 | MAC_100 | MAC_1000FD;
1036
1037 if (!extint) {
1038 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1039 config->supported_interfaces);
1040
1041 /* GMII is the default interface mode for phylib, so
1042 * we have to support it for ports with integrated PHY.
1043 */
1044 __set_bit(PHY_INTERFACE_MODE_GMII,
1045 config->supported_interfaces);
1046 return;
1047 }
1048
1049 /* Populate according to the modes supported by _this driver_,
1050 * not necessarily the modes supported by the hardware, some of
1051 * which remain unimplemented.
1052 */
1053
1054 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII)
1055 phy_interface_set_rgmii(config->supported_interfaces);
1056 }
1057
rtl8365mb_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)1058 static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port,
1059 unsigned int mode,
1060 const struct phylink_link_state *state)
1061 {
1062 struct realtek_priv *priv = ds->priv;
1063 int ret;
1064
1065 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) {
1066 dev_err(priv->dev,
1067 "port %d supports only conventional PHY or fixed-link\n",
1068 port);
1069 return;
1070 }
1071
1072 if (phy_interface_mode_is_rgmii(state->interface)) {
1073 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface);
1074 if (ret)
1075 dev_err(priv->dev,
1076 "failed to configure RGMII mode on port %d: %d\n",
1077 port, ret);
1078 return;
1079 }
1080
1081 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also
1082 * supports
1083 */
1084 }
1085
rtl8365mb_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)1086 static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port,
1087 unsigned int mode,
1088 phy_interface_t interface)
1089 {
1090 struct realtek_priv *priv = ds->priv;
1091 struct rtl8365mb_port *p;
1092 struct rtl8365mb *mb;
1093 int ret;
1094
1095 mb = priv->chip_data;
1096 p = &mb->ports[port];
1097 cancel_delayed_work_sync(&p->mib_work);
1098
1099 if (phy_interface_mode_is_rgmii(interface)) {
1100 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0,
1101 false, false);
1102 if (ret)
1103 dev_err(priv->dev,
1104 "failed to reset forced mode on port %d: %d\n",
1105 port, ret);
1106
1107 return;
1108 }
1109 }
1110
rtl8365mb_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)1111 static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port,
1112 unsigned int mode,
1113 phy_interface_t interface,
1114 struct phy_device *phydev, int speed,
1115 int duplex, bool tx_pause,
1116 bool rx_pause)
1117 {
1118 struct realtek_priv *priv = ds->priv;
1119 struct rtl8365mb_port *p;
1120 struct rtl8365mb *mb;
1121 int ret;
1122
1123 mb = priv->chip_data;
1124 p = &mb->ports[port];
1125 schedule_delayed_work(&p->mib_work, 0);
1126
1127 if (phy_interface_mode_is_rgmii(interface)) {
1128 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed,
1129 duplex, tx_pause,
1130 rx_pause);
1131 if (ret)
1132 dev_err(priv->dev,
1133 "failed to force mode on port %d: %d\n", port,
1134 ret);
1135
1136 return;
1137 }
1138 }
1139
rtl8365mb_port_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1140 static int rtl8365mb_port_change_mtu(struct dsa_switch *ds, int port,
1141 int new_mtu)
1142 {
1143 struct realtek_priv *priv = ds->priv;
1144 int frame_size;
1145
1146 /* When a new MTU is set, DSA always sets the CPU port's MTU to the
1147 * largest MTU of the slave ports. Because the switch only has a global
1148 * RX length register, only allowing CPU port here is enough.
1149 */
1150 if (!dsa_is_cpu_port(ds, port))
1151 return 0;
1152
1153 frame_size = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
1154
1155 dev_dbg(priv->dev, "changing mtu to %d (frame size: %d)\n",
1156 new_mtu, frame_size);
1157
1158 return regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG,
1159 RTL8365MB_CFG0_MAX_LEN_MASK,
1160 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK,
1161 frame_size));
1162 }
1163
rtl8365mb_port_max_mtu(struct dsa_switch * ds,int port)1164 static int rtl8365mb_port_max_mtu(struct dsa_switch *ds, int port)
1165 {
1166 return RTL8365MB_CFG0_MAX_LEN_MAX - VLAN_ETH_HLEN - ETH_FCS_LEN;
1167 }
1168
rtl8365mb_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1169 static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port,
1170 u8 state)
1171 {
1172 struct realtek_priv *priv = ds->priv;
1173 enum rtl8365mb_stp_state val;
1174 int msti = 0;
1175
1176 switch (state) {
1177 case BR_STATE_DISABLED:
1178 val = RTL8365MB_STP_STATE_DISABLED;
1179 break;
1180 case BR_STATE_BLOCKING:
1181 case BR_STATE_LISTENING:
1182 val = RTL8365MB_STP_STATE_BLOCKING;
1183 break;
1184 case BR_STATE_LEARNING:
1185 val = RTL8365MB_STP_STATE_LEARNING;
1186 break;
1187 case BR_STATE_FORWARDING:
1188 val = RTL8365MB_STP_STATE_FORWARDING;
1189 break;
1190 default:
1191 dev_err(priv->dev, "invalid STP state: %u\n", state);
1192 return;
1193 }
1194
1195 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port),
1196 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port),
1197 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port));
1198 }
1199
rtl8365mb_port_set_learning(struct realtek_priv * priv,int port,bool enable)1200 static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,
1201 bool enable)
1202 {
1203 /* Enable/disable learning by limiting the number of L2 addresses the
1204 * port can learn. Realtek documentation states that a limit of zero
1205 * disables learning. When enabling learning, set it to the chip's
1206 * maximum.
1207 */
1208 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port),
1209 enable ? RTL8365MB_LEARN_LIMIT_MAX : 0);
1210 }
1211
rtl8365mb_port_set_isolation(struct realtek_priv * priv,int port,u32 mask)1212 static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port,
1213 u32 mask)
1214 {
1215 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);
1216 }
1217
rtl8365mb_mib_counter_read(struct realtek_priv * priv,int port,u32 offset,u32 length,u64 * mibvalue)1218 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port,
1219 u32 offset, u32 length, u64 *mibvalue)
1220 {
1221 u64 tmpvalue = 0;
1222 u32 val;
1223 int ret;
1224 int i;
1225
1226 /* The MIB address is an SRAM address. We request a particular address
1227 * and then poll the control register before reading the value from some
1228 * counter registers.
1229 */
1230 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG,
1231 RTL8365MB_MIB_ADDRESS(port, offset));
1232 if (ret)
1233 return ret;
1234
1235 /* Poll for completion */
1236 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val,
1237 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK),
1238 10, 100);
1239 if (ret)
1240 return ret;
1241
1242 /* Presumably this indicates a MIB counter read failure */
1243 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK)
1244 return -EIO;
1245
1246 /* There are four MIB counter registers each holding a 16 bit word of a
1247 * MIB counter. Depending on the offset, we should read from the upper
1248 * two or lower two registers. In case the MIB counter is 4 words, we
1249 * read from all four registers.
1250 */
1251 if (length == 4)
1252 offset = 3;
1253 else
1254 offset = (offset + 1) % 4;
1255
1256 /* Read the MIB counter 16 bits at a time */
1257 for (i = 0; i < length; i++) {
1258 ret = regmap_read(priv->map,
1259 RTL8365MB_MIB_COUNTER_REG(offset - i), &val);
1260 if (ret)
1261 return ret;
1262
1263 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF);
1264 }
1265
1266 /* Only commit the result if no error occurred */
1267 *mibvalue = tmpvalue;
1268
1269 return 0;
1270 }
1271
rtl8365mb_get_ethtool_stats(struct dsa_switch * ds,int port,u64 * data)1272 static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
1273 {
1274 struct realtek_priv *priv = ds->priv;
1275 struct rtl8365mb *mb;
1276 int ret;
1277 int i;
1278
1279 mb = priv->chip_data;
1280
1281 mutex_lock(&mb->mib_lock);
1282 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1283 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1284
1285 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
1286 mib->length, &data[i]);
1287 if (ret) {
1288 dev_err(priv->dev,
1289 "failed to read port %d counters: %d\n", port,
1290 ret);
1291 break;
1292 }
1293 }
1294 mutex_unlock(&mb->mib_lock);
1295 }
1296
rtl8365mb_get_strings(struct dsa_switch * ds,int port,u32 stringset,u8 * data)1297 static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data)
1298 {
1299 int i;
1300
1301 if (stringset != ETH_SS_STATS)
1302 return;
1303
1304 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1305 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1306
1307 strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN);
1308 }
1309 }
1310
rtl8365mb_get_sset_count(struct dsa_switch * ds,int port,int sset)1311 static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset)
1312 {
1313 if (sset != ETH_SS_STATS)
1314 return -EOPNOTSUPP;
1315
1316 return RTL8365MB_MIB_END;
1317 }
1318
rtl8365mb_get_phy_stats(struct dsa_switch * ds,int port,struct ethtool_eth_phy_stats * phy_stats)1319 static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port,
1320 struct ethtool_eth_phy_stats *phy_stats)
1321 {
1322 struct realtek_priv *priv = ds->priv;
1323 struct rtl8365mb_mib_counter *mib;
1324 struct rtl8365mb *mb;
1325
1326 mb = priv->chip_data;
1327 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors];
1328
1329 mutex_lock(&mb->mib_lock);
1330 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,
1331 &phy_stats->SymbolErrorDuringCarrier);
1332 mutex_unlock(&mb->mib_lock);
1333 }
1334
rtl8365mb_get_mac_stats(struct dsa_switch * ds,int port,struct ethtool_eth_mac_stats * mac_stats)1335 static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port,
1336 struct ethtool_eth_mac_stats *mac_stats)
1337 {
1338 u64 cnt[RTL8365MB_MIB_END] = {
1339 [RTL8365MB_MIB_ifOutOctets] = 1,
1340 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1341 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1342 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1343 [RTL8365MB_MIB_dot3OutPauseFrames] = 1,
1344 [RTL8365MB_MIB_ifOutDiscards] = 1,
1345 [RTL8365MB_MIB_ifInOctets] = 1,
1346 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1347 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1348 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1349 [RTL8365MB_MIB_dot3InPauseFrames] = 1,
1350 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1,
1351 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1,
1352 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1353 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1,
1354 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1355 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1,
1356
1357 };
1358 struct realtek_priv *priv = ds->priv;
1359 struct rtl8365mb *mb;
1360 int ret;
1361 int i;
1362
1363 mb = priv->chip_data;
1364
1365 mutex_lock(&mb->mib_lock);
1366 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1367 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1368
1369 /* Only fetch required MIB counters (marked = 1 above) */
1370 if (!cnt[i])
1371 continue;
1372
1373 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
1374 mib->length, &cnt[i]);
1375 if (ret)
1376 break;
1377 }
1378 mutex_unlock(&mb->mib_lock);
1379
1380 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into
1381 * IEEE 802.3 Managed Objects. This is not always completely faithful,
1382 * but we try out best. See RFC 3635 for a detailed treatment of the
1383 * subject.
1384 */
1385
1386 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1387 cnt[RTL8365MB_MIB_ifOutMulticastPkts] +
1388 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] +
1389 cnt[RTL8365MB_MIB_dot3OutPauseFrames] -
1390 cnt[RTL8365MB_MIB_ifOutDiscards];
1391 mac_stats->SingleCollisionFrames =
1392 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames];
1393 mac_stats->MultipleCollisionFrames =
1394 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames];
1395 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1396 cnt[RTL8365MB_MIB_ifInMulticastPkts] +
1397 cnt[RTL8365MB_MIB_ifInBroadcastPkts] +
1398 cnt[RTL8365MB_MIB_dot3InPauseFrames];
1399 mac_stats->FrameCheckSequenceErrors =
1400 cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1401 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] -
1402 18 * mac_stats->FramesTransmittedOK;
1403 mac_stats->FramesWithDeferredXmissions =
1404 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions];
1405 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1406 mac_stats->FramesAbortedDueToXSColls =
1407 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions];
1408 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] -
1409 18 * mac_stats->FramesReceivedOK;
1410 mac_stats->MulticastFramesXmittedOK =
1411 cnt[RTL8365MB_MIB_ifOutMulticastPkts];
1412 mac_stats->BroadcastFramesXmittedOK =
1413 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];
1414 mac_stats->MulticastFramesReceivedOK =
1415 cnt[RTL8365MB_MIB_ifInMulticastPkts];
1416 mac_stats->BroadcastFramesReceivedOK =
1417 cnt[RTL8365MB_MIB_ifInBroadcastPkts];
1418 }
1419
rtl8365mb_get_ctrl_stats(struct dsa_switch * ds,int port,struct ethtool_eth_ctrl_stats * ctrl_stats)1420 static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port,
1421 struct ethtool_eth_ctrl_stats *ctrl_stats)
1422 {
1423 struct realtek_priv *priv = ds->priv;
1424 struct rtl8365mb_mib_counter *mib;
1425 struct rtl8365mb *mb;
1426
1427 mb = priv->chip_data;
1428 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes];
1429
1430 mutex_lock(&mb->mib_lock);
1431 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,
1432 &ctrl_stats->UnsupportedOpcodesReceived);
1433 mutex_unlock(&mb->mib_lock);
1434 }
1435
rtl8365mb_stats_update(struct realtek_priv * priv,int port)1436 static void rtl8365mb_stats_update(struct realtek_priv *priv, int port)
1437 {
1438 u64 cnt[RTL8365MB_MIB_END] = {
1439 [RTL8365MB_MIB_ifOutOctets] = 1,
1440 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1441 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1442 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1443 [RTL8365MB_MIB_ifOutDiscards] = 1,
1444 [RTL8365MB_MIB_ifInOctets] = 1,
1445 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1446 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1447 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1448 [RTL8365MB_MIB_etherStatsDropEvents] = 1,
1449 [RTL8365MB_MIB_etherStatsCollisions] = 1,
1450 [RTL8365MB_MIB_etherStatsFragments] = 1,
1451 [RTL8365MB_MIB_etherStatsJabbers] = 1,
1452 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1453 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1454 };
1455 struct rtl8365mb *mb = priv->chip_data;
1456 struct rtnl_link_stats64 *stats;
1457 int ret;
1458 int i;
1459
1460 stats = &mb->ports[port].stats;
1461
1462 mutex_lock(&mb->mib_lock);
1463 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1464 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i];
1465
1466 /* Only fetch required MIB counters (marked = 1 above) */
1467 if (!cnt[i])
1468 continue;
1469
1470 ret = rtl8365mb_mib_counter_read(priv, port, c->offset,
1471 c->length, &cnt[i]);
1472 if (ret)
1473 break;
1474 }
1475 mutex_unlock(&mb->mib_lock);
1476
1477 /* Don't update statistics if there was an error reading the counters */
1478 if (ret)
1479 return;
1480
1481 spin_lock(&mb->ports[port].stats_lock);
1482
1483 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1484 cnt[RTL8365MB_MIB_ifInMulticastPkts] +
1485 cnt[RTL8365MB_MIB_ifInBroadcastPkts] -
1486 cnt[RTL8365MB_MIB_ifOutDiscards];
1487
1488 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1489 cnt[RTL8365MB_MIB_ifOutMulticastPkts] +
1490 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];
1491
1492 /* if{In,Out}Octets includes FCS - remove it */
1493 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets;
1494 stats->tx_bytes =
1495 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets;
1496
1497 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents];
1498 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards];
1499
1500 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts];
1501 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions];
1502
1503 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] +
1504 cnt[RTL8365MB_MIB_etherStatsJabbers];
1505 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1506 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors;
1507
1508 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards];
1509 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1510 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors;
1511
1512 spin_unlock(&mb->ports[port].stats_lock);
1513 }
1514
rtl8365mb_stats_poll(struct work_struct * work)1515 static void rtl8365mb_stats_poll(struct work_struct *work)
1516 {
1517 struct rtl8365mb_port *p = container_of(to_delayed_work(work),
1518 struct rtl8365mb_port,
1519 mib_work);
1520 struct realtek_priv *priv = p->priv;
1521
1522 rtl8365mb_stats_update(priv, p->index);
1523
1524 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES);
1525 }
1526
rtl8365mb_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)1527 static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port,
1528 struct rtnl_link_stats64 *s)
1529 {
1530 struct realtek_priv *priv = ds->priv;
1531 struct rtl8365mb_port *p;
1532 struct rtl8365mb *mb;
1533
1534 mb = priv->chip_data;
1535 p = &mb->ports[port];
1536
1537 spin_lock(&p->stats_lock);
1538 memcpy(s, &p->stats, sizeof(*s));
1539 spin_unlock(&p->stats_lock);
1540 }
1541
rtl8365mb_stats_setup(struct realtek_priv * priv)1542 static void rtl8365mb_stats_setup(struct realtek_priv *priv)
1543 {
1544 struct rtl8365mb *mb = priv->chip_data;
1545 int i;
1546
1547 /* Per-chip global mutex to protect MIB counter access, since doing
1548 * so requires accessing a series of registers in a particular order.
1549 */
1550 mutex_init(&mb->mib_lock);
1551
1552 for (i = 0; i < priv->num_ports; i++) {
1553 struct rtl8365mb_port *p = &mb->ports[i];
1554
1555 if (dsa_is_unused_port(priv->ds, i))
1556 continue;
1557
1558 /* Per-port spinlock to protect the stats64 data */
1559 spin_lock_init(&p->stats_lock);
1560
1561 /* This work polls the MIB counters and keeps the stats64 data
1562 * up-to-date.
1563 */
1564 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll);
1565 }
1566 }
1567
rtl8365mb_stats_teardown(struct realtek_priv * priv)1568 static void rtl8365mb_stats_teardown(struct realtek_priv *priv)
1569 {
1570 struct rtl8365mb *mb = priv->chip_data;
1571 int i;
1572
1573 for (i = 0; i < priv->num_ports; i++) {
1574 struct rtl8365mb_port *p = &mb->ports[i];
1575
1576 if (dsa_is_unused_port(priv->ds, i))
1577 continue;
1578
1579 cancel_delayed_work_sync(&p->mib_work);
1580 }
1581 }
1582
rtl8365mb_get_and_clear_status_reg(struct realtek_priv * priv,u32 reg,u32 * val)1583 static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg,
1584 u32 *val)
1585 {
1586 int ret;
1587
1588 ret = regmap_read(priv->map, reg, val);
1589 if (ret)
1590 return ret;
1591
1592 return regmap_write(priv->map, reg, *val);
1593 }
1594
rtl8365mb_irq(int irq,void * data)1595 static irqreturn_t rtl8365mb_irq(int irq, void *data)
1596 {
1597 struct realtek_priv *priv = data;
1598 unsigned long line_changes = 0;
1599 u32 stat;
1600 int line;
1601 int ret;
1602
1603 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG,
1604 &stat);
1605 if (ret)
1606 goto out_error;
1607
1608 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) {
1609 u32 linkdown_ind;
1610 u32 linkup_ind;
1611 u32 val;
1612
1613 ret = rtl8365mb_get_and_clear_status_reg(
1614 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val);
1615 if (ret)
1616 goto out_error;
1617
1618 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val);
1619
1620 ret = rtl8365mb_get_and_clear_status_reg(
1621 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val);
1622 if (ret)
1623 goto out_error;
1624
1625 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val);
1626
1627 line_changes = linkup_ind | linkdown_ind;
1628 }
1629
1630 if (!line_changes)
1631 goto out_none;
1632
1633 for_each_set_bit(line, &line_changes, priv->num_ports) {
1634 int child_irq = irq_find_mapping(priv->irqdomain, line);
1635
1636 handle_nested_irq(child_irq);
1637 }
1638
1639 return IRQ_HANDLED;
1640
1641 out_error:
1642 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret);
1643
1644 out_none:
1645 return IRQ_NONE;
1646 }
1647
1648 static struct irq_chip rtl8365mb_irq_chip = {
1649 .name = "rtl8365mb",
1650 /* The hardware doesn't support masking IRQs on a per-port basis */
1651 };
1652
rtl8365mb_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)1653 static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq,
1654 irq_hw_number_t hwirq)
1655 {
1656 irq_set_chip_data(irq, domain->host_data);
1657 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq);
1658 irq_set_nested_thread(irq, 1);
1659 irq_set_noprobe(irq);
1660
1661 return 0;
1662 }
1663
rtl8365mb_irq_unmap(struct irq_domain * d,unsigned int irq)1664 static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq)
1665 {
1666 irq_set_nested_thread(irq, 0);
1667 irq_set_chip_and_handler(irq, NULL, NULL);
1668 irq_set_chip_data(irq, NULL);
1669 }
1670
1671 static const struct irq_domain_ops rtl8365mb_irqdomain_ops = {
1672 .map = rtl8365mb_irq_map,
1673 .unmap = rtl8365mb_irq_unmap,
1674 .xlate = irq_domain_xlate_onecell,
1675 };
1676
rtl8365mb_set_irq_enable(struct realtek_priv * priv,bool enable)1677 static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable)
1678 {
1679 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG,
1680 RTL8365MB_INTR_LINK_CHANGE_MASK,
1681 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK,
1682 enable ? 1 : 0));
1683 }
1684
rtl8365mb_irq_enable(struct realtek_priv * priv)1685 static int rtl8365mb_irq_enable(struct realtek_priv *priv)
1686 {
1687 return rtl8365mb_set_irq_enable(priv, true);
1688 }
1689
rtl8365mb_irq_disable(struct realtek_priv * priv)1690 static int rtl8365mb_irq_disable(struct realtek_priv *priv)
1691 {
1692 return rtl8365mb_set_irq_enable(priv, false);
1693 }
1694
rtl8365mb_irq_setup(struct realtek_priv * priv)1695 static int rtl8365mb_irq_setup(struct realtek_priv *priv)
1696 {
1697 struct rtl8365mb *mb = priv->chip_data;
1698 struct device_node *intc;
1699 u32 irq_trig;
1700 int virq;
1701 int irq;
1702 u32 val;
1703 int ret;
1704 int i;
1705
1706 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
1707 if (!intc) {
1708 dev_err(priv->dev, "missing child interrupt-controller node\n");
1709 return -EINVAL;
1710 }
1711
1712 /* rtl8365mb IRQs cascade off this one */
1713 irq = of_irq_get(intc, 0);
1714 if (irq <= 0) {
1715 if (irq != -EPROBE_DEFER)
1716 dev_err(priv->dev, "failed to get parent irq: %d\n",
1717 irq);
1718 ret = irq ? irq : -EINVAL;
1719 goto out_put_node;
1720 }
1721
1722 priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports,
1723 &rtl8365mb_irqdomain_ops, priv);
1724 if (!priv->irqdomain) {
1725 dev_err(priv->dev, "failed to add irq domain\n");
1726 ret = -ENOMEM;
1727 goto out_put_node;
1728 }
1729
1730 for (i = 0; i < priv->num_ports; i++) {
1731 virq = irq_create_mapping(priv->irqdomain, i);
1732 if (!virq) {
1733 dev_err(priv->dev,
1734 "failed to create irq domain mapping\n");
1735 ret = -EINVAL;
1736 goto out_remove_irqdomain;
1737 }
1738
1739 irq_set_parent(virq, irq);
1740 }
1741
1742 /* Configure chip interrupt signal polarity */
1743 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1744 switch (irq_trig) {
1745 case IRQF_TRIGGER_RISING:
1746 case IRQF_TRIGGER_HIGH:
1747 val = RTL8365MB_INTR_POLARITY_HIGH;
1748 break;
1749 case IRQF_TRIGGER_FALLING:
1750 case IRQF_TRIGGER_LOW:
1751 val = RTL8365MB_INTR_POLARITY_LOW;
1752 break;
1753 default:
1754 dev_err(priv->dev, "unsupported irq trigger type %u\n",
1755 irq_trig);
1756 ret = -EINVAL;
1757 goto out_remove_irqdomain;
1758 }
1759
1760 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG,
1761 RTL8365MB_INTR_POLARITY_MASK,
1762 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val));
1763 if (ret)
1764 goto out_remove_irqdomain;
1765
1766 /* Disable the interrupt in case the chip has it enabled on reset */
1767 ret = rtl8365mb_irq_disable(priv);
1768 if (ret)
1769 goto out_remove_irqdomain;
1770
1771 /* Clear the interrupt status register */
1772 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG,
1773 RTL8365MB_INTR_ALL_MASK);
1774 if (ret)
1775 goto out_remove_irqdomain;
1776
1777 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT,
1778 "rtl8365mb", priv);
1779 if (ret) {
1780 dev_err(priv->dev, "failed to request irq: %d\n", ret);
1781 goto out_remove_irqdomain;
1782 }
1783
1784 /* Store the irq so that we know to free it during teardown */
1785 mb->irq = irq;
1786
1787 ret = rtl8365mb_irq_enable(priv);
1788 if (ret)
1789 goto out_free_irq;
1790
1791 of_node_put(intc);
1792
1793 return 0;
1794
1795 out_free_irq:
1796 free_irq(mb->irq, priv);
1797 mb->irq = 0;
1798
1799 out_remove_irqdomain:
1800 for (i = 0; i < priv->num_ports; i++) {
1801 virq = irq_find_mapping(priv->irqdomain, i);
1802 irq_dispose_mapping(virq);
1803 }
1804
1805 irq_domain_remove(priv->irqdomain);
1806 priv->irqdomain = NULL;
1807
1808 out_put_node:
1809 of_node_put(intc);
1810
1811 return ret;
1812 }
1813
rtl8365mb_irq_teardown(struct realtek_priv * priv)1814 static void rtl8365mb_irq_teardown(struct realtek_priv *priv)
1815 {
1816 struct rtl8365mb *mb = priv->chip_data;
1817 int virq;
1818 int i;
1819
1820 if (mb->irq) {
1821 free_irq(mb->irq, priv);
1822 mb->irq = 0;
1823 }
1824
1825 if (priv->irqdomain) {
1826 for (i = 0; i < priv->num_ports; i++) {
1827 virq = irq_find_mapping(priv->irqdomain, i);
1828 irq_dispose_mapping(virq);
1829 }
1830
1831 irq_domain_remove(priv->irqdomain);
1832 priv->irqdomain = NULL;
1833 }
1834 }
1835
rtl8365mb_cpu_config(struct realtek_priv * priv)1836 static int rtl8365mb_cpu_config(struct realtek_priv *priv)
1837 {
1838 struct rtl8365mb *mb = priv->chip_data;
1839 struct rtl8365mb_cpu *cpu = &mb->cpu;
1840 u32 val;
1841 int ret;
1842
1843 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG,
1844 RTL8365MB_CPU_PORT_MASK_MASK,
1845 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK,
1846 cpu->mask));
1847 if (ret)
1848 return ret;
1849
1850 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) |
1851 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) |
1852 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) |
1853 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) |
1854 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) |
1855 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) |
1856 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK,
1857 cpu->trap_port >> 3 & 0x1);
1858 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val);
1859 if (ret)
1860 return ret;
1861
1862 return 0;
1863 }
1864
rtl8365mb_change_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)1865 static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds,
1866 enum dsa_tag_protocol proto)
1867 {
1868 struct realtek_priv *priv = ds->priv;
1869 struct rtl8365mb_cpu *cpu;
1870 struct rtl8365mb *mb;
1871
1872 mb = priv->chip_data;
1873 cpu = &mb->cpu;
1874
1875 switch (proto) {
1876 case DSA_TAG_PROTO_RTL8_4:
1877 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;
1878 cpu->position = RTL8365MB_CPU_POS_AFTER_SA;
1879 break;
1880 case DSA_TAG_PROTO_RTL8_4T:
1881 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;
1882 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC;
1883 break;
1884 /* The switch also supports a 4-byte format, similar to rtl4a but with
1885 * the same 0x04 8-bit version and probably 8-bit port source/dest.
1886 * There is no public doc about it. Not supported yet and it will probably
1887 * never be.
1888 */
1889 default:
1890 return -EPROTONOSUPPORT;
1891 }
1892
1893 return rtl8365mb_cpu_config(priv);
1894 }
1895
rtl8365mb_switch_init(struct realtek_priv * priv)1896 static int rtl8365mb_switch_init(struct realtek_priv *priv)
1897 {
1898 struct rtl8365mb *mb = priv->chip_data;
1899 const struct rtl8365mb_chip_info *ci;
1900 int ret;
1901 int i;
1902
1903 ci = mb->chip_info;
1904
1905 /* Do any chip-specific init jam before getting to the common stuff */
1906 if (ci->jam_table) {
1907 for (i = 0; i < ci->jam_size; i++) {
1908 ret = regmap_write(priv->map, ci->jam_table[i].reg,
1909 ci->jam_table[i].val);
1910 if (ret)
1911 return ret;
1912 }
1913 }
1914
1915 /* Common init jam */
1916 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) {
1917 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg,
1918 rtl8365mb_init_jam_common[i].val);
1919 if (ret)
1920 return ret;
1921 }
1922
1923 return 0;
1924 }
1925
rtl8365mb_reset_chip(struct realtek_priv * priv)1926 static int rtl8365mb_reset_chip(struct realtek_priv *priv)
1927 {
1928 u32 val;
1929
1930 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG,
1931 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1));
1932
1933 /* Realtek documentation says the chip needs 1 second to reset. Sleep
1934 * for 100 ms before accessing any registers to prevent ACK timeouts.
1935 */
1936 msleep(100);
1937 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val,
1938 !(val & RTL8365MB_CHIP_RESET_HW_MASK),
1939 20000, 1e6);
1940 }
1941
rtl8365mb_setup(struct dsa_switch * ds)1942 static int rtl8365mb_setup(struct dsa_switch *ds)
1943 {
1944 struct realtek_priv *priv = ds->priv;
1945 struct rtl8365mb_cpu *cpu;
1946 struct dsa_port *cpu_dp;
1947 struct rtl8365mb *mb;
1948 int ret;
1949 int i;
1950
1951 mb = priv->chip_data;
1952 cpu = &mb->cpu;
1953
1954 ret = rtl8365mb_reset_chip(priv);
1955 if (ret) {
1956 dev_err(priv->dev, "failed to reset chip: %d\n", ret);
1957 goto out_error;
1958 }
1959
1960 /* Configure switch to vendor-defined initial state */
1961 ret = rtl8365mb_switch_init(priv);
1962 if (ret) {
1963 dev_err(priv->dev, "failed to initialize switch: %d\n", ret);
1964 goto out_error;
1965 }
1966
1967 /* Set up cascading IRQs */
1968 ret = rtl8365mb_irq_setup(priv);
1969 if (ret == -EPROBE_DEFER)
1970 return ret;
1971 else if (ret)
1972 dev_info(priv->dev, "no interrupt support\n");
1973
1974 /* Configure CPU tagging */
1975 dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) {
1976 cpu->mask |= BIT(cpu_dp->index);
1977
1978 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS)
1979 cpu->trap_port = cpu_dp->index;
1980 }
1981 cpu->enable = cpu->mask > 0;
1982 ret = rtl8365mb_cpu_config(priv);
1983 if (ret)
1984 goto out_teardown_irq;
1985
1986 /* Configure ports */
1987 for (i = 0; i < priv->num_ports; i++) {
1988 struct rtl8365mb_port *p = &mb->ports[i];
1989
1990 if (dsa_is_unused_port(priv->ds, i))
1991 continue;
1992
1993 /* Forward only to the CPU */
1994 ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask);
1995 if (ret)
1996 goto out_teardown_irq;
1997
1998 /* Disable learning */
1999 ret = rtl8365mb_port_set_learning(priv, i, false);
2000 if (ret)
2001 goto out_teardown_irq;
2002
2003 /* Set the initial STP state of all ports to DISABLED, otherwise
2004 * ports will still forward frames to the CPU despite being
2005 * administratively down by default.
2006 */
2007 rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED);
2008
2009 /* Set up per-port private data */
2010 p->priv = priv;
2011 p->index = i;
2012 }
2013
2014 ret = rtl8365mb_port_change_mtu(ds, cpu->trap_port, ETH_DATA_LEN);
2015 if (ret)
2016 goto out_teardown_irq;
2017
2018 if (priv->setup_interface) {
2019 ret = priv->setup_interface(ds);
2020 if (ret) {
2021 dev_err(priv->dev, "could not set up MDIO bus\n");
2022 goto out_teardown_irq;
2023 }
2024 }
2025
2026 /* Start statistics counter polling */
2027 rtl8365mb_stats_setup(priv);
2028
2029 return 0;
2030
2031 out_teardown_irq:
2032 rtl8365mb_irq_teardown(priv);
2033
2034 out_error:
2035 return ret;
2036 }
2037
rtl8365mb_teardown(struct dsa_switch * ds)2038 static void rtl8365mb_teardown(struct dsa_switch *ds)
2039 {
2040 struct realtek_priv *priv = ds->priv;
2041
2042 rtl8365mb_stats_teardown(priv);
2043 rtl8365mb_irq_teardown(priv);
2044 }
2045
rtl8365mb_get_chip_id_and_ver(struct regmap * map,u32 * id,u32 * ver)2046 static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver)
2047 {
2048 int ret;
2049
2050 /* For some reason we have to write a magic value to an arbitrary
2051 * register whenever accessing the chip ID/version registers.
2052 */
2053 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE);
2054 if (ret)
2055 return ret;
2056
2057 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id);
2058 if (ret)
2059 return ret;
2060
2061 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver);
2062 if (ret)
2063 return ret;
2064
2065 /* Reset magic register */
2066 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0);
2067 if (ret)
2068 return ret;
2069
2070 return 0;
2071 }
2072
rtl8365mb_detect(struct realtek_priv * priv)2073 static int rtl8365mb_detect(struct realtek_priv *priv)
2074 {
2075 struct rtl8365mb *mb = priv->chip_data;
2076 u32 chip_id;
2077 u32 chip_ver;
2078 int ret;
2079 int i;
2080
2081 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver);
2082 if (ret) {
2083 dev_err(priv->dev, "failed to read chip id and version: %d\n",
2084 ret);
2085 return ret;
2086 }
2087
2088 for (i = 0; i < ARRAY_SIZE(rtl8365mb_chip_infos); i++) {
2089 const struct rtl8365mb_chip_info *ci = &rtl8365mb_chip_infos[i];
2090
2091 if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) {
2092 mb->chip_info = ci;
2093 break;
2094 }
2095 }
2096
2097 if (!mb->chip_info) {
2098 dev_err(priv->dev,
2099 "unrecognized switch (id=0x%04x, ver=0x%04x)", chip_id,
2100 chip_ver);
2101 return -ENODEV;
2102 }
2103
2104 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name);
2105
2106 priv->num_ports = RTL8365MB_MAX_NUM_PORTS;
2107 mb->priv = priv;
2108 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;
2109 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
2110 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
2111 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;
2112 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;
2113
2114 return 0;
2115 }
2116
2117 static const struct dsa_switch_ops rtl8365mb_switch_ops_smi = {
2118 .get_tag_protocol = rtl8365mb_get_tag_protocol,
2119 .change_tag_protocol = rtl8365mb_change_tag_protocol,
2120 .setup = rtl8365mb_setup,
2121 .teardown = rtl8365mb_teardown,
2122 .phylink_get_caps = rtl8365mb_phylink_get_caps,
2123 .phylink_mac_config = rtl8365mb_phylink_mac_config,
2124 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down,
2125 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up,
2126 .port_stp_state_set = rtl8365mb_port_stp_state_set,
2127 .get_strings = rtl8365mb_get_strings,
2128 .get_ethtool_stats = rtl8365mb_get_ethtool_stats,
2129 .get_sset_count = rtl8365mb_get_sset_count,
2130 .get_eth_phy_stats = rtl8365mb_get_phy_stats,
2131 .get_eth_mac_stats = rtl8365mb_get_mac_stats,
2132 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats,
2133 .get_stats64 = rtl8365mb_get_stats64,
2134 .port_change_mtu = rtl8365mb_port_change_mtu,
2135 .port_max_mtu = rtl8365mb_port_max_mtu,
2136 };
2137
2138 static const struct dsa_switch_ops rtl8365mb_switch_ops_mdio = {
2139 .get_tag_protocol = rtl8365mb_get_tag_protocol,
2140 .change_tag_protocol = rtl8365mb_change_tag_protocol,
2141 .setup = rtl8365mb_setup,
2142 .teardown = rtl8365mb_teardown,
2143 .phylink_get_caps = rtl8365mb_phylink_get_caps,
2144 .phylink_mac_config = rtl8365mb_phylink_mac_config,
2145 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down,
2146 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up,
2147 .phy_read = rtl8365mb_dsa_phy_read,
2148 .phy_write = rtl8365mb_dsa_phy_write,
2149 .port_stp_state_set = rtl8365mb_port_stp_state_set,
2150 .get_strings = rtl8365mb_get_strings,
2151 .get_ethtool_stats = rtl8365mb_get_ethtool_stats,
2152 .get_sset_count = rtl8365mb_get_sset_count,
2153 .get_eth_phy_stats = rtl8365mb_get_phy_stats,
2154 .get_eth_mac_stats = rtl8365mb_get_mac_stats,
2155 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats,
2156 .get_stats64 = rtl8365mb_get_stats64,
2157 .port_change_mtu = rtl8365mb_port_change_mtu,
2158 .port_max_mtu = rtl8365mb_port_max_mtu,
2159 };
2160
2161 static const struct realtek_ops rtl8365mb_ops = {
2162 .detect = rtl8365mb_detect,
2163 .phy_read = rtl8365mb_phy_read,
2164 .phy_write = rtl8365mb_phy_write,
2165 };
2166
2167 const struct realtek_variant rtl8365mb_variant = {
2168 .ds_ops_smi = &rtl8365mb_switch_ops_smi,
2169 .ds_ops_mdio = &rtl8365mb_switch_ops_mdio,
2170 .ops = &rtl8365mb_ops,
2171 .clk_delay = 10,
2172 .cmd_read = 0xb9,
2173 .cmd_write = 0xb8,
2174 .chip_data_sz = sizeof(struct rtl8365mb),
2175 };
2176 EXPORT_SYMBOL_GPL(rtl8365mb_variant);
2177
2178 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>");
2179 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch");
2180 MODULE_LICENSE("GPL");
2181