1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 251dce24bSJeff Kirsher /* Copyright(c) 1999 - 2006 Intel Corporation. */ 3dee1ad47SJeff Kirsher 4dee1ad47SJeff Kirsher /* e1000_hw.h 5dee1ad47SJeff Kirsher * Structures, enums, and macros for the MAC 6dee1ad47SJeff Kirsher */ 7dee1ad47SJeff Kirsher 8dee1ad47SJeff Kirsher #ifndef _E1000_HW_H_ 9dee1ad47SJeff Kirsher #define _E1000_HW_H_ 10dee1ad47SJeff Kirsher 11dee1ad47SJeff Kirsher #include "e1000_osdep.h" 12dee1ad47SJeff Kirsher 13dee1ad47SJeff Kirsher 14dee1ad47SJeff Kirsher /* Forward declarations of structures used by the shared code */ 15dee1ad47SJeff Kirsher struct e1000_hw; 16dee1ad47SJeff Kirsher struct e1000_hw_stats; 17dee1ad47SJeff Kirsher 18dee1ad47SJeff Kirsher /* Enumerated types specific to the e1000 hardware */ 19dee1ad47SJeff Kirsher /* Media Access Controllers */ 20dee1ad47SJeff Kirsher typedef enum { 21dee1ad47SJeff Kirsher e1000_undefined = 0, 22dee1ad47SJeff Kirsher e1000_82542_rev2_0, 23dee1ad47SJeff Kirsher e1000_82542_rev2_1, 24dee1ad47SJeff Kirsher e1000_82543, 25dee1ad47SJeff Kirsher e1000_82544, 26dee1ad47SJeff Kirsher e1000_82540, 27dee1ad47SJeff Kirsher e1000_82545, 28dee1ad47SJeff Kirsher e1000_82545_rev_3, 29dee1ad47SJeff Kirsher e1000_82546, 30dee1ad47SJeff Kirsher e1000_ce4100, 31dee1ad47SJeff Kirsher e1000_82546_rev_3, 32dee1ad47SJeff Kirsher e1000_82541, 33dee1ad47SJeff Kirsher e1000_82541_rev_2, 34dee1ad47SJeff Kirsher e1000_82547, 35dee1ad47SJeff Kirsher e1000_82547_rev_2, 36dee1ad47SJeff Kirsher e1000_num_macs 37dee1ad47SJeff Kirsher } e1000_mac_type; 38dee1ad47SJeff Kirsher 39dee1ad47SJeff Kirsher typedef enum { 40dee1ad47SJeff Kirsher e1000_eeprom_uninitialized = 0, 41dee1ad47SJeff Kirsher e1000_eeprom_spi, 42dee1ad47SJeff Kirsher e1000_eeprom_microwire, 43dee1ad47SJeff Kirsher e1000_eeprom_flash, 44dee1ad47SJeff Kirsher e1000_eeprom_none, /* No NVM support */ 45dee1ad47SJeff Kirsher e1000_num_eeprom_types 46dee1ad47SJeff Kirsher } e1000_eeprom_type; 47dee1ad47SJeff Kirsher 48dee1ad47SJeff Kirsher /* Media Types */ 49dee1ad47SJeff Kirsher typedef enum { 50dee1ad47SJeff Kirsher e1000_media_type_copper = 0, 51dee1ad47SJeff Kirsher e1000_media_type_fiber = 1, 52dee1ad47SJeff Kirsher e1000_media_type_internal_serdes = 2, 53dee1ad47SJeff Kirsher e1000_num_media_types 54dee1ad47SJeff Kirsher } e1000_media_type; 55dee1ad47SJeff Kirsher 56dee1ad47SJeff Kirsher typedef enum { 57dee1ad47SJeff Kirsher e1000_10_half = 0, 58dee1ad47SJeff Kirsher e1000_10_full = 1, 59dee1ad47SJeff Kirsher e1000_100_half = 2, 60dee1ad47SJeff Kirsher e1000_100_full = 3 61dee1ad47SJeff Kirsher } e1000_speed_duplex_type; 62dee1ad47SJeff Kirsher 63dee1ad47SJeff Kirsher /* Flow Control Settings */ 64dee1ad47SJeff Kirsher typedef enum { 65dee1ad47SJeff Kirsher E1000_FC_NONE = 0, 66dee1ad47SJeff Kirsher E1000_FC_RX_PAUSE = 1, 67dee1ad47SJeff Kirsher E1000_FC_TX_PAUSE = 2, 68dee1ad47SJeff Kirsher E1000_FC_FULL = 3, 69dee1ad47SJeff Kirsher E1000_FC_DEFAULT = 0xFF 70dee1ad47SJeff Kirsher } e1000_fc_type; 71dee1ad47SJeff Kirsher 72dee1ad47SJeff Kirsher struct e1000_shadow_ram { 73dee1ad47SJeff Kirsher u16 eeprom_word; 74dee1ad47SJeff Kirsher bool modified; 75dee1ad47SJeff Kirsher }; 76dee1ad47SJeff Kirsher 77dee1ad47SJeff Kirsher /* PCI bus types */ 78dee1ad47SJeff Kirsher typedef enum { 79dee1ad47SJeff Kirsher e1000_bus_type_unknown = 0, 80dee1ad47SJeff Kirsher e1000_bus_type_pci, 81dee1ad47SJeff Kirsher e1000_bus_type_pcix, 82dee1ad47SJeff Kirsher e1000_bus_type_reserved 83dee1ad47SJeff Kirsher } e1000_bus_type; 84dee1ad47SJeff Kirsher 85dee1ad47SJeff Kirsher /* PCI bus speeds */ 86dee1ad47SJeff Kirsher typedef enum { 87dee1ad47SJeff Kirsher e1000_bus_speed_unknown = 0, 88dee1ad47SJeff Kirsher e1000_bus_speed_33, 89dee1ad47SJeff Kirsher e1000_bus_speed_66, 90dee1ad47SJeff Kirsher e1000_bus_speed_100, 91dee1ad47SJeff Kirsher e1000_bus_speed_120, 92dee1ad47SJeff Kirsher e1000_bus_speed_133, 93dee1ad47SJeff Kirsher e1000_bus_speed_reserved 94dee1ad47SJeff Kirsher } e1000_bus_speed; 95dee1ad47SJeff Kirsher 96dee1ad47SJeff Kirsher /* PCI bus widths */ 97dee1ad47SJeff Kirsher typedef enum { 98dee1ad47SJeff Kirsher e1000_bus_width_unknown = 0, 99dee1ad47SJeff Kirsher e1000_bus_width_32, 100dee1ad47SJeff Kirsher e1000_bus_width_64, 101dee1ad47SJeff Kirsher e1000_bus_width_reserved 102dee1ad47SJeff Kirsher } e1000_bus_width; 103dee1ad47SJeff Kirsher 104dee1ad47SJeff Kirsher /* PHY status info structure and supporting enums */ 105dee1ad47SJeff Kirsher typedef enum { 106dee1ad47SJeff Kirsher e1000_cable_length_50 = 0, 107dee1ad47SJeff Kirsher e1000_cable_length_50_80, 108dee1ad47SJeff Kirsher e1000_cable_length_80_110, 109dee1ad47SJeff Kirsher e1000_cable_length_110_140, 110dee1ad47SJeff Kirsher e1000_cable_length_140, 111dee1ad47SJeff Kirsher e1000_cable_length_undefined = 0xFF 112dee1ad47SJeff Kirsher } e1000_cable_length; 113dee1ad47SJeff Kirsher 114dee1ad47SJeff Kirsher typedef enum { 115dee1ad47SJeff Kirsher e1000_gg_cable_length_60 = 0, 116dee1ad47SJeff Kirsher e1000_gg_cable_length_60_115 = 1, 117dee1ad47SJeff Kirsher e1000_gg_cable_length_115_150 = 2, 118dee1ad47SJeff Kirsher e1000_gg_cable_length_150 = 4 119dee1ad47SJeff Kirsher } e1000_gg_cable_length; 120dee1ad47SJeff Kirsher 121dee1ad47SJeff Kirsher typedef enum { 122dee1ad47SJeff Kirsher e1000_igp_cable_length_10 = 10, 123dee1ad47SJeff Kirsher e1000_igp_cable_length_20 = 20, 124dee1ad47SJeff Kirsher e1000_igp_cable_length_30 = 30, 125dee1ad47SJeff Kirsher e1000_igp_cable_length_40 = 40, 126dee1ad47SJeff Kirsher e1000_igp_cable_length_50 = 50, 127dee1ad47SJeff Kirsher e1000_igp_cable_length_60 = 60, 128dee1ad47SJeff Kirsher e1000_igp_cable_length_70 = 70, 129dee1ad47SJeff Kirsher e1000_igp_cable_length_80 = 80, 130dee1ad47SJeff Kirsher e1000_igp_cable_length_90 = 90, 131dee1ad47SJeff Kirsher e1000_igp_cable_length_100 = 100, 132dee1ad47SJeff Kirsher e1000_igp_cable_length_110 = 110, 133dee1ad47SJeff Kirsher e1000_igp_cable_length_115 = 115, 134dee1ad47SJeff Kirsher e1000_igp_cable_length_120 = 120, 135dee1ad47SJeff Kirsher e1000_igp_cable_length_130 = 130, 136dee1ad47SJeff Kirsher e1000_igp_cable_length_140 = 140, 137dee1ad47SJeff Kirsher e1000_igp_cable_length_150 = 150, 138dee1ad47SJeff Kirsher e1000_igp_cable_length_160 = 160, 139dee1ad47SJeff Kirsher e1000_igp_cable_length_170 = 170, 140dee1ad47SJeff Kirsher e1000_igp_cable_length_180 = 180 141dee1ad47SJeff Kirsher } e1000_igp_cable_length; 142dee1ad47SJeff Kirsher 143dee1ad47SJeff Kirsher typedef enum { 144dee1ad47SJeff Kirsher e1000_10bt_ext_dist_enable_normal = 0, 145dee1ad47SJeff Kirsher e1000_10bt_ext_dist_enable_lower, 146dee1ad47SJeff Kirsher e1000_10bt_ext_dist_enable_undefined = 0xFF 147dee1ad47SJeff Kirsher } e1000_10bt_ext_dist_enable; 148dee1ad47SJeff Kirsher 149dee1ad47SJeff Kirsher typedef enum { 150dee1ad47SJeff Kirsher e1000_rev_polarity_normal = 0, 151dee1ad47SJeff Kirsher e1000_rev_polarity_reversed, 152dee1ad47SJeff Kirsher e1000_rev_polarity_undefined = 0xFF 153dee1ad47SJeff Kirsher } e1000_rev_polarity; 154dee1ad47SJeff Kirsher 155dee1ad47SJeff Kirsher typedef enum { 156dee1ad47SJeff Kirsher e1000_downshift_normal = 0, 157dee1ad47SJeff Kirsher e1000_downshift_activated, 158dee1ad47SJeff Kirsher e1000_downshift_undefined = 0xFF 159dee1ad47SJeff Kirsher } e1000_downshift; 160dee1ad47SJeff Kirsher 161dee1ad47SJeff Kirsher typedef enum { 162dee1ad47SJeff Kirsher e1000_smart_speed_default = 0, 163dee1ad47SJeff Kirsher e1000_smart_speed_on, 164dee1ad47SJeff Kirsher e1000_smart_speed_off 165dee1ad47SJeff Kirsher } e1000_smart_speed; 166dee1ad47SJeff Kirsher 167dee1ad47SJeff Kirsher typedef enum { 168dee1ad47SJeff Kirsher e1000_polarity_reversal_enabled = 0, 169dee1ad47SJeff Kirsher e1000_polarity_reversal_disabled, 170dee1ad47SJeff Kirsher e1000_polarity_reversal_undefined = 0xFF 171dee1ad47SJeff Kirsher } e1000_polarity_reversal; 172dee1ad47SJeff Kirsher 173dee1ad47SJeff Kirsher typedef enum { 174dee1ad47SJeff Kirsher e1000_auto_x_mode_manual_mdi = 0, 175dee1ad47SJeff Kirsher e1000_auto_x_mode_manual_mdix, 176dee1ad47SJeff Kirsher e1000_auto_x_mode_auto1, 177dee1ad47SJeff Kirsher e1000_auto_x_mode_auto2, 178dee1ad47SJeff Kirsher e1000_auto_x_mode_undefined = 0xFF 179dee1ad47SJeff Kirsher } e1000_auto_x_mode; 180dee1ad47SJeff Kirsher 181dee1ad47SJeff Kirsher typedef enum { 182dee1ad47SJeff Kirsher e1000_1000t_rx_status_not_ok = 0, 183dee1ad47SJeff Kirsher e1000_1000t_rx_status_ok, 184dee1ad47SJeff Kirsher e1000_1000t_rx_status_undefined = 0xFF 185dee1ad47SJeff Kirsher } e1000_1000t_rx_status; 186dee1ad47SJeff Kirsher 187dee1ad47SJeff Kirsher typedef enum { 188dee1ad47SJeff Kirsher e1000_phy_m88 = 0, 189dee1ad47SJeff Kirsher e1000_phy_igp, 190dee1ad47SJeff Kirsher e1000_phy_8211, 191dee1ad47SJeff Kirsher e1000_phy_8201, 192dee1ad47SJeff Kirsher e1000_phy_undefined = 0xFF 193dee1ad47SJeff Kirsher } e1000_phy_type; 194dee1ad47SJeff Kirsher 195dee1ad47SJeff Kirsher typedef enum { 196dee1ad47SJeff Kirsher e1000_ms_hw_default = 0, 197dee1ad47SJeff Kirsher e1000_ms_force_master, 198dee1ad47SJeff Kirsher e1000_ms_force_slave, 199dee1ad47SJeff Kirsher e1000_ms_auto 200dee1ad47SJeff Kirsher } e1000_ms_type; 201dee1ad47SJeff Kirsher 202dee1ad47SJeff Kirsher typedef enum { 203dee1ad47SJeff Kirsher e1000_ffe_config_enabled = 0, 204dee1ad47SJeff Kirsher e1000_ffe_config_active, 205dee1ad47SJeff Kirsher e1000_ffe_config_blocked 206dee1ad47SJeff Kirsher } e1000_ffe_config; 207dee1ad47SJeff Kirsher 208dee1ad47SJeff Kirsher typedef enum { 209dee1ad47SJeff Kirsher e1000_dsp_config_disabled = 0, 210dee1ad47SJeff Kirsher e1000_dsp_config_enabled, 211dee1ad47SJeff Kirsher e1000_dsp_config_activated, 212dee1ad47SJeff Kirsher e1000_dsp_config_undefined = 0xFF 213dee1ad47SJeff Kirsher } e1000_dsp_config; 214dee1ad47SJeff Kirsher 215dee1ad47SJeff Kirsher struct e1000_phy_info { 216dee1ad47SJeff Kirsher e1000_cable_length cable_length; 217dee1ad47SJeff Kirsher e1000_10bt_ext_dist_enable extended_10bt_distance; 218dee1ad47SJeff Kirsher e1000_rev_polarity cable_polarity; 219dee1ad47SJeff Kirsher e1000_downshift downshift; 220dee1ad47SJeff Kirsher e1000_polarity_reversal polarity_correction; 221dee1ad47SJeff Kirsher e1000_auto_x_mode mdix_mode; 222dee1ad47SJeff Kirsher e1000_1000t_rx_status local_rx; 223dee1ad47SJeff Kirsher e1000_1000t_rx_status remote_rx; 224dee1ad47SJeff Kirsher }; 225dee1ad47SJeff Kirsher 226dee1ad47SJeff Kirsher struct e1000_phy_stats { 227dee1ad47SJeff Kirsher u32 idle_errors; 228dee1ad47SJeff Kirsher u32 receive_errors; 229dee1ad47SJeff Kirsher }; 230dee1ad47SJeff Kirsher 231dee1ad47SJeff Kirsher struct e1000_eeprom_info { 232dee1ad47SJeff Kirsher e1000_eeprom_type type; 233dee1ad47SJeff Kirsher u16 word_size; 234dee1ad47SJeff Kirsher u16 opcode_bits; 235dee1ad47SJeff Kirsher u16 address_bits; 236dee1ad47SJeff Kirsher u16 delay_usec; 237dee1ad47SJeff Kirsher u16 page_size; 238dee1ad47SJeff Kirsher }; 239dee1ad47SJeff Kirsher 240dee1ad47SJeff Kirsher /* Flex ASF Information */ 241dee1ad47SJeff Kirsher #define E1000_HOST_IF_MAX_SIZE 2048 242dee1ad47SJeff Kirsher 243dee1ad47SJeff Kirsher typedef enum { 244dee1ad47SJeff Kirsher e1000_byte_align = 0, 245dee1ad47SJeff Kirsher e1000_word_align = 1, 246dee1ad47SJeff Kirsher e1000_dword_align = 2 247dee1ad47SJeff Kirsher } e1000_align_type; 248dee1ad47SJeff Kirsher 249dee1ad47SJeff Kirsher /* Error Codes */ 250dee1ad47SJeff Kirsher #define E1000_SUCCESS 0 251dee1ad47SJeff Kirsher #define E1000_ERR_EEPROM 1 252dee1ad47SJeff Kirsher #define E1000_ERR_PHY 2 253dee1ad47SJeff Kirsher #define E1000_ERR_CONFIG 3 254dee1ad47SJeff Kirsher #define E1000_ERR_PARAM 4 255dee1ad47SJeff Kirsher #define E1000_ERR_MAC_TYPE 5 256dee1ad47SJeff Kirsher #define E1000_ERR_PHY_TYPE 6 257dee1ad47SJeff Kirsher #define E1000_ERR_RESET 9 258dee1ad47SJeff Kirsher #define E1000_ERR_MASTER_REQUESTS_PENDING 10 259dee1ad47SJeff Kirsher #define E1000_ERR_HOST_INTERFACE_COMMAND 11 260dee1ad47SJeff Kirsher #define E1000_BLK_PHY_RESET 12 261dee1ad47SJeff Kirsher 262dee1ad47SJeff Kirsher #define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ 263dee1ad47SJeff Kirsher (((_value) & 0xff00) >> 8)) 264dee1ad47SJeff Kirsher 265dee1ad47SJeff Kirsher /* Function prototypes */ 266dee1ad47SJeff Kirsher /* Initialization */ 267dee1ad47SJeff Kirsher s32 e1000_reset_hw(struct e1000_hw *hw); 268dee1ad47SJeff Kirsher s32 e1000_init_hw(struct e1000_hw *hw); 269dee1ad47SJeff Kirsher s32 e1000_set_mac_type(struct e1000_hw *hw); 270dee1ad47SJeff Kirsher void e1000_set_media_type(struct e1000_hw *hw); 271dee1ad47SJeff Kirsher 272dee1ad47SJeff Kirsher /* Link Configuration */ 273dee1ad47SJeff Kirsher s32 e1000_setup_link(struct e1000_hw *hw); 274dee1ad47SJeff Kirsher s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 275dee1ad47SJeff Kirsher void e1000_config_collision_dist(struct e1000_hw *hw); 276dee1ad47SJeff Kirsher s32 e1000_check_for_link(struct e1000_hw *hw); 277dee1ad47SJeff Kirsher s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex); 278dee1ad47SJeff Kirsher s32 e1000_force_mac_fc(struct e1000_hw *hw); 279dee1ad47SJeff Kirsher 280dee1ad47SJeff Kirsher /* PHY */ 281dee1ad47SJeff Kirsher s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data); 282dee1ad47SJeff Kirsher s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); 283dee1ad47SJeff Kirsher s32 e1000_phy_hw_reset(struct e1000_hw *hw); 284dee1ad47SJeff Kirsher s32 e1000_phy_reset(struct e1000_hw *hw); 285dee1ad47SJeff Kirsher s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 286dee1ad47SJeff Kirsher s32 e1000_validate_mdi_setting(struct e1000_hw *hw); 287dee1ad47SJeff Kirsher 288dee1ad47SJeff Kirsher /* EEPROM Functions */ 289dee1ad47SJeff Kirsher s32 e1000_init_eeprom_params(struct e1000_hw *hw); 290dee1ad47SJeff Kirsher 291dee1ad47SJeff Kirsher /* MNG HOST IF functions */ 292dee1ad47SJeff Kirsher u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw); 293dee1ad47SJeff Kirsher 294dee1ad47SJeff Kirsher #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 295dee1ad47SJeff Kirsher #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 296dee1ad47SJeff Kirsher 297dee1ad47SJeff Kirsher #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 298dee1ad47SJeff Kirsher #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 299dee1ad47SJeff Kirsher #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 300dee1ad47SJeff Kirsher #define E1000_MNG_IAMT_MODE 0x3 301dee1ad47SJeff Kirsher #define E1000_MNG_ICH_IAMT_MODE 0x2 302dee1ad47SJeff Kirsher #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 303dee1ad47SJeff Kirsher 304dee1ad47SJeff Kirsher #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 305dee1ad47SJeff Kirsher #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ 306dee1ad47SJeff Kirsher #define E1000_VFTA_ENTRY_SHIFT 0x5 307dee1ad47SJeff Kirsher #define E1000_VFTA_ENTRY_MASK 0x7F 308dee1ad47SJeff Kirsher #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 309dee1ad47SJeff Kirsher 310dee1ad47SJeff Kirsher struct e1000_host_mng_command_header { 311dee1ad47SJeff Kirsher u8 command_id; 312dee1ad47SJeff Kirsher u8 checksum; 313dee1ad47SJeff Kirsher u16 reserved1; 314dee1ad47SJeff Kirsher u16 reserved2; 315dee1ad47SJeff Kirsher u16 command_length; 316dee1ad47SJeff Kirsher }; 317dee1ad47SJeff Kirsher 318dee1ad47SJeff Kirsher struct e1000_host_mng_command_info { 319dee1ad47SJeff Kirsher struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 320dee1ad47SJeff Kirsher u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658 */ 321dee1ad47SJeff Kirsher }; 322dee1ad47SJeff Kirsher #ifdef __BIG_ENDIAN 323dee1ad47SJeff Kirsher struct e1000_host_mng_dhcp_cookie { 324dee1ad47SJeff Kirsher u32 signature; 325dee1ad47SJeff Kirsher u16 vlan_id; 326dee1ad47SJeff Kirsher u8 reserved0; 327dee1ad47SJeff Kirsher u8 status; 328dee1ad47SJeff Kirsher u32 reserved1; 329dee1ad47SJeff Kirsher u8 checksum; 330dee1ad47SJeff Kirsher u8 reserved3; 331dee1ad47SJeff Kirsher u16 reserved2; 332dee1ad47SJeff Kirsher }; 333dee1ad47SJeff Kirsher #else 334dee1ad47SJeff Kirsher struct e1000_host_mng_dhcp_cookie { 335dee1ad47SJeff Kirsher u32 signature; 336dee1ad47SJeff Kirsher u8 status; 337dee1ad47SJeff Kirsher u8 reserved0; 338dee1ad47SJeff Kirsher u16 vlan_id; 339dee1ad47SJeff Kirsher u32 reserved1; 340dee1ad47SJeff Kirsher u16 reserved2; 341dee1ad47SJeff Kirsher u8 reserved3; 342dee1ad47SJeff Kirsher u8 checksum; 343dee1ad47SJeff Kirsher }; 344dee1ad47SJeff Kirsher #endif 345dee1ad47SJeff Kirsher 346dee1ad47SJeff Kirsher s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data); 347dee1ad47SJeff Kirsher s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw); 348dee1ad47SJeff Kirsher s32 e1000_update_eeprom_checksum(struct e1000_hw *hw); 349dee1ad47SJeff Kirsher s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data); 350dee1ad47SJeff Kirsher s32 e1000_read_mac_addr(struct e1000_hw *hw); 351dee1ad47SJeff Kirsher 352dee1ad47SJeff Kirsher /* Filters (multicast, vlan, receive) */ 353dee1ad47SJeff Kirsher u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr); 354dee1ad47SJeff Kirsher void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index); 355dee1ad47SJeff Kirsher void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); 356dee1ad47SJeff Kirsher 357dee1ad47SJeff Kirsher /* LED functions */ 358dee1ad47SJeff Kirsher s32 e1000_setup_led(struct e1000_hw *hw); 359dee1ad47SJeff Kirsher s32 e1000_cleanup_led(struct e1000_hw *hw); 360dee1ad47SJeff Kirsher s32 e1000_led_on(struct e1000_hw *hw); 361dee1ad47SJeff Kirsher s32 e1000_led_off(struct e1000_hw *hw); 362dee1ad47SJeff Kirsher 363dee1ad47SJeff Kirsher /* Adaptive IFS Functions */ 364dee1ad47SJeff Kirsher 365dee1ad47SJeff Kirsher /* Everything else */ 366dee1ad47SJeff Kirsher void e1000_reset_adaptive(struct e1000_hw *hw); 367dee1ad47SJeff Kirsher void e1000_update_adaptive(struct e1000_hw *hw); 368dee1ad47SJeff Kirsher void e1000_get_bus_info(struct e1000_hw *hw); 369dee1ad47SJeff Kirsher void e1000_pci_set_mwi(struct e1000_hw *hw); 370dee1ad47SJeff Kirsher void e1000_pci_clear_mwi(struct e1000_hw *hw); 371dee1ad47SJeff Kirsher void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc); 372dee1ad47SJeff Kirsher int e1000_pcix_get_mmrbc(struct e1000_hw *hw); 373dee1ad47SJeff Kirsher /* Port I/O is only supported on 82544 and newer */ 374dee1ad47SJeff Kirsher void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); 375dee1ad47SJeff Kirsher 376dee1ad47SJeff Kirsher #define E1000_READ_REG_IO(a, reg) \ 377dee1ad47SJeff Kirsher e1000_read_reg_io((a), E1000_##reg) 378dee1ad47SJeff Kirsher #define E1000_WRITE_REG_IO(a, reg, val) \ 379dee1ad47SJeff Kirsher e1000_write_reg_io((a), E1000_##reg, val) 380dee1ad47SJeff Kirsher 381dee1ad47SJeff Kirsher /* PCI Device IDs */ 382dee1ad47SJeff Kirsher #define E1000_DEV_ID_82542 0x1000 383dee1ad47SJeff Kirsher #define E1000_DEV_ID_82543GC_FIBER 0x1001 384dee1ad47SJeff Kirsher #define E1000_DEV_ID_82543GC_COPPER 0x1004 385dee1ad47SJeff Kirsher #define E1000_DEV_ID_82544EI_COPPER 0x1008 386dee1ad47SJeff Kirsher #define E1000_DEV_ID_82544EI_FIBER 0x1009 387dee1ad47SJeff Kirsher #define E1000_DEV_ID_82544GC_COPPER 0x100C 388dee1ad47SJeff Kirsher #define E1000_DEV_ID_82544GC_LOM 0x100D 389dee1ad47SJeff Kirsher #define E1000_DEV_ID_82540EM 0x100E 390dee1ad47SJeff Kirsher #define E1000_DEV_ID_82540EM_LOM 0x1015 391dee1ad47SJeff Kirsher #define E1000_DEV_ID_82540EP_LOM 0x1016 392dee1ad47SJeff Kirsher #define E1000_DEV_ID_82540EP 0x1017 393dee1ad47SJeff Kirsher #define E1000_DEV_ID_82540EP_LP 0x101E 394dee1ad47SJeff Kirsher #define E1000_DEV_ID_82545EM_COPPER 0x100F 395dee1ad47SJeff Kirsher #define E1000_DEV_ID_82545EM_FIBER 0x1011 396dee1ad47SJeff Kirsher #define E1000_DEV_ID_82545GM_COPPER 0x1026 397dee1ad47SJeff Kirsher #define E1000_DEV_ID_82545GM_FIBER 0x1027 398dee1ad47SJeff Kirsher #define E1000_DEV_ID_82545GM_SERDES 0x1028 399dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546EB_COPPER 0x1010 400dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546EB_FIBER 0x1012 401dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 402dee1ad47SJeff Kirsher #define E1000_DEV_ID_82541EI 0x1013 403dee1ad47SJeff Kirsher #define E1000_DEV_ID_82541EI_MOBILE 0x1018 404dee1ad47SJeff Kirsher #define E1000_DEV_ID_82541ER_LOM 0x1014 405dee1ad47SJeff Kirsher #define E1000_DEV_ID_82541ER 0x1078 406dee1ad47SJeff Kirsher #define E1000_DEV_ID_82547GI 0x1075 407dee1ad47SJeff Kirsher #define E1000_DEV_ID_82541GI 0x1076 408dee1ad47SJeff Kirsher #define E1000_DEV_ID_82541GI_MOBILE 0x1077 409dee1ad47SJeff Kirsher #define E1000_DEV_ID_82541GI_LF 0x107C 410dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546GB_COPPER 0x1079 411dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546GB_FIBER 0x107A 412dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546GB_SERDES 0x107B 413dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546GB_PCIE 0x108A 414dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 415dee1ad47SJeff Kirsher #define E1000_DEV_ID_82547EI 0x1019 416dee1ad47SJeff Kirsher #define E1000_DEV_ID_82547EI_MOBILE 0x101A 417dee1ad47SJeff Kirsher #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 418dee1ad47SJeff Kirsher #define E1000_DEV_ID_INTEL_CE4100_GBE 0x2E6E 419dee1ad47SJeff Kirsher 420dee1ad47SJeff Kirsher #define NODE_ADDRESS_SIZE 6 421dee1ad47SJeff Kirsher 422dee1ad47SJeff Kirsher /* MAC decode size is 128K - This is the size of BAR0 */ 423dee1ad47SJeff Kirsher #define MAC_DECODE_SIZE (128 * 1024) 424dee1ad47SJeff Kirsher 425dee1ad47SJeff Kirsher #define E1000_82542_2_0_REV_ID 2 426dee1ad47SJeff Kirsher #define E1000_82542_2_1_REV_ID 3 427dee1ad47SJeff Kirsher #define E1000_REVISION_0 0 428dee1ad47SJeff Kirsher #define E1000_REVISION_1 1 429dee1ad47SJeff Kirsher #define E1000_REVISION_2 2 430dee1ad47SJeff Kirsher #define E1000_REVISION_3 3 431dee1ad47SJeff Kirsher 432dee1ad47SJeff Kirsher #define SPEED_10 10 433dee1ad47SJeff Kirsher #define SPEED_100 100 434dee1ad47SJeff Kirsher #define SPEED_1000 1000 435dee1ad47SJeff Kirsher #define HALF_DUPLEX 1 436dee1ad47SJeff Kirsher #define FULL_DUPLEX 2 437dee1ad47SJeff Kirsher 438dee1ad47SJeff Kirsher /* The sizes (in bytes) of a ethernet packet */ 439dee1ad47SJeff Kirsher #define ENET_HEADER_SIZE 14 440dee1ad47SJeff Kirsher #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 441dee1ad47SJeff Kirsher #define ETHERNET_FCS_SIZE 4 442dee1ad47SJeff Kirsher #define MINIMUM_ETHERNET_PACKET_SIZE \ 443dee1ad47SJeff Kirsher (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 444dee1ad47SJeff Kirsher #define CRC_LENGTH ETHERNET_FCS_SIZE 445dee1ad47SJeff Kirsher #define MAX_JUMBO_FRAME_SIZE 0x3F00 446dee1ad47SJeff Kirsher 447dee1ad47SJeff Kirsher /* 802.1q VLAN Packet Sizes */ 448dee1ad47SJeff Kirsher #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 449dee1ad47SJeff Kirsher 450dee1ad47SJeff Kirsher /* Ethertype field values */ 451dee1ad47SJeff Kirsher #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 452dee1ad47SJeff Kirsher #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 453dee1ad47SJeff Kirsher #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 454dee1ad47SJeff Kirsher 455dee1ad47SJeff Kirsher /* Packet Header defines */ 456dee1ad47SJeff Kirsher #define IP_PROTOCOL_TCP 6 457dee1ad47SJeff Kirsher #define IP_PROTOCOL_UDP 0x11 458dee1ad47SJeff Kirsher 459dee1ad47SJeff Kirsher /* This defines the bits that are set in the Interrupt Mask 460dee1ad47SJeff Kirsher * Set/Read Register. Each bit is documented below: 461dee1ad47SJeff Kirsher * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 462dee1ad47SJeff Kirsher * o RXSEQ = Receive Sequence Error 463dee1ad47SJeff Kirsher */ 464dee1ad47SJeff Kirsher #define POLL_IMS_ENABLE_MASK ( \ 465dee1ad47SJeff Kirsher E1000_IMS_RXDMT0 | \ 466dee1ad47SJeff Kirsher E1000_IMS_RXSEQ) 467dee1ad47SJeff Kirsher 468dee1ad47SJeff Kirsher /* This defines the bits that are set in the Interrupt Mask 469dee1ad47SJeff Kirsher * Set/Read Register. Each bit is documented below: 470dee1ad47SJeff Kirsher * o RXT0 = Receiver Timer Interrupt (ring 0) 471dee1ad47SJeff Kirsher * o TXDW = Transmit Descriptor Written Back 472dee1ad47SJeff Kirsher * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 473dee1ad47SJeff Kirsher * o RXSEQ = Receive Sequence Error 474dee1ad47SJeff Kirsher * o LSC = Link Status Change 475dee1ad47SJeff Kirsher */ 476dee1ad47SJeff Kirsher #define IMS_ENABLE_MASK ( \ 477dee1ad47SJeff Kirsher E1000_IMS_RXT0 | \ 478dee1ad47SJeff Kirsher E1000_IMS_TXDW | \ 479dee1ad47SJeff Kirsher E1000_IMS_RXDMT0 | \ 480dee1ad47SJeff Kirsher E1000_IMS_RXSEQ | \ 481dee1ad47SJeff Kirsher E1000_IMS_LSC) 482dee1ad47SJeff Kirsher 483dee1ad47SJeff Kirsher /* Number of high/low register pairs in the RAR. The RAR (Receive Address 484dee1ad47SJeff Kirsher * Registers) holds the directed and multicast addresses that we monitor. We 485dee1ad47SJeff Kirsher * reserve one of these spots for our directed address, allowing us room for 486dee1ad47SJeff Kirsher * E1000_RAR_ENTRIES - 1 multicast addresses. 487dee1ad47SJeff Kirsher */ 488dee1ad47SJeff Kirsher #define E1000_RAR_ENTRIES 15 489dee1ad47SJeff Kirsher 490dee1ad47SJeff Kirsher #define MIN_NUMBER_OF_DESCRIPTORS 8 491dee1ad47SJeff Kirsher #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 492dee1ad47SJeff Kirsher 493dee1ad47SJeff Kirsher /* Receive Descriptor */ 494dee1ad47SJeff Kirsher struct e1000_rx_desc { 495dee1ad47SJeff Kirsher __le64 buffer_addr; /* Address of the descriptor's data buffer */ 496dee1ad47SJeff Kirsher __le16 length; /* Length of data DMAed into data buffer */ 497dee1ad47SJeff Kirsher __le16 csum; /* Packet checksum */ 498dee1ad47SJeff Kirsher u8 status; /* Descriptor status */ 499dee1ad47SJeff Kirsher u8 errors; /* Descriptor Errors */ 500dee1ad47SJeff Kirsher __le16 special; 501dee1ad47SJeff Kirsher }; 502dee1ad47SJeff Kirsher 503dee1ad47SJeff Kirsher /* Receive Descriptor - Extended */ 504dee1ad47SJeff Kirsher union e1000_rx_desc_extended { 505dee1ad47SJeff Kirsher struct { 506dee1ad47SJeff Kirsher __le64 buffer_addr; 507dee1ad47SJeff Kirsher __le64 reserved; 508dee1ad47SJeff Kirsher } read; 509dee1ad47SJeff Kirsher struct { 510dee1ad47SJeff Kirsher struct { 511dee1ad47SJeff Kirsher __le32 mrq; /* Multiple Rx Queues */ 512dee1ad47SJeff Kirsher union { 513dee1ad47SJeff Kirsher __le32 rss; /* RSS Hash */ 514dee1ad47SJeff Kirsher struct { 515dee1ad47SJeff Kirsher __le16 ip_id; /* IP id */ 516dee1ad47SJeff Kirsher __le16 csum; /* Packet Checksum */ 517dee1ad47SJeff Kirsher } csum_ip; 518dee1ad47SJeff Kirsher } hi_dword; 519dee1ad47SJeff Kirsher } lower; 520dee1ad47SJeff Kirsher struct { 521dee1ad47SJeff Kirsher __le32 status_error; /* ext status/error */ 522dee1ad47SJeff Kirsher __le16 length; 523dee1ad47SJeff Kirsher __le16 vlan; /* VLAN tag */ 524dee1ad47SJeff Kirsher } upper; 525dee1ad47SJeff Kirsher } wb; /* writeback */ 526dee1ad47SJeff Kirsher }; 527dee1ad47SJeff Kirsher 528dee1ad47SJeff Kirsher #define MAX_PS_BUFFERS 4 529dee1ad47SJeff Kirsher /* Receive Descriptor - Packet Split */ 530dee1ad47SJeff Kirsher union e1000_rx_desc_packet_split { 531dee1ad47SJeff Kirsher struct { 532dee1ad47SJeff Kirsher /* one buffer for protocol header(s), three data buffers */ 533dee1ad47SJeff Kirsher __le64 buffer_addr[MAX_PS_BUFFERS]; 534dee1ad47SJeff Kirsher } read; 535dee1ad47SJeff Kirsher struct { 536dee1ad47SJeff Kirsher struct { 537dee1ad47SJeff Kirsher __le32 mrq; /* Multiple Rx Queues */ 538dee1ad47SJeff Kirsher union { 539dee1ad47SJeff Kirsher __le32 rss; /* RSS Hash */ 540dee1ad47SJeff Kirsher struct { 541dee1ad47SJeff Kirsher __le16 ip_id; /* IP id */ 542dee1ad47SJeff Kirsher __le16 csum; /* Packet Checksum */ 543dee1ad47SJeff Kirsher } csum_ip; 544dee1ad47SJeff Kirsher } hi_dword; 545dee1ad47SJeff Kirsher } lower; 546dee1ad47SJeff Kirsher struct { 547dee1ad47SJeff Kirsher __le32 status_error; /* ext status/error */ 548dee1ad47SJeff Kirsher __le16 length0; /* length of buffer 0 */ 549dee1ad47SJeff Kirsher __le16 vlan; /* VLAN tag */ 550dee1ad47SJeff Kirsher } middle; 551dee1ad47SJeff Kirsher struct { 552dee1ad47SJeff Kirsher __le16 header_status; 553dee1ad47SJeff Kirsher __le16 length[3]; /* length of buffers 1-3 */ 554dee1ad47SJeff Kirsher } upper; 555dee1ad47SJeff Kirsher __le64 reserved; 556dee1ad47SJeff Kirsher } wb; /* writeback */ 557dee1ad47SJeff Kirsher }; 558dee1ad47SJeff Kirsher 559dee1ad47SJeff Kirsher /* Receive Descriptor bit definitions */ 560dee1ad47SJeff Kirsher #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 561dee1ad47SJeff Kirsher #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 562dee1ad47SJeff Kirsher #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 563dee1ad47SJeff Kirsher #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 564dee1ad47SJeff Kirsher #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 565dee1ad47SJeff Kirsher #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 566dee1ad47SJeff Kirsher #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 567dee1ad47SJeff Kirsher #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 568dee1ad47SJeff Kirsher #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 569dee1ad47SJeff Kirsher #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 570dee1ad47SJeff Kirsher #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 571dee1ad47SJeff Kirsher #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 572dee1ad47SJeff Kirsher #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 573dee1ad47SJeff Kirsher #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 574dee1ad47SJeff Kirsher #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 575dee1ad47SJeff Kirsher #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 576dee1ad47SJeff Kirsher #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 577dee1ad47SJeff Kirsher #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 578dee1ad47SJeff Kirsher #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 579dee1ad47SJeff Kirsher #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 580dee1ad47SJeff Kirsher #define E1000_RXD_SPC_PRI_SHIFT 13 581dee1ad47SJeff Kirsher #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 582dee1ad47SJeff Kirsher #define E1000_RXD_SPC_CFI_SHIFT 12 583dee1ad47SJeff Kirsher 584dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_CE 0x01000000 585dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_SE 0x02000000 586dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_SEQ 0x04000000 587dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_CXE 0x10000000 588dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_TCPE 0x20000000 589dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_IPE 0x40000000 590dee1ad47SJeff Kirsher #define E1000_RXDEXT_STATERR_RXE 0x80000000 591dee1ad47SJeff Kirsher 592dee1ad47SJeff Kirsher #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 593dee1ad47SJeff Kirsher #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 594dee1ad47SJeff Kirsher 595dee1ad47SJeff Kirsher /* mask to determine if packets should be dropped due to frame errors */ 596dee1ad47SJeff Kirsher #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 597dee1ad47SJeff Kirsher E1000_RXD_ERR_CE | \ 598dee1ad47SJeff Kirsher E1000_RXD_ERR_SE | \ 599dee1ad47SJeff Kirsher E1000_RXD_ERR_SEQ | \ 600dee1ad47SJeff Kirsher E1000_RXD_ERR_CXE | \ 601dee1ad47SJeff Kirsher E1000_RXD_ERR_RXE) 602dee1ad47SJeff Kirsher 603dee1ad47SJeff Kirsher /* Same mask, but for extended and packet split descriptors */ 604dee1ad47SJeff Kirsher #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 605dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_CE | \ 606dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_SE | \ 607dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_SEQ | \ 608dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_CXE | \ 609dee1ad47SJeff Kirsher E1000_RXDEXT_STATERR_RXE) 610dee1ad47SJeff Kirsher 611dee1ad47SJeff Kirsher /* Transmit Descriptor */ 612dee1ad47SJeff Kirsher struct e1000_tx_desc { 613dee1ad47SJeff Kirsher __le64 buffer_addr; /* Address of the descriptor's data buffer */ 614dee1ad47SJeff Kirsher union { 615dee1ad47SJeff Kirsher __le32 data; 616dee1ad47SJeff Kirsher struct { 617dee1ad47SJeff Kirsher __le16 length; /* Data buffer length */ 618dee1ad47SJeff Kirsher u8 cso; /* Checksum offset */ 619dee1ad47SJeff Kirsher u8 cmd; /* Descriptor control */ 620dee1ad47SJeff Kirsher } flags; 621dee1ad47SJeff Kirsher } lower; 622dee1ad47SJeff Kirsher union { 623dee1ad47SJeff Kirsher __le32 data; 624dee1ad47SJeff Kirsher struct { 625dee1ad47SJeff Kirsher u8 status; /* Descriptor status */ 626dee1ad47SJeff Kirsher u8 css; /* Checksum start */ 627dee1ad47SJeff Kirsher __le16 special; 628dee1ad47SJeff Kirsher } fields; 629dee1ad47SJeff Kirsher } upper; 630dee1ad47SJeff Kirsher }; 631dee1ad47SJeff Kirsher 632dee1ad47SJeff Kirsher /* Transmit Descriptor bit definitions */ 633dee1ad47SJeff Kirsher #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 634dee1ad47SJeff Kirsher #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 635dee1ad47SJeff Kirsher #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 636dee1ad47SJeff Kirsher #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 637dee1ad47SJeff Kirsher #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 638dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 639dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 640dee1ad47SJeff Kirsher #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 641dee1ad47SJeff Kirsher #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 642dee1ad47SJeff Kirsher #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 643dee1ad47SJeff Kirsher #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 644dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 645dee1ad47SJeff Kirsher #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 646dee1ad47SJeff Kirsher #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 647dee1ad47SJeff Kirsher #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 648dee1ad47SJeff Kirsher #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 649dee1ad47SJeff Kirsher #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 650dee1ad47SJeff Kirsher #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 651dee1ad47SJeff Kirsher #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 652dee1ad47SJeff Kirsher #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 653dee1ad47SJeff Kirsher 654dee1ad47SJeff Kirsher /* Offload Context Descriptor */ 655dee1ad47SJeff Kirsher struct e1000_context_desc { 656dee1ad47SJeff Kirsher union { 657dee1ad47SJeff Kirsher __le32 ip_config; 658dee1ad47SJeff Kirsher struct { 659dee1ad47SJeff Kirsher u8 ipcss; /* IP checksum start */ 660dee1ad47SJeff Kirsher u8 ipcso; /* IP checksum offset */ 661dee1ad47SJeff Kirsher __le16 ipcse; /* IP checksum end */ 662dee1ad47SJeff Kirsher } ip_fields; 663dee1ad47SJeff Kirsher } lower_setup; 664dee1ad47SJeff Kirsher union { 665dee1ad47SJeff Kirsher __le32 tcp_config; 666dee1ad47SJeff Kirsher struct { 667dee1ad47SJeff Kirsher u8 tucss; /* TCP checksum start */ 668dee1ad47SJeff Kirsher u8 tucso; /* TCP checksum offset */ 669dee1ad47SJeff Kirsher __le16 tucse; /* TCP checksum end */ 670dee1ad47SJeff Kirsher } tcp_fields; 671dee1ad47SJeff Kirsher } upper_setup; 672dee1ad47SJeff Kirsher __le32 cmd_and_length; /* */ 673dee1ad47SJeff Kirsher union { 674dee1ad47SJeff Kirsher __le32 data; 675dee1ad47SJeff Kirsher struct { 676dee1ad47SJeff Kirsher u8 status; /* Descriptor status */ 677dee1ad47SJeff Kirsher u8 hdr_len; /* Header length */ 678dee1ad47SJeff Kirsher __le16 mss; /* Maximum segment size */ 679dee1ad47SJeff Kirsher } fields; 680dee1ad47SJeff Kirsher } tcp_seg_setup; 681dee1ad47SJeff Kirsher }; 682dee1ad47SJeff Kirsher 683dee1ad47SJeff Kirsher /* Offload data descriptor */ 684dee1ad47SJeff Kirsher struct e1000_data_desc { 685dee1ad47SJeff Kirsher __le64 buffer_addr; /* Address of the descriptor's buffer address */ 686dee1ad47SJeff Kirsher union { 687dee1ad47SJeff Kirsher __le32 data; 688dee1ad47SJeff Kirsher struct { 689dee1ad47SJeff Kirsher __le16 length; /* Data buffer length */ 690dee1ad47SJeff Kirsher u8 typ_len_ext; /* */ 691dee1ad47SJeff Kirsher u8 cmd; /* */ 692dee1ad47SJeff Kirsher } flags; 693dee1ad47SJeff Kirsher } lower; 694dee1ad47SJeff Kirsher union { 695dee1ad47SJeff Kirsher __le32 data; 696dee1ad47SJeff Kirsher struct { 697dee1ad47SJeff Kirsher u8 status; /* Descriptor status */ 698dee1ad47SJeff Kirsher u8 popts; /* Packet Options */ 699dee1ad47SJeff Kirsher __le16 special; /* */ 700dee1ad47SJeff Kirsher } fields; 701dee1ad47SJeff Kirsher } upper; 702dee1ad47SJeff Kirsher }; 703dee1ad47SJeff Kirsher 704dee1ad47SJeff Kirsher /* Filters */ 705dee1ad47SJeff Kirsher #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 706dee1ad47SJeff Kirsher #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 707dee1ad47SJeff Kirsher #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 708dee1ad47SJeff Kirsher 709dee1ad47SJeff Kirsher /* Receive Address Register */ 710dee1ad47SJeff Kirsher struct e1000_rar { 711dee1ad47SJeff Kirsher volatile __le32 low; /* receive address low */ 712dee1ad47SJeff Kirsher volatile __le32 high; /* receive address high */ 713dee1ad47SJeff Kirsher }; 714dee1ad47SJeff Kirsher 715dee1ad47SJeff Kirsher /* Number of entries in the Multicast Table Array (MTA). */ 716dee1ad47SJeff Kirsher #define E1000_NUM_MTA_REGISTERS 128 717dee1ad47SJeff Kirsher 718dee1ad47SJeff Kirsher /* IPv4 Address Table Entry */ 719dee1ad47SJeff Kirsher struct e1000_ipv4_at_entry { 720dee1ad47SJeff Kirsher volatile u32 ipv4_addr; /* IP Address (RW) */ 721dee1ad47SJeff Kirsher volatile u32 reserved; 722dee1ad47SJeff Kirsher }; 723dee1ad47SJeff Kirsher 724dee1ad47SJeff Kirsher /* Four wakeup IP addresses are supported */ 725dee1ad47SJeff Kirsher #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 726dee1ad47SJeff Kirsher #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 727dee1ad47SJeff Kirsher #define E1000_IP6AT_SIZE 1 728dee1ad47SJeff Kirsher 729dee1ad47SJeff Kirsher /* IPv6 Address Table Entry */ 730dee1ad47SJeff Kirsher struct e1000_ipv6_at_entry { 731dee1ad47SJeff Kirsher volatile u8 ipv6_addr[16]; 732dee1ad47SJeff Kirsher }; 733dee1ad47SJeff Kirsher 734dee1ad47SJeff Kirsher /* Flexible Filter Length Table Entry */ 735dee1ad47SJeff Kirsher struct e1000_fflt_entry { 736dee1ad47SJeff Kirsher volatile u32 length; /* Flexible Filter Length (RW) */ 737dee1ad47SJeff Kirsher volatile u32 reserved; 738dee1ad47SJeff Kirsher }; 739dee1ad47SJeff Kirsher 740dee1ad47SJeff Kirsher /* Flexible Filter Mask Table Entry */ 741dee1ad47SJeff Kirsher struct e1000_ffmt_entry { 742dee1ad47SJeff Kirsher volatile u32 mask; /* Flexible Filter Mask (RW) */ 743dee1ad47SJeff Kirsher volatile u32 reserved; 744dee1ad47SJeff Kirsher }; 745dee1ad47SJeff Kirsher 746dee1ad47SJeff Kirsher /* Flexible Filter Value Table Entry */ 747dee1ad47SJeff Kirsher struct e1000_ffvt_entry { 748dee1ad47SJeff Kirsher volatile u32 value; /* Flexible Filter Value (RW) */ 749dee1ad47SJeff Kirsher volatile u32 reserved; 750dee1ad47SJeff Kirsher }; 751dee1ad47SJeff Kirsher 752dee1ad47SJeff Kirsher /* Four Flexible Filters are supported */ 753dee1ad47SJeff Kirsher #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 754dee1ad47SJeff Kirsher 755dee1ad47SJeff Kirsher /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 756dee1ad47SJeff Kirsher #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 757dee1ad47SJeff Kirsher 758dee1ad47SJeff Kirsher #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 759dee1ad47SJeff Kirsher #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 760dee1ad47SJeff Kirsher #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 761dee1ad47SJeff Kirsher 762dee1ad47SJeff Kirsher #define E1000_DISABLE_SERDES_LOOPBACK 0x0400 763dee1ad47SJeff Kirsher 764dee1ad47SJeff Kirsher /* Register Set. (82543, 82544) 765dee1ad47SJeff Kirsher * 766dee1ad47SJeff Kirsher * Registers are defined to be 32 bits and should be accessed as 32 bit values. 767dee1ad47SJeff Kirsher * These registers are physically located on the NIC, but are mapped into the 768dee1ad47SJeff Kirsher * host memory address space. 769dee1ad47SJeff Kirsher * 770dee1ad47SJeff Kirsher * RW - register is both readable and writable 771dee1ad47SJeff Kirsher * RO - register is read only 772dee1ad47SJeff Kirsher * WO - register is write only 773dee1ad47SJeff Kirsher * R/clr - register is read only and is cleared when read 774dee1ad47SJeff Kirsher * A - register array 775dee1ad47SJeff Kirsher */ 776dee1ad47SJeff Kirsher #define E1000_CTRL 0x00000 /* Device Control - RW */ 777dee1ad47SJeff Kirsher #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 778dee1ad47SJeff Kirsher #define E1000_STATUS 0x00008 /* Device Status - RO */ 779dee1ad47SJeff Kirsher #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 780dee1ad47SJeff Kirsher #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 781dee1ad47SJeff Kirsher #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 782dee1ad47SJeff Kirsher #define E1000_FLA 0x0001C /* Flash Access - RW */ 783dee1ad47SJeff Kirsher #define E1000_MDIC 0x00020 /* MDI Control - RW */ 784dee1ad47SJeff Kirsher 78513acde8fSFlorian Fainelli #define INTEL_CE_GBE_MDIO_RCOMP_BASE (hw->ce4100_gbe_mdio_base_virt) 786dee1ad47SJeff Kirsher #define E1000_MDIO_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0) 787dee1ad47SJeff Kirsher #define E1000_MDIO_CMD (INTEL_CE_GBE_MDIO_RCOMP_BASE + 4) 788dee1ad47SJeff Kirsher #define E1000_MDIO_DRV (INTEL_CE_GBE_MDIO_RCOMP_BASE + 8) 789dee1ad47SJeff Kirsher #define E1000_MDC_CMD (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0xC) 790dee1ad47SJeff Kirsher #define E1000_RCOMP_CTL (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x20) 791dee1ad47SJeff Kirsher #define E1000_RCOMP_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x24) 792dee1ad47SJeff Kirsher 793dee1ad47SJeff Kirsher #define E1000_SCTL 0x00024 /* SerDes Control - RW */ 794dee1ad47SJeff Kirsher #define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ 795dee1ad47SJeff Kirsher #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 796dee1ad47SJeff Kirsher #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 797dee1ad47SJeff Kirsher #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 798dee1ad47SJeff Kirsher #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 799dee1ad47SJeff Kirsher #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 800dee1ad47SJeff Kirsher #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 801dee1ad47SJeff Kirsher #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 802dee1ad47SJeff Kirsher #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 803dee1ad47SJeff Kirsher #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 804dee1ad47SJeff Kirsher #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 805dee1ad47SJeff Kirsher 806dee1ad47SJeff Kirsher /* Auxiliary Control Register. This register is CE4100 specific, 807dee1ad47SJeff Kirsher * RMII/RGMII function is switched by this register - RW 808dee1ad47SJeff Kirsher * Following are bits definitions of the Auxiliary Control Register 809dee1ad47SJeff Kirsher */ 810dee1ad47SJeff Kirsher #define E1000_CTL_AUX 0x000E0 811dee1ad47SJeff Kirsher #define E1000_CTL_AUX_END_SEL_SHIFT 10 812dee1ad47SJeff Kirsher #define E1000_CTL_AUX_ENDIANESS_SHIFT 8 813dee1ad47SJeff Kirsher #define E1000_CTL_AUX_RGMII_RMII_SHIFT 0 814dee1ad47SJeff Kirsher 815dee1ad47SJeff Kirsher /* descriptor and packet transfer use CTL_AUX.ENDIANESS */ 816dee1ad47SJeff Kirsher #define E1000_CTL_AUX_DES_PKT (0x0 << E1000_CTL_AUX_END_SEL_SHIFT) 817dee1ad47SJeff Kirsher /* descriptor use CTL_AUX.ENDIANESS, packet use default */ 818dee1ad47SJeff Kirsher #define E1000_CTL_AUX_DES (0x1 << E1000_CTL_AUX_END_SEL_SHIFT) 819dee1ad47SJeff Kirsher /* descriptor use default, packet use CTL_AUX.ENDIANESS */ 820dee1ad47SJeff Kirsher #define E1000_CTL_AUX_PKT (0x2 << E1000_CTL_AUX_END_SEL_SHIFT) 821dee1ad47SJeff Kirsher /* all use CTL_AUX.ENDIANESS */ 822dee1ad47SJeff Kirsher #define E1000_CTL_AUX_ALL (0x3 << E1000_CTL_AUX_END_SEL_SHIFT) 823dee1ad47SJeff Kirsher 824dee1ad47SJeff Kirsher #define E1000_CTL_AUX_RGMII (0x0 << E1000_CTL_AUX_RGMII_RMII_SHIFT) 825dee1ad47SJeff Kirsher #define E1000_CTL_AUX_RMII (0x1 << E1000_CTL_AUX_RGMII_RMII_SHIFT) 826dee1ad47SJeff Kirsher 827dee1ad47SJeff Kirsher /* LW little endian, Byte big endian */ 828dee1ad47SJeff Kirsher #define E1000_CTL_AUX_LWLE_BBE (0x0 << E1000_CTL_AUX_ENDIANESS_SHIFT) 829dee1ad47SJeff Kirsher #define E1000_CTL_AUX_LWLE_BLE (0x1 << E1000_CTL_AUX_ENDIANESS_SHIFT) 830dee1ad47SJeff Kirsher #define E1000_CTL_AUX_LWBE_BBE (0x2 << E1000_CTL_AUX_ENDIANESS_SHIFT) 831dee1ad47SJeff Kirsher #define E1000_CTL_AUX_LWBE_BLE (0x3 << E1000_CTL_AUX_ENDIANESS_SHIFT) 832dee1ad47SJeff Kirsher 833dee1ad47SJeff Kirsher #define E1000_RCTL 0x00100 /* RX Control - RW */ 834dee1ad47SJeff Kirsher #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ 835dee1ad47SJeff Kirsher #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ 836dee1ad47SJeff Kirsher #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ 837dee1ad47SJeff Kirsher #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ 838dee1ad47SJeff Kirsher #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ 839dee1ad47SJeff Kirsher #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ 840dee1ad47SJeff Kirsher #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 841dee1ad47SJeff Kirsher #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 842dee1ad47SJeff Kirsher #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 843dee1ad47SJeff Kirsher #define E1000_TCTL 0x00400 /* TX Control - RW */ 844dee1ad47SJeff Kirsher #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 845dee1ad47SJeff Kirsher #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 846dee1ad47SJeff Kirsher #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 847dee1ad47SJeff Kirsher #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 848dee1ad47SJeff Kirsher #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 849dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 850dee1ad47SJeff Kirsher #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 851dee1ad47SJeff Kirsher #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 852dee1ad47SJeff Kirsher #define FEXTNVM_SW_CONFIG 0x0001 853dee1ad47SJeff Kirsher #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 854dee1ad47SJeff Kirsher #define E1000_PBS 0x01008 /* Packet Buffer Size */ 855dee1ad47SJeff Kirsher #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 856dee1ad47SJeff Kirsher #define E1000_FLASH_UPDATES 1000 857dee1ad47SJeff Kirsher #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 858dee1ad47SJeff Kirsher #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 859dee1ad47SJeff Kirsher #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 860dee1ad47SJeff Kirsher #define E1000_FLSWCTL 0x01030 /* FLASH control register */ 861dee1ad47SJeff Kirsher #define E1000_FLSWDATA 0x01034 /* FLASH data register */ 862dee1ad47SJeff Kirsher #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 863dee1ad47SJeff Kirsher #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 864dee1ad47SJeff Kirsher #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 865dee1ad47SJeff Kirsher #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 866dee1ad47SJeff Kirsher #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 867dee1ad47SJeff Kirsher #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 868b04e36baSTushar Dave #define E1000_RDFH 0x02410 /* RX Data FIFO Head - RW */ 869b04e36baSTushar Dave #define E1000_RDFT 0x02418 /* RX Data FIFO Tail - RW */ 870b04e36baSTushar Dave #define E1000_RDFHS 0x02420 /* RX Data FIFO Head Saved - RW */ 871b04e36baSTushar Dave #define E1000_RDFTS 0x02428 /* RX Data FIFO Tail Saved - RW */ 872b04e36baSTushar Dave #define E1000_RDFPC 0x02430 /* RX Data FIFO Packet Count - RW */ 873dee1ad47SJeff Kirsher #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 874dee1ad47SJeff Kirsher #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 875dee1ad47SJeff Kirsher #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 876dee1ad47SJeff Kirsher #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 877dee1ad47SJeff Kirsher #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 878dee1ad47SJeff Kirsher #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 879dee1ad47SJeff Kirsher #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ 880dee1ad47SJeff Kirsher #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ 881dee1ad47SJeff Kirsher #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ 882dee1ad47SJeff Kirsher #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 883dee1ad47SJeff Kirsher #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 884dee1ad47SJeff Kirsher #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 885dee1ad47SJeff Kirsher #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ 886dee1ad47SJeff Kirsher #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ 887dee1ad47SJeff Kirsher #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 888dee1ad47SJeff Kirsher #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 889dee1ad47SJeff Kirsher #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 890dee1ad47SJeff Kirsher #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 891dee1ad47SJeff Kirsher #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 892dee1ad47SJeff Kirsher #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 893dee1ad47SJeff Kirsher #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 894dee1ad47SJeff Kirsher #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 895dee1ad47SJeff Kirsher #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 896dee1ad47SJeff Kirsher #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 897dee1ad47SJeff Kirsher #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 898dee1ad47SJeff Kirsher #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 899dee1ad47SJeff Kirsher #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 900dee1ad47SJeff Kirsher #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 901dee1ad47SJeff Kirsher #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 902dee1ad47SJeff Kirsher #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 903dee1ad47SJeff Kirsher #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 904dee1ad47SJeff Kirsher #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 905dee1ad47SJeff Kirsher #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 906dee1ad47SJeff Kirsher #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ 907dee1ad47SJeff Kirsher #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ 908dee1ad47SJeff Kirsher #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ 909dee1ad47SJeff Kirsher #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ 910dee1ad47SJeff Kirsher #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ 911dee1ad47SJeff Kirsher #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ 912dee1ad47SJeff Kirsher #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ 913dee1ad47SJeff Kirsher #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ 914dee1ad47SJeff Kirsher #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 915dee1ad47SJeff Kirsher #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 916dee1ad47SJeff Kirsher #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 917dee1ad47SJeff Kirsher #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 918dee1ad47SJeff Kirsher #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 919dee1ad47SJeff Kirsher #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 920dee1ad47SJeff Kirsher #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 921dee1ad47SJeff Kirsher #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 922dee1ad47SJeff Kirsher #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 923dee1ad47SJeff Kirsher #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 924dee1ad47SJeff Kirsher #define E1000_DC 0x04030 /* Defer Count - R/clr */ 925dee1ad47SJeff Kirsher #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 926dee1ad47SJeff Kirsher #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 927dee1ad47SJeff Kirsher #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 928dee1ad47SJeff Kirsher #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 929dee1ad47SJeff Kirsher #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 930dee1ad47SJeff Kirsher #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 931dee1ad47SJeff Kirsher #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 932dee1ad47SJeff Kirsher #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 933dee1ad47SJeff Kirsher #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 934dee1ad47SJeff Kirsher #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 935dee1ad47SJeff Kirsher #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 936dee1ad47SJeff Kirsher #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 937dee1ad47SJeff Kirsher #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 938dee1ad47SJeff Kirsher #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 939dee1ad47SJeff Kirsher #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 940dee1ad47SJeff Kirsher #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 941dee1ad47SJeff Kirsher #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 942dee1ad47SJeff Kirsher #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 943dee1ad47SJeff Kirsher #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 944dee1ad47SJeff Kirsher #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 945dee1ad47SJeff Kirsher #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 946dee1ad47SJeff Kirsher #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 947dee1ad47SJeff Kirsher #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 948dee1ad47SJeff Kirsher #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 949dee1ad47SJeff Kirsher #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 950dee1ad47SJeff Kirsher #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 951dee1ad47SJeff Kirsher #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 952dee1ad47SJeff Kirsher #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 953dee1ad47SJeff Kirsher #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 954dee1ad47SJeff Kirsher #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 955dee1ad47SJeff Kirsher #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 956dee1ad47SJeff Kirsher #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 957dee1ad47SJeff Kirsher #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 958dee1ad47SJeff Kirsher #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 959dee1ad47SJeff Kirsher #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 960dee1ad47SJeff Kirsher #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 961dee1ad47SJeff Kirsher #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 962dee1ad47SJeff Kirsher #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 963dee1ad47SJeff Kirsher #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 964dee1ad47SJeff Kirsher #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 965dee1ad47SJeff Kirsher #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 966dee1ad47SJeff Kirsher #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 967dee1ad47SJeff Kirsher #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 968dee1ad47SJeff Kirsher #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 969dee1ad47SJeff Kirsher #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 970dee1ad47SJeff Kirsher #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 971dee1ad47SJeff Kirsher #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 972dee1ad47SJeff Kirsher #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 973dee1ad47SJeff Kirsher #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ 974dee1ad47SJeff Kirsher #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ 975dee1ad47SJeff Kirsher #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ 976dee1ad47SJeff Kirsher #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ 977dee1ad47SJeff Kirsher #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 978dee1ad47SJeff Kirsher #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ 979dee1ad47SJeff Kirsher #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 980dee1ad47SJeff Kirsher #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 981dee1ad47SJeff Kirsher #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 982dee1ad47SJeff Kirsher #define E1000_RFCTL 0x05008 /* Receive Filter Control */ 983dee1ad47SJeff Kirsher #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 984dee1ad47SJeff Kirsher #define E1000_RA 0x05400 /* Receive Address - RW Array */ 985dee1ad47SJeff Kirsher #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 986dee1ad47SJeff Kirsher #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 987dee1ad47SJeff Kirsher #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 988dee1ad47SJeff Kirsher #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 989dee1ad47SJeff Kirsher #define E1000_MANC 0x05820 /* Management Control - RW */ 990dee1ad47SJeff Kirsher #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 991dee1ad47SJeff Kirsher #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 992dee1ad47SJeff Kirsher #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 993dee1ad47SJeff Kirsher #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 994dee1ad47SJeff Kirsher #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 995dee1ad47SJeff Kirsher #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 996dee1ad47SJeff Kirsher #define E1000_HOST_IF 0x08800 /* Host Interface */ 997dee1ad47SJeff Kirsher #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 998dee1ad47SJeff Kirsher #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 999dee1ad47SJeff Kirsher 1000dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 1001dee1ad47SJeff Kirsher #define E1000_MDPHYA 0x0003C /* PHY address - RW */ 1002dee1ad47SJeff Kirsher #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 1003dee1ad47SJeff Kirsher #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 1004dee1ad47SJeff Kirsher 1005dee1ad47SJeff Kirsher #define E1000_GCR 0x05B00 /* PCI-Ex Control */ 1006dee1ad47SJeff Kirsher #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 1007dee1ad47SJeff Kirsher #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 1008dee1ad47SJeff Kirsher #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 1009dee1ad47SJeff Kirsher #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 1010dee1ad47SJeff Kirsher #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 1011dee1ad47SJeff Kirsher #define E1000_SWSM 0x05B50 /* SW Semaphore */ 1012dee1ad47SJeff Kirsher #define E1000_FWSM 0x05B54 /* FW Semaphore */ 1013dee1ad47SJeff Kirsher #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 1014dee1ad47SJeff Kirsher #define E1000_HICR 0x08F00 /* Host Interface Control */ 1015dee1ad47SJeff Kirsher 1016dee1ad47SJeff Kirsher /* RSS registers */ 1017dee1ad47SJeff Kirsher #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 1018dee1ad47SJeff Kirsher #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 1019dee1ad47SJeff Kirsher #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ 1020dee1ad47SJeff Kirsher #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ 1021dee1ad47SJeff Kirsher #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ 1022dee1ad47SJeff Kirsher #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ 1023dee1ad47SJeff Kirsher /* Register Set (82542) 1024dee1ad47SJeff Kirsher * 1025dee1ad47SJeff Kirsher * Some of the 82542 registers are located at different offsets than they are 1026dee1ad47SJeff Kirsher * in more current versions of the 8254x. Despite the difference in location, 1027dee1ad47SJeff Kirsher * the registers function in the same manner. 1028dee1ad47SJeff Kirsher */ 1029dee1ad47SJeff Kirsher #define E1000_82542_CTL_AUX E1000_CTL_AUX 1030dee1ad47SJeff Kirsher #define E1000_82542_CTRL E1000_CTRL 1031dee1ad47SJeff Kirsher #define E1000_82542_CTRL_DUP E1000_CTRL_DUP 1032dee1ad47SJeff Kirsher #define E1000_82542_STATUS E1000_STATUS 1033dee1ad47SJeff Kirsher #define E1000_82542_EECD E1000_EECD 1034dee1ad47SJeff Kirsher #define E1000_82542_EERD E1000_EERD 1035dee1ad47SJeff Kirsher #define E1000_82542_CTRL_EXT E1000_CTRL_EXT 1036dee1ad47SJeff Kirsher #define E1000_82542_FLA E1000_FLA 1037dee1ad47SJeff Kirsher #define E1000_82542_MDIC E1000_MDIC 1038dee1ad47SJeff Kirsher #define E1000_82542_SCTL E1000_SCTL 1039dee1ad47SJeff Kirsher #define E1000_82542_FEXTNVM E1000_FEXTNVM 1040dee1ad47SJeff Kirsher #define E1000_82542_FCAL E1000_FCAL 1041dee1ad47SJeff Kirsher #define E1000_82542_FCAH E1000_FCAH 1042dee1ad47SJeff Kirsher #define E1000_82542_FCT E1000_FCT 1043dee1ad47SJeff Kirsher #define E1000_82542_VET E1000_VET 1044dee1ad47SJeff Kirsher #define E1000_82542_RA 0x00040 1045dee1ad47SJeff Kirsher #define E1000_82542_ICR E1000_ICR 1046dee1ad47SJeff Kirsher #define E1000_82542_ITR E1000_ITR 1047dee1ad47SJeff Kirsher #define E1000_82542_ICS E1000_ICS 1048dee1ad47SJeff Kirsher #define E1000_82542_IMS E1000_IMS 1049dee1ad47SJeff Kirsher #define E1000_82542_IMC E1000_IMC 1050dee1ad47SJeff Kirsher #define E1000_82542_RCTL E1000_RCTL 1051dee1ad47SJeff Kirsher #define E1000_82542_RDTR 0x00108 1052b04e36baSTushar Dave #define E1000_82542_RDFH E1000_RDFH 1053b04e36baSTushar Dave #define E1000_82542_RDFT E1000_RDFT 1054b04e36baSTushar Dave #define E1000_82542_RDFHS E1000_RDFHS 1055b04e36baSTushar Dave #define E1000_82542_RDFTS E1000_RDFTS 1056b04e36baSTushar Dave #define E1000_82542_RDFPC E1000_RDFPC 1057dee1ad47SJeff Kirsher #define E1000_82542_RDBAL 0x00110 1058dee1ad47SJeff Kirsher #define E1000_82542_RDBAH 0x00114 1059dee1ad47SJeff Kirsher #define E1000_82542_RDLEN 0x00118 1060dee1ad47SJeff Kirsher #define E1000_82542_RDH 0x00120 1061dee1ad47SJeff Kirsher #define E1000_82542_RDT 0x00128 1062dee1ad47SJeff Kirsher #define E1000_82542_RDTR0 E1000_82542_RDTR 1063dee1ad47SJeff Kirsher #define E1000_82542_RDBAL0 E1000_82542_RDBAL 1064dee1ad47SJeff Kirsher #define E1000_82542_RDBAH0 E1000_82542_RDBAH 1065dee1ad47SJeff Kirsher #define E1000_82542_RDLEN0 E1000_82542_RDLEN 1066dee1ad47SJeff Kirsher #define E1000_82542_RDH0 E1000_82542_RDH 1067dee1ad47SJeff Kirsher #define E1000_82542_RDT0 E1000_82542_RDT 1068dee1ad47SJeff Kirsher #define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication 1069dee1ad47SJeff Kirsher * RX Control - RW */ 1070dee1ad47SJeff Kirsher #define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) 1071dee1ad47SJeff Kirsher #define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ 1072dee1ad47SJeff Kirsher #define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ 1073dee1ad47SJeff Kirsher #define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ 1074dee1ad47SJeff Kirsher #define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ 1075dee1ad47SJeff Kirsher #define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ 1076dee1ad47SJeff Kirsher #define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ 1077dee1ad47SJeff Kirsher #define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ 1078dee1ad47SJeff Kirsher #define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ 1079dee1ad47SJeff Kirsher #define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ 1080dee1ad47SJeff Kirsher #define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ 1081dee1ad47SJeff Kirsher #define E1000_82542_RDTR1 0x00130 1082dee1ad47SJeff Kirsher #define E1000_82542_RDBAL1 0x00138 1083dee1ad47SJeff Kirsher #define E1000_82542_RDBAH1 0x0013C 1084dee1ad47SJeff Kirsher #define E1000_82542_RDLEN1 0x00140 1085dee1ad47SJeff Kirsher #define E1000_82542_RDH1 0x00148 1086dee1ad47SJeff Kirsher #define E1000_82542_RDT1 0x00150 1087dee1ad47SJeff Kirsher #define E1000_82542_FCRTH 0x00160 1088dee1ad47SJeff Kirsher #define E1000_82542_FCRTL 0x00168 1089dee1ad47SJeff Kirsher #define E1000_82542_FCTTV E1000_FCTTV 1090dee1ad47SJeff Kirsher #define E1000_82542_TXCW E1000_TXCW 1091dee1ad47SJeff Kirsher #define E1000_82542_RXCW E1000_RXCW 1092dee1ad47SJeff Kirsher #define E1000_82542_MTA 0x00200 1093dee1ad47SJeff Kirsher #define E1000_82542_TCTL E1000_TCTL 1094dee1ad47SJeff Kirsher #define E1000_82542_TCTL_EXT E1000_TCTL_EXT 1095dee1ad47SJeff Kirsher #define E1000_82542_TIPG E1000_TIPG 1096dee1ad47SJeff Kirsher #define E1000_82542_TDBAL 0x00420 1097dee1ad47SJeff Kirsher #define E1000_82542_TDBAH 0x00424 1098dee1ad47SJeff Kirsher #define E1000_82542_TDLEN 0x00428 1099dee1ad47SJeff Kirsher #define E1000_82542_TDH 0x00430 1100dee1ad47SJeff Kirsher #define E1000_82542_TDT 0x00438 1101dee1ad47SJeff Kirsher #define E1000_82542_TIDV 0x00440 1102dee1ad47SJeff Kirsher #define E1000_82542_TBT E1000_TBT 1103dee1ad47SJeff Kirsher #define E1000_82542_AIT E1000_AIT 1104dee1ad47SJeff Kirsher #define E1000_82542_VFTA 0x00600 1105dee1ad47SJeff Kirsher #define E1000_82542_LEDCTL E1000_LEDCTL 1106dee1ad47SJeff Kirsher #define E1000_82542_PBA E1000_PBA 1107dee1ad47SJeff Kirsher #define E1000_82542_PBS E1000_PBS 1108dee1ad47SJeff Kirsher #define E1000_82542_EEMNGCTL E1000_EEMNGCTL 1109dee1ad47SJeff Kirsher #define E1000_82542_EEARBC E1000_EEARBC 1110dee1ad47SJeff Kirsher #define E1000_82542_FLASHT E1000_FLASHT 1111dee1ad47SJeff Kirsher #define E1000_82542_EEWR E1000_EEWR 1112dee1ad47SJeff Kirsher #define E1000_82542_FLSWCTL E1000_FLSWCTL 1113dee1ad47SJeff Kirsher #define E1000_82542_FLSWDATA E1000_FLSWDATA 1114dee1ad47SJeff Kirsher #define E1000_82542_FLSWCNT E1000_FLSWCNT 1115dee1ad47SJeff Kirsher #define E1000_82542_FLOP E1000_FLOP 1116dee1ad47SJeff Kirsher #define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL 1117dee1ad47SJeff Kirsher #define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE 1118dee1ad47SJeff Kirsher #define E1000_82542_PHY_CTRL E1000_PHY_CTRL 1119dee1ad47SJeff Kirsher #define E1000_82542_ERT E1000_ERT 1120dee1ad47SJeff Kirsher #define E1000_82542_RXDCTL E1000_RXDCTL 1121dee1ad47SJeff Kirsher #define E1000_82542_RXDCTL1 E1000_RXDCTL1 1122dee1ad47SJeff Kirsher #define E1000_82542_RADV E1000_RADV 1123dee1ad47SJeff Kirsher #define E1000_82542_RSRPD E1000_RSRPD 1124dee1ad47SJeff Kirsher #define E1000_82542_TXDMAC E1000_TXDMAC 1125dee1ad47SJeff Kirsher #define E1000_82542_KABGTXD E1000_KABGTXD 1126dee1ad47SJeff Kirsher #define E1000_82542_TDFHS E1000_TDFHS 1127dee1ad47SJeff Kirsher #define E1000_82542_TDFTS E1000_TDFTS 1128dee1ad47SJeff Kirsher #define E1000_82542_TDFPC E1000_TDFPC 1129dee1ad47SJeff Kirsher #define E1000_82542_TXDCTL E1000_TXDCTL 1130dee1ad47SJeff Kirsher #define E1000_82542_TADV E1000_TADV 1131dee1ad47SJeff Kirsher #define E1000_82542_TSPMT E1000_TSPMT 1132dee1ad47SJeff Kirsher #define E1000_82542_CRCERRS E1000_CRCERRS 1133dee1ad47SJeff Kirsher #define E1000_82542_ALGNERRC E1000_ALGNERRC 1134dee1ad47SJeff Kirsher #define E1000_82542_SYMERRS E1000_SYMERRS 1135dee1ad47SJeff Kirsher #define E1000_82542_RXERRC E1000_RXERRC 1136dee1ad47SJeff Kirsher #define E1000_82542_MPC E1000_MPC 1137dee1ad47SJeff Kirsher #define E1000_82542_SCC E1000_SCC 1138dee1ad47SJeff Kirsher #define E1000_82542_ECOL E1000_ECOL 1139dee1ad47SJeff Kirsher #define E1000_82542_MCC E1000_MCC 1140dee1ad47SJeff Kirsher #define E1000_82542_LATECOL E1000_LATECOL 1141dee1ad47SJeff Kirsher #define E1000_82542_COLC E1000_COLC 1142dee1ad47SJeff Kirsher #define E1000_82542_DC E1000_DC 1143dee1ad47SJeff Kirsher #define E1000_82542_TNCRS E1000_TNCRS 1144dee1ad47SJeff Kirsher #define E1000_82542_SEC E1000_SEC 1145dee1ad47SJeff Kirsher #define E1000_82542_CEXTERR E1000_CEXTERR 1146dee1ad47SJeff Kirsher #define E1000_82542_RLEC E1000_RLEC 1147dee1ad47SJeff Kirsher #define E1000_82542_XONRXC E1000_XONRXC 1148dee1ad47SJeff Kirsher #define E1000_82542_XONTXC E1000_XONTXC 1149dee1ad47SJeff Kirsher #define E1000_82542_XOFFRXC E1000_XOFFRXC 1150dee1ad47SJeff Kirsher #define E1000_82542_XOFFTXC E1000_XOFFTXC 1151dee1ad47SJeff Kirsher #define E1000_82542_FCRUC E1000_FCRUC 1152dee1ad47SJeff Kirsher #define E1000_82542_PRC64 E1000_PRC64 1153dee1ad47SJeff Kirsher #define E1000_82542_PRC127 E1000_PRC127 1154dee1ad47SJeff Kirsher #define E1000_82542_PRC255 E1000_PRC255 1155dee1ad47SJeff Kirsher #define E1000_82542_PRC511 E1000_PRC511 1156dee1ad47SJeff Kirsher #define E1000_82542_PRC1023 E1000_PRC1023 1157dee1ad47SJeff Kirsher #define E1000_82542_PRC1522 E1000_PRC1522 1158dee1ad47SJeff Kirsher #define E1000_82542_GPRC E1000_GPRC 1159dee1ad47SJeff Kirsher #define E1000_82542_BPRC E1000_BPRC 1160dee1ad47SJeff Kirsher #define E1000_82542_MPRC E1000_MPRC 1161dee1ad47SJeff Kirsher #define E1000_82542_GPTC E1000_GPTC 1162dee1ad47SJeff Kirsher #define E1000_82542_GORCL E1000_GORCL 1163dee1ad47SJeff Kirsher #define E1000_82542_GORCH E1000_GORCH 1164dee1ad47SJeff Kirsher #define E1000_82542_GOTCL E1000_GOTCL 1165dee1ad47SJeff Kirsher #define E1000_82542_GOTCH E1000_GOTCH 1166dee1ad47SJeff Kirsher #define E1000_82542_RNBC E1000_RNBC 1167dee1ad47SJeff Kirsher #define E1000_82542_RUC E1000_RUC 1168dee1ad47SJeff Kirsher #define E1000_82542_RFC E1000_RFC 1169dee1ad47SJeff Kirsher #define E1000_82542_ROC E1000_ROC 1170dee1ad47SJeff Kirsher #define E1000_82542_RJC E1000_RJC 1171dee1ad47SJeff Kirsher #define E1000_82542_MGTPRC E1000_MGTPRC 1172dee1ad47SJeff Kirsher #define E1000_82542_MGTPDC E1000_MGTPDC 1173dee1ad47SJeff Kirsher #define E1000_82542_MGTPTC E1000_MGTPTC 1174dee1ad47SJeff Kirsher #define E1000_82542_TORL E1000_TORL 1175dee1ad47SJeff Kirsher #define E1000_82542_TORH E1000_TORH 1176dee1ad47SJeff Kirsher #define E1000_82542_TOTL E1000_TOTL 1177dee1ad47SJeff Kirsher #define E1000_82542_TOTH E1000_TOTH 1178dee1ad47SJeff Kirsher #define E1000_82542_TPR E1000_TPR 1179dee1ad47SJeff Kirsher #define E1000_82542_TPT E1000_TPT 1180dee1ad47SJeff Kirsher #define E1000_82542_PTC64 E1000_PTC64 1181dee1ad47SJeff Kirsher #define E1000_82542_PTC127 E1000_PTC127 1182dee1ad47SJeff Kirsher #define E1000_82542_PTC255 E1000_PTC255 1183dee1ad47SJeff Kirsher #define E1000_82542_PTC511 E1000_PTC511 1184dee1ad47SJeff Kirsher #define E1000_82542_PTC1023 E1000_PTC1023 1185dee1ad47SJeff Kirsher #define E1000_82542_PTC1522 E1000_PTC1522 1186dee1ad47SJeff Kirsher #define E1000_82542_MPTC E1000_MPTC 1187dee1ad47SJeff Kirsher #define E1000_82542_BPTC E1000_BPTC 1188dee1ad47SJeff Kirsher #define E1000_82542_TSCTC E1000_TSCTC 1189dee1ad47SJeff Kirsher #define E1000_82542_TSCTFC E1000_TSCTFC 1190dee1ad47SJeff Kirsher #define E1000_82542_RXCSUM E1000_RXCSUM 1191dee1ad47SJeff Kirsher #define E1000_82542_WUC E1000_WUC 1192dee1ad47SJeff Kirsher #define E1000_82542_WUFC E1000_WUFC 1193dee1ad47SJeff Kirsher #define E1000_82542_WUS E1000_WUS 1194dee1ad47SJeff Kirsher #define E1000_82542_MANC E1000_MANC 1195dee1ad47SJeff Kirsher #define E1000_82542_IPAV E1000_IPAV 1196dee1ad47SJeff Kirsher #define E1000_82542_IP4AT E1000_IP4AT 1197dee1ad47SJeff Kirsher #define E1000_82542_IP6AT E1000_IP6AT 1198dee1ad47SJeff Kirsher #define E1000_82542_WUPL E1000_WUPL 1199dee1ad47SJeff Kirsher #define E1000_82542_WUPM E1000_WUPM 1200dee1ad47SJeff Kirsher #define E1000_82542_FFLT E1000_FFLT 1201dee1ad47SJeff Kirsher #define E1000_82542_TDFH 0x08010 1202dee1ad47SJeff Kirsher #define E1000_82542_TDFT 0x08018 1203dee1ad47SJeff Kirsher #define E1000_82542_FFMT E1000_FFMT 1204dee1ad47SJeff Kirsher #define E1000_82542_FFVT E1000_FFVT 1205dee1ad47SJeff Kirsher #define E1000_82542_HOST_IF E1000_HOST_IF 1206dee1ad47SJeff Kirsher #define E1000_82542_IAM E1000_IAM 1207dee1ad47SJeff Kirsher #define E1000_82542_EEMNGCTL E1000_EEMNGCTL 1208dee1ad47SJeff Kirsher #define E1000_82542_PSRCTL E1000_PSRCTL 1209dee1ad47SJeff Kirsher #define E1000_82542_RAID E1000_RAID 1210dee1ad47SJeff Kirsher #define E1000_82542_TARC0 E1000_TARC0 1211dee1ad47SJeff Kirsher #define E1000_82542_TDBAL1 E1000_TDBAL1 1212dee1ad47SJeff Kirsher #define E1000_82542_TDBAH1 E1000_TDBAH1 1213dee1ad47SJeff Kirsher #define E1000_82542_TDLEN1 E1000_TDLEN1 1214dee1ad47SJeff Kirsher #define E1000_82542_TDH1 E1000_TDH1 1215dee1ad47SJeff Kirsher #define E1000_82542_TDT1 E1000_TDT1 1216dee1ad47SJeff Kirsher #define E1000_82542_TXDCTL1 E1000_TXDCTL1 1217dee1ad47SJeff Kirsher #define E1000_82542_TARC1 E1000_TARC1 1218dee1ad47SJeff Kirsher #define E1000_82542_RFCTL E1000_RFCTL 1219dee1ad47SJeff Kirsher #define E1000_82542_GCR E1000_GCR 1220dee1ad47SJeff Kirsher #define E1000_82542_GSCL_1 E1000_GSCL_1 1221dee1ad47SJeff Kirsher #define E1000_82542_GSCL_2 E1000_GSCL_2 1222dee1ad47SJeff Kirsher #define E1000_82542_GSCL_3 E1000_GSCL_3 1223dee1ad47SJeff Kirsher #define E1000_82542_GSCL_4 E1000_GSCL_4 1224dee1ad47SJeff Kirsher #define E1000_82542_FACTPS E1000_FACTPS 1225dee1ad47SJeff Kirsher #define E1000_82542_SWSM E1000_SWSM 1226dee1ad47SJeff Kirsher #define E1000_82542_FWSM E1000_FWSM 1227dee1ad47SJeff Kirsher #define E1000_82542_FFLT_DBG E1000_FFLT_DBG 1228dee1ad47SJeff Kirsher #define E1000_82542_IAC E1000_IAC 1229dee1ad47SJeff Kirsher #define E1000_82542_ICRXPTC E1000_ICRXPTC 1230dee1ad47SJeff Kirsher #define E1000_82542_ICRXATC E1000_ICRXATC 1231dee1ad47SJeff Kirsher #define E1000_82542_ICTXPTC E1000_ICTXPTC 1232dee1ad47SJeff Kirsher #define E1000_82542_ICTXATC E1000_ICTXATC 1233dee1ad47SJeff Kirsher #define E1000_82542_ICTXQEC E1000_ICTXQEC 1234dee1ad47SJeff Kirsher #define E1000_82542_ICTXQMTC E1000_ICTXQMTC 1235dee1ad47SJeff Kirsher #define E1000_82542_ICRXDMTC E1000_ICRXDMTC 1236dee1ad47SJeff Kirsher #define E1000_82542_ICRXOC E1000_ICRXOC 1237dee1ad47SJeff Kirsher #define E1000_82542_HICR E1000_HICR 1238dee1ad47SJeff Kirsher 1239dee1ad47SJeff Kirsher #define E1000_82542_CPUVEC E1000_CPUVEC 1240dee1ad47SJeff Kirsher #define E1000_82542_MRQC E1000_MRQC 1241dee1ad47SJeff Kirsher #define E1000_82542_RETA E1000_RETA 1242dee1ad47SJeff Kirsher #define E1000_82542_RSSRK E1000_RSSRK 1243dee1ad47SJeff Kirsher #define E1000_82542_RSSIM E1000_RSSIM 1244dee1ad47SJeff Kirsher #define E1000_82542_RSSIR E1000_RSSIR 1245dee1ad47SJeff Kirsher #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA 1246dee1ad47SJeff Kirsher #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC 1247dee1ad47SJeff Kirsher 1248dee1ad47SJeff Kirsher /* Statistics counters collected by the MAC */ 1249dee1ad47SJeff Kirsher struct e1000_hw_stats { 1250dee1ad47SJeff Kirsher u64 crcerrs; 1251dee1ad47SJeff Kirsher u64 algnerrc; 1252dee1ad47SJeff Kirsher u64 symerrs; 1253dee1ad47SJeff Kirsher u64 rxerrc; 1254dee1ad47SJeff Kirsher u64 txerrc; 1255dee1ad47SJeff Kirsher u64 mpc; 1256dee1ad47SJeff Kirsher u64 scc; 1257dee1ad47SJeff Kirsher u64 ecol; 1258dee1ad47SJeff Kirsher u64 mcc; 1259dee1ad47SJeff Kirsher u64 latecol; 1260dee1ad47SJeff Kirsher u64 colc; 1261dee1ad47SJeff Kirsher u64 dc; 1262dee1ad47SJeff Kirsher u64 tncrs; 1263dee1ad47SJeff Kirsher u64 sec; 1264dee1ad47SJeff Kirsher u64 cexterr; 1265dee1ad47SJeff Kirsher u64 rlec; 1266dee1ad47SJeff Kirsher u64 xonrxc; 1267dee1ad47SJeff Kirsher u64 xontxc; 1268dee1ad47SJeff Kirsher u64 xoffrxc; 1269dee1ad47SJeff Kirsher u64 xofftxc; 1270dee1ad47SJeff Kirsher u64 fcruc; 1271dee1ad47SJeff Kirsher u64 prc64; 1272dee1ad47SJeff Kirsher u64 prc127; 1273dee1ad47SJeff Kirsher u64 prc255; 1274dee1ad47SJeff Kirsher u64 prc511; 1275dee1ad47SJeff Kirsher u64 prc1023; 1276dee1ad47SJeff Kirsher u64 prc1522; 1277dee1ad47SJeff Kirsher u64 gprc; 1278dee1ad47SJeff Kirsher u64 bprc; 1279dee1ad47SJeff Kirsher u64 mprc; 1280dee1ad47SJeff Kirsher u64 gptc; 1281dee1ad47SJeff Kirsher u64 gorcl; 1282dee1ad47SJeff Kirsher u64 gorch; 1283dee1ad47SJeff Kirsher u64 gotcl; 1284dee1ad47SJeff Kirsher u64 gotch; 1285dee1ad47SJeff Kirsher u64 rnbc; 1286dee1ad47SJeff Kirsher u64 ruc; 1287dee1ad47SJeff Kirsher u64 rfc; 1288dee1ad47SJeff Kirsher u64 roc; 1289dee1ad47SJeff Kirsher u64 rlerrc; 1290dee1ad47SJeff Kirsher u64 rjc; 1291dee1ad47SJeff Kirsher u64 mgprc; 1292dee1ad47SJeff Kirsher u64 mgpdc; 1293dee1ad47SJeff Kirsher u64 mgptc; 1294dee1ad47SJeff Kirsher u64 torl; 1295dee1ad47SJeff Kirsher u64 torh; 1296dee1ad47SJeff Kirsher u64 totl; 1297dee1ad47SJeff Kirsher u64 toth; 1298dee1ad47SJeff Kirsher u64 tpr; 1299dee1ad47SJeff Kirsher u64 tpt; 1300dee1ad47SJeff Kirsher u64 ptc64; 1301dee1ad47SJeff Kirsher u64 ptc127; 1302dee1ad47SJeff Kirsher u64 ptc255; 1303dee1ad47SJeff Kirsher u64 ptc511; 1304dee1ad47SJeff Kirsher u64 ptc1023; 1305dee1ad47SJeff Kirsher u64 ptc1522; 1306dee1ad47SJeff Kirsher u64 mptc; 1307dee1ad47SJeff Kirsher u64 bptc; 1308dee1ad47SJeff Kirsher u64 tsctc; 1309dee1ad47SJeff Kirsher u64 tsctfc; 1310dee1ad47SJeff Kirsher u64 iac; 1311dee1ad47SJeff Kirsher u64 icrxptc; 1312dee1ad47SJeff Kirsher u64 icrxatc; 1313dee1ad47SJeff Kirsher u64 ictxptc; 1314dee1ad47SJeff Kirsher u64 ictxatc; 1315dee1ad47SJeff Kirsher u64 ictxqec; 1316dee1ad47SJeff Kirsher u64 ictxqmtc; 1317dee1ad47SJeff Kirsher u64 icrxdmtc; 1318dee1ad47SJeff Kirsher u64 icrxoc; 1319dee1ad47SJeff Kirsher }; 1320dee1ad47SJeff Kirsher 1321dee1ad47SJeff Kirsher /* Structure containing variables used by the shared code (e1000_hw.c) */ 1322dee1ad47SJeff Kirsher struct e1000_hw { 1323dee1ad47SJeff Kirsher u8 __iomem *hw_addr; 1324dee1ad47SJeff Kirsher u8 __iomem *flash_address; 132513acde8fSFlorian Fainelli void __iomem *ce4100_gbe_mdio_base_virt; 1326dee1ad47SJeff Kirsher e1000_mac_type mac_type; 1327dee1ad47SJeff Kirsher e1000_phy_type phy_type; 1328dee1ad47SJeff Kirsher u32 phy_init_script; 1329dee1ad47SJeff Kirsher e1000_media_type media_type; 1330dee1ad47SJeff Kirsher void *back; 1331dee1ad47SJeff Kirsher struct e1000_shadow_ram *eeprom_shadow_ram; 1332dee1ad47SJeff Kirsher u32 flash_bank_size; 1333dee1ad47SJeff Kirsher u32 flash_base_addr; 1334dee1ad47SJeff Kirsher e1000_fc_type fc; 1335dee1ad47SJeff Kirsher e1000_bus_speed bus_speed; 1336dee1ad47SJeff Kirsher e1000_bus_width bus_width; 1337dee1ad47SJeff Kirsher e1000_bus_type bus_type; 1338dee1ad47SJeff Kirsher struct e1000_eeprom_info eeprom; 1339dee1ad47SJeff Kirsher e1000_ms_type master_slave; 1340dee1ad47SJeff Kirsher e1000_ms_type original_master_slave; 1341dee1ad47SJeff Kirsher e1000_ffe_config ffe_config_state; 1342dee1ad47SJeff Kirsher u32 asf_firmware_present; 1343dee1ad47SJeff Kirsher u32 eeprom_semaphore_present; 1344dee1ad47SJeff Kirsher unsigned long io_base; 1345dee1ad47SJeff Kirsher u32 phy_id; 1346dee1ad47SJeff Kirsher u32 phy_revision; 1347dee1ad47SJeff Kirsher u32 phy_addr; 1348dee1ad47SJeff Kirsher u32 original_fc; 1349dee1ad47SJeff Kirsher u32 txcw; 1350dee1ad47SJeff Kirsher u32 autoneg_failed; 1351dee1ad47SJeff Kirsher u32 max_frame_size; 1352dee1ad47SJeff Kirsher u32 min_frame_size; 1353dee1ad47SJeff Kirsher u32 mc_filter_type; 1354dee1ad47SJeff Kirsher u32 num_mc_addrs; 1355dee1ad47SJeff Kirsher u32 collision_delta; 1356dee1ad47SJeff Kirsher u32 tx_packet_delta; 1357dee1ad47SJeff Kirsher u32 ledctl_default; 1358dee1ad47SJeff Kirsher u32 ledctl_mode1; 1359dee1ad47SJeff Kirsher u32 ledctl_mode2; 1360dee1ad47SJeff Kirsher bool tx_pkt_filtering; 1361dee1ad47SJeff Kirsher struct e1000_host_mng_dhcp_cookie mng_cookie; 1362dee1ad47SJeff Kirsher u16 phy_spd_default; 1363dee1ad47SJeff Kirsher u16 autoneg_advertised; 1364dee1ad47SJeff Kirsher u16 pci_cmd_word; 1365dee1ad47SJeff Kirsher u16 fc_high_water; 1366dee1ad47SJeff Kirsher u16 fc_low_water; 1367dee1ad47SJeff Kirsher u16 fc_pause_time; 1368dee1ad47SJeff Kirsher u16 current_ifs_val; 1369dee1ad47SJeff Kirsher u16 ifs_min_val; 1370dee1ad47SJeff Kirsher u16 ifs_max_val; 1371dee1ad47SJeff Kirsher u16 ifs_step_size; 1372dee1ad47SJeff Kirsher u16 ifs_ratio; 1373dee1ad47SJeff Kirsher u16 device_id; 1374dee1ad47SJeff Kirsher u16 vendor_id; 1375dee1ad47SJeff Kirsher u16 subsystem_id; 1376dee1ad47SJeff Kirsher u16 subsystem_vendor_id; 1377dee1ad47SJeff Kirsher u8 revision_id; 1378dee1ad47SJeff Kirsher u8 autoneg; 1379dee1ad47SJeff Kirsher u8 mdix; 1380dee1ad47SJeff Kirsher u8 forced_speed_duplex; 1381dee1ad47SJeff Kirsher u8 wait_autoneg_complete; 1382dee1ad47SJeff Kirsher u8 dma_fairness; 1383dee1ad47SJeff Kirsher u8 mac_addr[NODE_ADDRESS_SIZE]; 1384dee1ad47SJeff Kirsher u8 perm_mac_addr[NODE_ADDRESS_SIZE]; 1385dee1ad47SJeff Kirsher bool disable_polarity_correction; 1386dee1ad47SJeff Kirsher bool speed_downgraded; 1387dee1ad47SJeff Kirsher e1000_smart_speed smart_speed; 1388dee1ad47SJeff Kirsher e1000_dsp_config dsp_config_state; 1389dee1ad47SJeff Kirsher bool get_link_status; 1390dee1ad47SJeff Kirsher bool serdes_has_link; 1391dee1ad47SJeff Kirsher bool tbi_compatibility_en; 1392dee1ad47SJeff Kirsher bool tbi_compatibility_on; 1393dee1ad47SJeff Kirsher bool laa_is_present; 1394dee1ad47SJeff Kirsher bool phy_reset_disable; 1395dee1ad47SJeff Kirsher bool initialize_hw_bits_disable; 1396dee1ad47SJeff Kirsher bool fc_send_xon; 1397dee1ad47SJeff Kirsher bool fc_strict_ieee; 1398dee1ad47SJeff Kirsher bool report_tx_early; 1399dee1ad47SJeff Kirsher bool adaptive_ifs; 1400dee1ad47SJeff Kirsher bool ifs_params_forced; 1401dee1ad47SJeff Kirsher bool in_ifs_mode; 1402dee1ad47SJeff Kirsher bool mng_reg_access_disabled; 1403dee1ad47SJeff Kirsher bool leave_av_bit_off; 1404dee1ad47SJeff Kirsher bool bad_tx_carr_stats_fd; 1405dee1ad47SJeff Kirsher bool has_smbus; 1406dee1ad47SJeff Kirsher }; 1407dee1ad47SJeff Kirsher 1408dee1ad47SJeff Kirsher #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1409dee1ad47SJeff Kirsher #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1410dee1ad47SJeff Kirsher #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ 1411dee1ad47SJeff Kirsher #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1412dee1ad47SJeff Kirsher #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ 1413dee1ad47SJeff Kirsher #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1414dee1ad47SJeff Kirsher #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ 1415dee1ad47SJeff Kirsher #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ 1416dee1ad47SJeff Kirsher /* Register Bit Masks */ 1417dee1ad47SJeff Kirsher /* Device Control */ 1418dee1ad47SJeff Kirsher #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1419dee1ad47SJeff Kirsher #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1420dee1ad47SJeff Kirsher #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1421dee1ad47SJeff Kirsher #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 1422dee1ad47SJeff Kirsher #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1423dee1ad47SJeff Kirsher #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1424dee1ad47SJeff Kirsher #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1425dee1ad47SJeff Kirsher #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 1426dee1ad47SJeff Kirsher #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 1427dee1ad47SJeff Kirsher #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 1428dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 1429dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 1430dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 1431dee1ad47SJeff Kirsher #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 1432dee1ad47SJeff Kirsher #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1433dee1ad47SJeff Kirsher #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1434dee1ad47SJeff Kirsher #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1435dee1ad47SJeff Kirsher #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 1436dee1ad47SJeff Kirsher #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 1437dee1ad47SJeff Kirsher #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 1438dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ 1439dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1440dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1441dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1442dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 1443dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 1444dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 1445dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 1446dee1ad47SJeff Kirsher #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 1447dee1ad47SJeff Kirsher #define E1000_CTRL_RST 0x04000000 /* Global reset */ 1448dee1ad47SJeff Kirsher #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 1449dee1ad47SJeff Kirsher #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 1450dee1ad47SJeff Kirsher #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1451dee1ad47SJeff Kirsher #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1452dee1ad47SJeff Kirsher #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1453dee1ad47SJeff Kirsher #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 1454dee1ad47SJeff Kirsher 1455dee1ad47SJeff Kirsher /* Device Status */ 1456dee1ad47SJeff Kirsher #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1457dee1ad47SJeff Kirsher #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1458dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1459dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_SHIFT 2 1460dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1461dee1ad47SJeff Kirsher #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1462dee1ad47SJeff Kirsher #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1463dee1ad47SJeff Kirsher #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 1464dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_MASK 0x000000C0 1465dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1466dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1467dee1ad47SJeff Kirsher #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1468dee1ad47SJeff Kirsher #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion 1469dee1ad47SJeff Kirsher by EEPROM/Flash */ 1470dee1ad47SJeff Kirsher #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1471dee1ad47SJeff Kirsher #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1472dee1ad47SJeff Kirsher #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1473dee1ad47SJeff Kirsher #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1474dee1ad47SJeff Kirsher #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1475dee1ad47SJeff Kirsher #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1476dee1ad47SJeff Kirsher #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 1477dee1ad47SJeff Kirsher #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 1478dee1ad47SJeff Kirsher #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 1479dee1ad47SJeff Kirsher #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 1480dee1ad47SJeff Kirsher #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 1481dee1ad47SJeff Kirsher #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 1482dee1ad47SJeff Kirsher #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ 1483dee1ad47SJeff Kirsher #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 1484dee1ad47SJeff Kirsher #define E1000_STATUS_FUSE_8 0x04000000 1485dee1ad47SJeff Kirsher #define E1000_STATUS_FUSE_9 0x08000000 1486dee1ad47SJeff Kirsher #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 1487dee1ad47SJeff Kirsher #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 1488dee1ad47SJeff Kirsher 1489dee1ad47SJeff Kirsher /* Constants used to interpret the masked PCI-X bus speed. */ 1490dee1ad47SJeff Kirsher #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 1491dee1ad47SJeff Kirsher #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 1492dee1ad47SJeff Kirsher #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 1493dee1ad47SJeff Kirsher 1494dee1ad47SJeff Kirsher /* EEPROM/Flash Control */ 1495dee1ad47SJeff Kirsher #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 1496dee1ad47SJeff Kirsher #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 1497dee1ad47SJeff Kirsher #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 1498dee1ad47SJeff Kirsher #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 1499dee1ad47SJeff Kirsher #define E1000_EECD_FWE_MASK 0x00000030 1500dee1ad47SJeff Kirsher #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1501dee1ad47SJeff Kirsher #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1502dee1ad47SJeff Kirsher #define E1000_EECD_FWE_SHIFT 4 1503dee1ad47SJeff Kirsher #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 1504dee1ad47SJeff Kirsher #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 1505dee1ad47SJeff Kirsher #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1506dee1ad47SJeff Kirsher #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 1507dee1ad47SJeff Kirsher #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1508dee1ad47SJeff Kirsher * (0-small, 1-large) */ 1509dee1ad47SJeff Kirsher #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1510dee1ad47SJeff Kirsher #ifndef E1000_EEPROM_GRANT_ATTEMPTS 1511dee1ad47SJeff Kirsher #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1512dee1ad47SJeff Kirsher #endif 1513dee1ad47SJeff Kirsher #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 1514dee1ad47SJeff Kirsher #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 1515dee1ad47SJeff Kirsher #define E1000_EECD_SIZE_EX_SHIFT 11 1516dee1ad47SJeff Kirsher #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1517dee1ad47SJeff Kirsher #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1518dee1ad47SJeff Kirsher #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1519dee1ad47SJeff Kirsher #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1520dee1ad47SJeff Kirsher #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1521dee1ad47SJeff Kirsher #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1522dee1ad47SJeff Kirsher #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1523dee1ad47SJeff Kirsher #define E1000_EECD_SECVAL_SHIFT 22 1524dee1ad47SJeff Kirsher #define E1000_STM_OPCODE 0xDB00 1525dee1ad47SJeff Kirsher #define E1000_HICR_FW_RESET 0xC0 1526dee1ad47SJeff Kirsher 1527dee1ad47SJeff Kirsher #define E1000_SHADOW_RAM_WORDS 2048 1528dee1ad47SJeff Kirsher #define E1000_ICH_NVM_SIG_WORD 0x13 1529dee1ad47SJeff Kirsher #define E1000_ICH_NVM_SIG_MASK 0xC0 1530dee1ad47SJeff Kirsher 1531dee1ad47SJeff Kirsher /* EEPROM Read */ 1532dee1ad47SJeff Kirsher #define E1000_EERD_START 0x00000001 /* Start Read */ 1533dee1ad47SJeff Kirsher #define E1000_EERD_DONE 0x00000010 /* Read Done */ 1534dee1ad47SJeff Kirsher #define E1000_EERD_ADDR_SHIFT 8 1535dee1ad47SJeff Kirsher #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 1536dee1ad47SJeff Kirsher #define E1000_EERD_DATA_SHIFT 16 1537dee1ad47SJeff Kirsher #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 1538dee1ad47SJeff Kirsher 1539dee1ad47SJeff Kirsher /* SPI EEPROM Status Register */ 1540dee1ad47SJeff Kirsher #define EEPROM_STATUS_RDY_SPI 0x01 1541dee1ad47SJeff Kirsher #define EEPROM_STATUS_WEN_SPI 0x02 1542dee1ad47SJeff Kirsher #define EEPROM_STATUS_BP0_SPI 0x04 1543dee1ad47SJeff Kirsher #define EEPROM_STATUS_BP1_SPI 0x08 1544dee1ad47SJeff Kirsher #define EEPROM_STATUS_WPEN_SPI 0x80 1545dee1ad47SJeff Kirsher 1546dee1ad47SJeff Kirsher /* Extended Device Control */ 1547dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 1548dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 1549dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 1550dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 1551dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1552dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 1553dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 1554dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 1555dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 1556dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 1557dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 1558dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 1559dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 1560dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 1561dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 1562dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 1563dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 1564dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1565dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1566dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 1567dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 1568dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 1569dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 1570dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000 1571dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 1572dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 1573dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 1574dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1575dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1576dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1577dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1578dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1579dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1580dee1ad47SJeff Kirsher #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 1581dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 1582dee1ad47SJeff Kirsher #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 1583dee1ad47SJeff Kirsher 1584dee1ad47SJeff Kirsher /* MDI Control */ 1585dee1ad47SJeff Kirsher #define E1000_MDIC_DATA_MASK 0x0000FFFF 1586dee1ad47SJeff Kirsher #define E1000_MDIC_REG_MASK 0x001F0000 1587dee1ad47SJeff Kirsher #define E1000_MDIC_REG_SHIFT 16 1588dee1ad47SJeff Kirsher #define E1000_MDIC_PHY_MASK 0x03E00000 1589dee1ad47SJeff Kirsher #define E1000_MDIC_PHY_SHIFT 21 1590dee1ad47SJeff Kirsher #define E1000_MDIC_OP_WRITE 0x04000000 1591dee1ad47SJeff Kirsher #define E1000_MDIC_OP_READ 0x08000000 1592dee1ad47SJeff Kirsher #define E1000_MDIC_READY 0x10000000 1593dee1ad47SJeff Kirsher #define E1000_MDIC_INT_EN 0x20000000 1594dee1ad47SJeff Kirsher #define E1000_MDIC_ERROR 0x40000000 1595dee1ad47SJeff Kirsher 1596dee1ad47SJeff Kirsher #define INTEL_CE_GBE_MDIC_OP_WRITE 0x04000000 1597dee1ad47SJeff Kirsher #define INTEL_CE_GBE_MDIC_OP_READ 0x00000000 1598dee1ad47SJeff Kirsher #define INTEL_CE_GBE_MDIC_GO 0x80000000 1599dee1ad47SJeff Kirsher #define INTEL_CE_GBE_MDIC_READ_ERROR 0x80000000 1600dee1ad47SJeff Kirsher 1601dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_MASK 0x0000FFFF 1602dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET 0x001F0000 1603dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16 1604dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_REN 0x00200000 1605dee1ad47SJeff Kirsher 1606dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 1607dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 1608dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 1609dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 1610dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 1611dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 1612dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 1613dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E 1614dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F 1615dee1ad47SJeff Kirsher 1616dee1ad47SJeff Kirsher /* FIFO Control */ 1617dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 1618dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 1619dee1ad47SJeff Kirsher 1620dee1ad47SJeff Kirsher /* In-Band Control */ 1621dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500 1622dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 1623dee1ad47SJeff Kirsher 1624dee1ad47SJeff Kirsher /* Half-Duplex Control */ 1625dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 1626dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 1627dee1ad47SJeff Kirsher 1628dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E 1629dee1ad47SJeff Kirsher 1630dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 1631dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 1632dee1ad47SJeff Kirsher 1633dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000 1634dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 1635dee1ad47SJeff Kirsher #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003 1636dee1ad47SJeff Kirsher 1637dee1ad47SJeff Kirsher #define E1000_KABGTXD_BGSQLBIAS 0x00050000 1638dee1ad47SJeff Kirsher 1639dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_SPD_EN 0x00000001 1640dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 1641dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 1642dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 1643dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 1644dee1ad47SJeff Kirsher #define E1000_PHY_CTRL_B2B_EN 0x00000080 1645dee1ad47SJeff Kirsher 1646dee1ad47SJeff Kirsher /* LED Control */ 1647dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1648dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_MODE_SHIFT 0 1649dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020 1650dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_IVRT 0x00000040 1651dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED0_BLINK 0x00000080 1652dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 1653dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED1_MODE_SHIFT 8 1654dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000 1655dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED1_IVRT 0x00004000 1656dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED1_BLINK 0x00008000 1657dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 1658dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED2_MODE_SHIFT 16 1659dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 1660dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED2_IVRT 0x00400000 1661dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED2_BLINK 0x00800000 1662dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 1663dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED3_MODE_SHIFT 24 1664dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 1665dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED3_IVRT 0x40000000 1666dee1ad47SJeff Kirsher #define E1000_LEDCTL_LED3_BLINK 0x80000000 1667dee1ad47SJeff Kirsher 1668dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 1669dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 1670dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_UP 0x2 1671dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_ACTIVITY 0x3 1672dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 1673dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_10 0x5 1674dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_100 0x6 1675dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LINK_1000 0x7 1676dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 1677dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 1678dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_COLLISION 0xA 1679dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 1680dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 1681dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_PAUSED 0xD 1682dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LED_ON 0xE 1683dee1ad47SJeff Kirsher #define E1000_LEDCTL_MODE_LED_OFF 0xF 1684dee1ad47SJeff Kirsher 1685dee1ad47SJeff Kirsher /* Receive Address */ 1686dee1ad47SJeff Kirsher #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1687dee1ad47SJeff Kirsher 1688dee1ad47SJeff Kirsher /* Interrupt Cause Read */ 1689dee1ad47SJeff Kirsher #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1690dee1ad47SJeff Kirsher #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1691dee1ad47SJeff Kirsher #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1692dee1ad47SJeff Kirsher #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1693dee1ad47SJeff Kirsher #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1694dee1ad47SJeff Kirsher #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1695dee1ad47SJeff Kirsher #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1696dee1ad47SJeff Kirsher #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1697dee1ad47SJeff Kirsher #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1698dee1ad47SJeff Kirsher #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1699dee1ad47SJeff Kirsher #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1700dee1ad47SJeff Kirsher #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1701dee1ad47SJeff Kirsher #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1702dee1ad47SJeff Kirsher #define E1000_ICR_TXD_LOW 0x00008000 1703dee1ad47SJeff Kirsher #define E1000_ICR_SRPD 0x00010000 1704dee1ad47SJeff Kirsher #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 1705dee1ad47SJeff Kirsher #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 1706dee1ad47SJeff Kirsher #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 1707dee1ad47SJeff Kirsher #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 1708dee1ad47SJeff Kirsher #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 1709dee1ad47SJeff Kirsher #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 1710dee1ad47SJeff Kirsher #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 1711dee1ad47SJeff Kirsher #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 1712dee1ad47SJeff Kirsher #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1713dee1ad47SJeff Kirsher #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1714dee1ad47SJeff Kirsher #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1715dee1ad47SJeff Kirsher #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 1716dee1ad47SJeff Kirsher #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 1717dee1ad47SJeff Kirsher #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ 1718dee1ad47SJeff Kirsher 1719dee1ad47SJeff Kirsher /* Interrupt Cause Set */ 1720dee1ad47SJeff Kirsher #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1721dee1ad47SJeff Kirsher #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1722dee1ad47SJeff Kirsher #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1723dee1ad47SJeff Kirsher #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1724dee1ad47SJeff Kirsher #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1725dee1ad47SJeff Kirsher #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1726dee1ad47SJeff Kirsher #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1727dee1ad47SJeff Kirsher #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1728dee1ad47SJeff Kirsher #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1729dee1ad47SJeff Kirsher #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1730dee1ad47SJeff Kirsher #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1731dee1ad47SJeff Kirsher #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1732dee1ad47SJeff Kirsher #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1733dee1ad47SJeff Kirsher #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1734dee1ad47SJeff Kirsher #define E1000_ICS_SRPD E1000_ICR_SRPD 1735dee1ad47SJeff Kirsher #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1736dee1ad47SJeff Kirsher #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 1737dee1ad47SJeff Kirsher #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1738dee1ad47SJeff Kirsher #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1739dee1ad47SJeff Kirsher #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1740dee1ad47SJeff Kirsher #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1741dee1ad47SJeff Kirsher #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1742dee1ad47SJeff Kirsher #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1743dee1ad47SJeff Kirsher #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1744dee1ad47SJeff Kirsher #define E1000_ICS_DSW E1000_ICR_DSW 1745dee1ad47SJeff Kirsher #define E1000_ICS_PHYINT E1000_ICR_PHYINT 1746dee1ad47SJeff Kirsher #define E1000_ICS_EPRST E1000_ICR_EPRST 1747dee1ad47SJeff Kirsher 1748dee1ad47SJeff Kirsher /* Interrupt Mask Set */ 1749dee1ad47SJeff Kirsher #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1750dee1ad47SJeff Kirsher #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1751dee1ad47SJeff Kirsher #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1752dee1ad47SJeff Kirsher #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1753dee1ad47SJeff Kirsher #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1754dee1ad47SJeff Kirsher #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1755dee1ad47SJeff Kirsher #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1756dee1ad47SJeff Kirsher #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1757dee1ad47SJeff Kirsher #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1758dee1ad47SJeff Kirsher #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1759dee1ad47SJeff Kirsher #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1760dee1ad47SJeff Kirsher #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1761dee1ad47SJeff Kirsher #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1762dee1ad47SJeff Kirsher #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1763dee1ad47SJeff Kirsher #define E1000_IMS_SRPD E1000_ICR_SRPD 1764dee1ad47SJeff Kirsher #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1765dee1ad47SJeff Kirsher #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 1766dee1ad47SJeff Kirsher #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1767dee1ad47SJeff Kirsher #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1768dee1ad47SJeff Kirsher #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1769dee1ad47SJeff Kirsher #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1770dee1ad47SJeff Kirsher #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1771dee1ad47SJeff Kirsher #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1772dee1ad47SJeff Kirsher #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1773dee1ad47SJeff Kirsher #define E1000_IMS_DSW E1000_ICR_DSW 1774dee1ad47SJeff Kirsher #define E1000_IMS_PHYINT E1000_ICR_PHYINT 1775dee1ad47SJeff Kirsher #define E1000_IMS_EPRST E1000_ICR_EPRST 1776dee1ad47SJeff Kirsher 1777dee1ad47SJeff Kirsher /* Interrupt Mask Clear */ 1778dee1ad47SJeff Kirsher #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1779dee1ad47SJeff Kirsher #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1780dee1ad47SJeff Kirsher #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1781dee1ad47SJeff Kirsher #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1782dee1ad47SJeff Kirsher #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1783dee1ad47SJeff Kirsher #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1784dee1ad47SJeff Kirsher #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1785dee1ad47SJeff Kirsher #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1786dee1ad47SJeff Kirsher #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1787dee1ad47SJeff Kirsher #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1788dee1ad47SJeff Kirsher #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1789dee1ad47SJeff Kirsher #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1790dee1ad47SJeff Kirsher #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1791dee1ad47SJeff Kirsher #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1792dee1ad47SJeff Kirsher #define E1000_IMC_SRPD E1000_ICR_SRPD 1793dee1ad47SJeff Kirsher #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ 1794dee1ad47SJeff Kirsher #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ 1795dee1ad47SJeff Kirsher #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1796dee1ad47SJeff Kirsher #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1797dee1ad47SJeff Kirsher #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1798dee1ad47SJeff Kirsher #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1799dee1ad47SJeff Kirsher #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1800dee1ad47SJeff Kirsher #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1801dee1ad47SJeff Kirsher #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1802dee1ad47SJeff Kirsher #define E1000_IMC_DSW E1000_ICR_DSW 1803dee1ad47SJeff Kirsher #define E1000_IMC_PHYINT E1000_ICR_PHYINT 1804dee1ad47SJeff Kirsher #define E1000_IMC_EPRST E1000_ICR_EPRST 1805dee1ad47SJeff Kirsher 1806dee1ad47SJeff Kirsher /* Receive Control */ 1807dee1ad47SJeff Kirsher #define E1000_RCTL_RST 0x00000001 /* Software reset */ 1808dee1ad47SJeff Kirsher #define E1000_RCTL_EN 0x00000002 /* enable */ 1809dee1ad47SJeff Kirsher #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1810dee1ad47SJeff Kirsher #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1811dee1ad47SJeff Kirsher #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1812dee1ad47SJeff Kirsher #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1813dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1814dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1815dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1816dee1ad47SJeff Kirsher #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1817dee1ad47SJeff Kirsher #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 1818dee1ad47SJeff Kirsher #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 1819dee1ad47SJeff Kirsher #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1820dee1ad47SJeff Kirsher #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1821dee1ad47SJeff Kirsher #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1822dee1ad47SJeff Kirsher #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1823dee1ad47SJeff Kirsher #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1824dee1ad47SJeff Kirsher #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1825dee1ad47SJeff Kirsher #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1826dee1ad47SJeff Kirsher #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1827dee1ad47SJeff Kirsher #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1828dee1ad47SJeff Kirsher #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1829dee1ad47SJeff Kirsher /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1830dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1831dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1832dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1833dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1834dee1ad47SJeff Kirsher /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1835dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1836dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1837dee1ad47SJeff Kirsher #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1838dee1ad47SJeff Kirsher #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1839dee1ad47SJeff Kirsher #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1840dee1ad47SJeff Kirsher #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1841dee1ad47SJeff Kirsher #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1842dee1ad47SJeff Kirsher #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1843dee1ad47SJeff Kirsher #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1844dee1ad47SJeff Kirsher #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1845dee1ad47SJeff Kirsher #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 1846dee1ad47SJeff Kirsher #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 1847dee1ad47SJeff Kirsher 1848dee1ad47SJeff Kirsher /* Use byte values for the following shift parameters 1849dee1ad47SJeff Kirsher * Usage: 1850dee1ad47SJeff Kirsher * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 1851dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE0_MASK) | 1852dee1ad47SJeff Kirsher * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 1853dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE1_MASK) | 1854dee1ad47SJeff Kirsher * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 1855dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE2_MASK) | 1856dee1ad47SJeff Kirsher * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 1857dee1ad47SJeff Kirsher * E1000_PSRCTL_BSIZE3_MASK)) 1858dee1ad47SJeff Kirsher * where value0 = [128..16256], default=256 1859dee1ad47SJeff Kirsher * value1 = [1024..64512], default=4096 1860dee1ad47SJeff Kirsher * value2 = [0..64512], default=4096 1861dee1ad47SJeff Kirsher * value3 = [0..64512], default=0 1862dee1ad47SJeff Kirsher */ 1863dee1ad47SJeff Kirsher 1864dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 1865dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 1866dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 1867dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 1868dee1ad47SJeff Kirsher 1869dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 1870dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 1871dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 1872dee1ad47SJeff Kirsher #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 1873dee1ad47SJeff Kirsher 1874dee1ad47SJeff Kirsher /* SW_W_SYNC definitions */ 1875dee1ad47SJeff Kirsher #define E1000_SWFW_EEP_SM 0x0001 1876dee1ad47SJeff Kirsher #define E1000_SWFW_PHY0_SM 0x0002 1877dee1ad47SJeff Kirsher #define E1000_SWFW_PHY1_SM 0x0004 1878dee1ad47SJeff Kirsher #define E1000_SWFW_MAC_CSR_SM 0x0008 1879dee1ad47SJeff Kirsher 1880dee1ad47SJeff Kirsher /* Receive Descriptor */ 1881dee1ad47SJeff Kirsher #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1882dee1ad47SJeff Kirsher #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 1883dee1ad47SJeff Kirsher #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 1884dee1ad47SJeff Kirsher #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 1885dee1ad47SJeff Kirsher #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 1886dee1ad47SJeff Kirsher 1887dee1ad47SJeff Kirsher /* Flow Control */ 1888dee1ad47SJeff Kirsher #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1889dee1ad47SJeff Kirsher #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1890dee1ad47SJeff Kirsher #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1891dee1ad47SJeff Kirsher #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1892dee1ad47SJeff Kirsher 1893dee1ad47SJeff Kirsher /* Header split receive */ 1894dee1ad47SJeff Kirsher #define E1000_RFCTL_ISCSI_DIS 0x00000001 1895dee1ad47SJeff Kirsher #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E 1896dee1ad47SJeff Kirsher #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 1897dee1ad47SJeff Kirsher #define E1000_RFCTL_NFSW_DIS 0x00000040 1898dee1ad47SJeff Kirsher #define E1000_RFCTL_NFSR_DIS 0x00000080 1899dee1ad47SJeff Kirsher #define E1000_RFCTL_NFS_VER_MASK 0x00000300 1900dee1ad47SJeff Kirsher #define E1000_RFCTL_NFS_VER_SHIFT 8 1901dee1ad47SJeff Kirsher #define E1000_RFCTL_IPV6_DIS 0x00000400 1902dee1ad47SJeff Kirsher #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 1903dee1ad47SJeff Kirsher #define E1000_RFCTL_ACK_DIS 0x00001000 1904dee1ad47SJeff Kirsher #define E1000_RFCTL_ACKD_DIS 0x00002000 1905dee1ad47SJeff Kirsher #define E1000_RFCTL_IPFRSP_DIS 0x00004000 1906dee1ad47SJeff Kirsher #define E1000_RFCTL_EXTEN 0x00008000 1907dee1ad47SJeff Kirsher #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 1908dee1ad47SJeff Kirsher #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1909dee1ad47SJeff Kirsher 1910dee1ad47SJeff Kirsher /* Receive Descriptor Control */ 1911dee1ad47SJeff Kirsher #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1912dee1ad47SJeff Kirsher #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1913dee1ad47SJeff Kirsher #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 1914dee1ad47SJeff Kirsher #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1915dee1ad47SJeff Kirsher 1916dee1ad47SJeff Kirsher /* Transmit Descriptor Control */ 1917dee1ad47SJeff Kirsher #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 1918dee1ad47SJeff Kirsher #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 1919dee1ad47SJeff Kirsher #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 1920dee1ad47SJeff Kirsher #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1921dee1ad47SJeff Kirsher #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1922dee1ad47SJeff Kirsher #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1923dee1ad47SJeff Kirsher #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. 1924dee1ad47SJeff Kirsher still to be processed. */ 1925dee1ad47SJeff Kirsher /* Transmit Configuration Word */ 1926dee1ad47SJeff Kirsher #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1927dee1ad47SJeff Kirsher #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1928dee1ad47SJeff Kirsher #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1929dee1ad47SJeff Kirsher #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1930dee1ad47SJeff Kirsher #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1931dee1ad47SJeff Kirsher #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1932dee1ad47SJeff Kirsher #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1933dee1ad47SJeff Kirsher #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1934dee1ad47SJeff Kirsher #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1935dee1ad47SJeff Kirsher #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1936dee1ad47SJeff Kirsher 1937dee1ad47SJeff Kirsher /* Receive Configuration Word */ 1938dee1ad47SJeff Kirsher #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1939dee1ad47SJeff Kirsher #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1940dee1ad47SJeff Kirsher #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1941dee1ad47SJeff Kirsher #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1942dee1ad47SJeff Kirsher #define E1000_RXCW_C 0x20000000 /* Receive config */ 1943dee1ad47SJeff Kirsher #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1944dee1ad47SJeff Kirsher #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1945dee1ad47SJeff Kirsher 1946dee1ad47SJeff Kirsher /* Transmit Control */ 1947dee1ad47SJeff Kirsher #define E1000_TCTL_RST 0x00000001 /* software reset */ 1948dee1ad47SJeff Kirsher #define E1000_TCTL_EN 0x00000002 /* enable tx */ 1949dee1ad47SJeff Kirsher #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 1950dee1ad47SJeff Kirsher #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 1951dee1ad47SJeff Kirsher #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 1952dee1ad47SJeff Kirsher #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 1953dee1ad47SJeff Kirsher #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 1954dee1ad47SJeff Kirsher #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1955dee1ad47SJeff Kirsher #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1956dee1ad47SJeff Kirsher #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1957dee1ad47SJeff Kirsher #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 1958dee1ad47SJeff Kirsher /* Extended Transmit Control */ 1959dee1ad47SJeff Kirsher #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 1960dee1ad47SJeff Kirsher #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 1961dee1ad47SJeff Kirsher 1962dee1ad47SJeff Kirsher /* Receive Checksum Control */ 1963dee1ad47SJeff Kirsher #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1964dee1ad47SJeff Kirsher #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1965dee1ad47SJeff Kirsher #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1966dee1ad47SJeff Kirsher #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1967dee1ad47SJeff Kirsher #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1968dee1ad47SJeff Kirsher #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1969dee1ad47SJeff Kirsher 1970dee1ad47SJeff Kirsher /* Multiple Receive Queue Control */ 1971dee1ad47SJeff Kirsher #define E1000_MRQC_ENABLE_MASK 0x00000003 1972dee1ad47SJeff Kirsher #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 1973dee1ad47SJeff Kirsher #define E1000_MRQC_ENABLE_RSS_INT 0x00000004 1974dee1ad47SJeff Kirsher #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 1975dee1ad47SJeff Kirsher #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 1976dee1ad47SJeff Kirsher #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 1977dee1ad47SJeff Kirsher #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 1978dee1ad47SJeff Kirsher #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 1979dee1ad47SJeff Kirsher #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 1980dee1ad47SJeff Kirsher #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 1981dee1ad47SJeff Kirsher 1982dee1ad47SJeff Kirsher /* Definitions for power management and wakeup registers */ 1983dee1ad47SJeff Kirsher /* Wake Up Control */ 1984dee1ad47SJeff Kirsher #define E1000_WUC_APME 0x00000001 /* APM Enable */ 1985dee1ad47SJeff Kirsher #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 1986dee1ad47SJeff Kirsher #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 1987dee1ad47SJeff Kirsher #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 1988dee1ad47SJeff Kirsher #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 1989dee1ad47SJeff Kirsher 1990dee1ad47SJeff Kirsher /* Wake Up Filter Control */ 1991dee1ad47SJeff Kirsher #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 1992dee1ad47SJeff Kirsher #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 1993dee1ad47SJeff Kirsher #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 1994dee1ad47SJeff Kirsher #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 1995dee1ad47SJeff Kirsher #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 1996dee1ad47SJeff Kirsher #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1997dee1ad47SJeff Kirsher #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1998dee1ad47SJeff Kirsher #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1999dee1ad47SJeff Kirsher #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 2000dee1ad47SJeff Kirsher #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 2001dee1ad47SJeff Kirsher #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 2002dee1ad47SJeff Kirsher #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 2003dee1ad47SJeff Kirsher #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 2004dee1ad47SJeff Kirsher #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 2005dee1ad47SJeff Kirsher #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 2006dee1ad47SJeff Kirsher #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 2007dee1ad47SJeff Kirsher 2008dee1ad47SJeff Kirsher /* Wake Up Status */ 2009dee1ad47SJeff Kirsher #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 2010dee1ad47SJeff Kirsher #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 2011dee1ad47SJeff Kirsher #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 2012dee1ad47SJeff Kirsher #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 2013dee1ad47SJeff Kirsher #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 2014dee1ad47SJeff Kirsher #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 2015dee1ad47SJeff Kirsher #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 2016dee1ad47SJeff Kirsher #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 2017dee1ad47SJeff Kirsher #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 2018dee1ad47SJeff Kirsher #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 2019dee1ad47SJeff Kirsher #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 2020dee1ad47SJeff Kirsher #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 2021dee1ad47SJeff Kirsher #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 2022dee1ad47SJeff Kirsher 2023dee1ad47SJeff Kirsher /* Management Control */ 2024dee1ad47SJeff Kirsher #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 2025dee1ad47SJeff Kirsher #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 2026dee1ad47SJeff Kirsher #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 2027dee1ad47SJeff Kirsher #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 2028dee1ad47SJeff Kirsher #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 2029dee1ad47SJeff Kirsher #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 2030dee1ad47SJeff Kirsher #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 2031dee1ad47SJeff Kirsher #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 2032dee1ad47SJeff Kirsher #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 2033dee1ad47SJeff Kirsher #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 2034dee1ad47SJeff Kirsher * Filtering */ 2035dee1ad47SJeff Kirsher #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 2036dee1ad47SJeff Kirsher #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 2037dee1ad47SJeff Kirsher #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 2038dee1ad47SJeff Kirsher #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 2039dee1ad47SJeff Kirsher #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 2040dee1ad47SJeff Kirsher #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 2041dee1ad47SJeff Kirsher #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 2042dee1ad47SJeff Kirsher * filtering */ 2043dee1ad47SJeff Kirsher #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 2044dee1ad47SJeff Kirsher * memory */ 2045dee1ad47SJeff Kirsher #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2046dee1ad47SJeff Kirsher * filtering */ 2047dee1ad47SJeff Kirsher #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2048dee1ad47SJeff Kirsher #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2049dee1ad47SJeff Kirsher #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2050dee1ad47SJeff Kirsher #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2051dee1ad47SJeff Kirsher #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2052dee1ad47SJeff Kirsher #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 2053dee1ad47SJeff Kirsher #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 2054dee1ad47SJeff Kirsher #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 2055dee1ad47SJeff Kirsher 2056dee1ad47SJeff Kirsher #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 2057dee1ad47SJeff Kirsher #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 2058dee1ad47SJeff Kirsher 2059dee1ad47SJeff Kirsher /* SW Semaphore Register */ 2060dee1ad47SJeff Kirsher #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2061dee1ad47SJeff Kirsher #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2062dee1ad47SJeff Kirsher #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2063dee1ad47SJeff Kirsher #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 2064dee1ad47SJeff Kirsher 2065dee1ad47SJeff Kirsher /* FW Semaphore Register */ 2066dee1ad47SJeff Kirsher #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ 2067dee1ad47SJeff Kirsher #define E1000_FWSM_MODE_SHIFT 1 2068dee1ad47SJeff Kirsher #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2069dee1ad47SJeff Kirsher 2070dee1ad47SJeff Kirsher #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 2071dee1ad47SJeff Kirsher #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ 2072dee1ad47SJeff Kirsher #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ 2073dee1ad47SJeff Kirsher #define E1000_FWSM_SKUEL_SHIFT 29 2074dee1ad47SJeff Kirsher #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ 2075dee1ad47SJeff Kirsher #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ 2076dee1ad47SJeff Kirsher #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ 2077dee1ad47SJeff Kirsher #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ 2078dee1ad47SJeff Kirsher 2079dee1ad47SJeff Kirsher /* FFLT Debug Register */ 2080dee1ad47SJeff Kirsher #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2081dee1ad47SJeff Kirsher 2082dee1ad47SJeff Kirsher typedef enum { 2083dee1ad47SJeff Kirsher e1000_mng_mode_none = 0, 2084dee1ad47SJeff Kirsher e1000_mng_mode_asf, 2085dee1ad47SJeff Kirsher e1000_mng_mode_pt, 2086dee1ad47SJeff Kirsher e1000_mng_mode_ipmi, 2087dee1ad47SJeff Kirsher e1000_mng_mode_host_interface_only 2088dee1ad47SJeff Kirsher } e1000_mng_mode; 2089dee1ad47SJeff Kirsher 2090dee1ad47SJeff Kirsher /* Host Interface Control Register */ 2091dee1ad47SJeff Kirsher #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ 2092dee1ad47SJeff Kirsher #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done 2093dee1ad47SJeff Kirsher * to put command in RAM */ 2094dee1ad47SJeff Kirsher #define E1000_HICR_SV 0x00000004 /* Status Validity */ 2095dee1ad47SJeff Kirsher #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ 2096dee1ad47SJeff Kirsher 2097dee1ad47SJeff Kirsher /* Host Interface Command Interface - Address range 0x8800-0x8EFF */ 2098dee1ad47SJeff Kirsher #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ 2099dee1ad47SJeff Kirsher #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ 2100dee1ad47SJeff Kirsher #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ 2101dee1ad47SJeff Kirsher #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ 2102dee1ad47SJeff Kirsher 2103dee1ad47SJeff Kirsher struct e1000_host_command_header { 2104dee1ad47SJeff Kirsher u8 command_id; 2105dee1ad47SJeff Kirsher u8 command_length; 2106dee1ad47SJeff Kirsher u8 command_options; /* I/F bits for command, status for return */ 2107dee1ad47SJeff Kirsher u8 checksum; 2108dee1ad47SJeff Kirsher }; 2109dee1ad47SJeff Kirsher struct e1000_host_command_info { 2110dee1ad47SJeff Kirsher struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 2111dee1ad47SJeff Kirsher u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ 2112dee1ad47SJeff Kirsher }; 2113dee1ad47SJeff Kirsher 2114dee1ad47SJeff Kirsher /* Host SMB register #0 */ 2115dee1ad47SJeff Kirsher #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ 2116dee1ad47SJeff Kirsher #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ 2117dee1ad47SJeff Kirsher #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ 2118dee1ad47SJeff Kirsher #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ 2119dee1ad47SJeff Kirsher 2120dee1ad47SJeff Kirsher /* Host SMB register #1 */ 2121dee1ad47SJeff Kirsher #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN 2122dee1ad47SJeff Kirsher #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN 2123dee1ad47SJeff Kirsher #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT 2124dee1ad47SJeff Kirsher #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT 2125dee1ad47SJeff Kirsher 2126dee1ad47SJeff Kirsher /* FW Status Register */ 2127dee1ad47SJeff Kirsher #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ 2128dee1ad47SJeff Kirsher 2129dee1ad47SJeff Kirsher /* Wake Up Packet Length */ 2130dee1ad47SJeff Kirsher #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 2131dee1ad47SJeff Kirsher 2132dee1ad47SJeff Kirsher #define E1000_MDALIGN 4096 2133dee1ad47SJeff Kirsher 2134dee1ad47SJeff Kirsher /* PCI-Ex registers*/ 2135dee1ad47SJeff Kirsher 2136dee1ad47SJeff Kirsher /* PCI-Ex Control Register */ 2137dee1ad47SJeff Kirsher #define E1000_GCR_RXD_NO_SNOOP 0x00000001 2138dee1ad47SJeff Kirsher #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 2139dee1ad47SJeff Kirsher #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 2140dee1ad47SJeff Kirsher #define E1000_GCR_TXD_NO_SNOOP 0x00000008 2141dee1ad47SJeff Kirsher #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 2142dee1ad47SJeff Kirsher #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 2143dee1ad47SJeff Kirsher 2144dee1ad47SJeff Kirsher #define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 2145dee1ad47SJeff Kirsher E1000_GCR_RXDSCW_NO_SNOOP | \ 2146dee1ad47SJeff Kirsher E1000_GCR_RXDSCR_NO_SNOOP | \ 2147dee1ad47SJeff Kirsher E1000_GCR_TXD_NO_SNOOP | \ 2148dee1ad47SJeff Kirsher E1000_GCR_TXDSCW_NO_SNOOP | \ 2149dee1ad47SJeff Kirsher E1000_GCR_TXDSCR_NO_SNOOP) 2150dee1ad47SJeff Kirsher 2151dee1ad47SJeff Kirsher #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL 2152dee1ad47SJeff Kirsher 2153dee1ad47SJeff Kirsher #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 2154dee1ad47SJeff Kirsher /* Function Active and Power State to MNG */ 2155dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 2156dee1ad47SJeff Kirsher #define E1000_FACTPS_LAN0_VALID 0x00000004 2157dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008 2158dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0 2159dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6 2160dee1ad47SJeff Kirsher #define E1000_FACTPS_LAN1_VALID 0x00000100 2161dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200 2162dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000 2163dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12 2164dee1ad47SJeff Kirsher #define E1000_FACTPS_IDE_ENABLE 0x00004000 2165dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000 2166dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000 2167dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18 2168dee1ad47SJeff Kirsher #define E1000_FACTPS_SP_ENABLE 0x00100000 2169dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000 2170dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000 2171dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24 2172dee1ad47SJeff Kirsher #define E1000_FACTPS_IPMI_ENABLE 0x04000000 2173dee1ad47SJeff Kirsher #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000 2174dee1ad47SJeff Kirsher #define E1000_FACTPS_MNGCG 0x20000000 2175dee1ad47SJeff Kirsher #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000 2176dee1ad47SJeff Kirsher #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000 2177dee1ad47SJeff Kirsher 2178dee1ad47SJeff Kirsher /* PCI-Ex Config Space */ 2179dee1ad47SJeff Kirsher #define PCI_EX_LINK_STATUS 0x12 2180dee1ad47SJeff Kirsher #define PCI_EX_LINK_WIDTH_MASK 0x3F0 2181dee1ad47SJeff Kirsher #define PCI_EX_LINK_WIDTH_SHIFT 4 2182dee1ad47SJeff Kirsher 2183dee1ad47SJeff Kirsher /* EEPROM Commands - Microwire */ 2184dee1ad47SJeff Kirsher #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 2185dee1ad47SJeff Kirsher #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 2186dee1ad47SJeff Kirsher #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 2187dee1ad47SJeff Kirsher #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 2188dee1ad47SJeff Kirsher #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */ 2189dee1ad47SJeff Kirsher 2190dee1ad47SJeff Kirsher /* EEPROM Commands - SPI */ 2191dee1ad47SJeff Kirsher #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2192dee1ad47SJeff Kirsher #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2193dee1ad47SJeff Kirsher #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2194dee1ad47SJeff Kirsher #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2195dee1ad47SJeff Kirsher #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ 2196dee1ad47SJeff Kirsher #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ 2197dee1ad47SJeff Kirsher #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ 2198dee1ad47SJeff Kirsher #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ 2199dee1ad47SJeff Kirsher #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2200dee1ad47SJeff Kirsher #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2201dee1ad47SJeff Kirsher #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2202dee1ad47SJeff Kirsher 2203dee1ad47SJeff Kirsher /* EEPROM Size definitions */ 2204dee1ad47SJeff Kirsher #define EEPROM_WORD_SIZE_SHIFT 6 2205dee1ad47SJeff Kirsher #define EEPROM_SIZE_SHIFT 10 2206dee1ad47SJeff Kirsher #define EEPROM_SIZE_MASK 0x1C00 2207dee1ad47SJeff Kirsher 2208dee1ad47SJeff Kirsher /* EEPROM Word Offsets */ 2209dee1ad47SJeff Kirsher #define EEPROM_COMPAT 0x0003 2210dee1ad47SJeff Kirsher #define EEPROM_ID_LED_SETTINGS 0x0004 2211dee1ad47SJeff Kirsher #define EEPROM_VERSION 0x0005 2212dee1ad47SJeff Kirsher #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 2213dee1ad47SJeff Kirsher #define EEPROM_PHY_CLASS_WORD 0x0007 2214dee1ad47SJeff Kirsher #define EEPROM_INIT_CONTROL1_REG 0x000A 2215dee1ad47SJeff Kirsher #define EEPROM_INIT_CONTROL2_REG 0x000F 2216dee1ad47SJeff Kirsher #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 2217dee1ad47SJeff Kirsher #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 2218dee1ad47SJeff Kirsher #define EEPROM_INIT_3GIO_3 0x001A 2219dee1ad47SJeff Kirsher #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 2220dee1ad47SJeff Kirsher #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 2221dee1ad47SJeff Kirsher #define EEPROM_CFG 0x0012 2222dee1ad47SJeff Kirsher #define EEPROM_FLASH_VERSION 0x0032 2223dee1ad47SJeff Kirsher #define EEPROM_CHECKSUM_REG 0x003F 2224dee1ad47SJeff Kirsher 2225dee1ad47SJeff Kirsher #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ 2226dee1ad47SJeff Kirsher #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ 2227dee1ad47SJeff Kirsher 2228dee1ad47SJeff Kirsher /* Word definitions for ID LED Settings */ 2229dee1ad47SJeff Kirsher #define ID_LED_RESERVED_0000 0x0000 2230dee1ad47SJeff Kirsher #define ID_LED_RESERVED_FFFF 0xFFFF 2231dee1ad47SJeff Kirsher #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 2232dee1ad47SJeff Kirsher (ID_LED_OFF1_OFF2 << 8) | \ 2233dee1ad47SJeff Kirsher (ID_LED_DEF1_DEF2 << 4) | \ 2234dee1ad47SJeff Kirsher (ID_LED_DEF1_DEF2)) 2235dee1ad47SJeff Kirsher #define ID_LED_DEF1_DEF2 0x1 2236dee1ad47SJeff Kirsher #define ID_LED_DEF1_ON2 0x2 2237dee1ad47SJeff Kirsher #define ID_LED_DEF1_OFF2 0x3 2238dee1ad47SJeff Kirsher #define ID_LED_ON1_DEF2 0x4 2239dee1ad47SJeff Kirsher #define ID_LED_ON1_ON2 0x5 2240dee1ad47SJeff Kirsher #define ID_LED_ON1_OFF2 0x6 2241dee1ad47SJeff Kirsher #define ID_LED_OFF1_DEF2 0x7 2242dee1ad47SJeff Kirsher #define ID_LED_OFF1_ON2 0x8 2243dee1ad47SJeff Kirsher #define ID_LED_OFF1_OFF2 0x9 2244dee1ad47SJeff Kirsher 2245dee1ad47SJeff Kirsher #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 2246dee1ad47SJeff Kirsher #define IGP_ACTIVITY_LED_ENABLE 0x0300 2247dee1ad47SJeff Kirsher #define IGP_LED3_MODE 0x07000000 2248dee1ad47SJeff Kirsher 2249dee1ad47SJeff Kirsher /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ 2250dee1ad47SJeff Kirsher #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F 2251dee1ad47SJeff Kirsher 2252dee1ad47SJeff Kirsher /* Mask bit for PHY class in Word 7 of the EEPROM */ 2253dee1ad47SJeff Kirsher #define EEPROM_PHY_CLASS_A 0x8000 2254dee1ad47SJeff Kirsher 2255dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x0a of the EEPROM */ 2256dee1ad47SJeff Kirsher #define EEPROM_WORD0A_ILOS 0x0010 2257dee1ad47SJeff Kirsher #define EEPROM_WORD0A_SWDPIO 0x01E0 2258dee1ad47SJeff Kirsher #define EEPROM_WORD0A_LRST 0x0200 2259dee1ad47SJeff Kirsher #define EEPROM_WORD0A_FD 0x0400 2260dee1ad47SJeff Kirsher #define EEPROM_WORD0A_66MHZ 0x0800 2261dee1ad47SJeff Kirsher 2262dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x0f of the EEPROM */ 2263dee1ad47SJeff Kirsher #define EEPROM_WORD0F_PAUSE_MASK 0x3000 2264dee1ad47SJeff Kirsher #define EEPROM_WORD0F_PAUSE 0x1000 2265dee1ad47SJeff Kirsher #define EEPROM_WORD0F_ASM_DIR 0x2000 2266dee1ad47SJeff Kirsher #define EEPROM_WORD0F_ANE 0x0800 2267dee1ad47SJeff Kirsher #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 2268dee1ad47SJeff Kirsher #define EEPROM_WORD0F_LPLU 0x0001 2269dee1ad47SJeff Kirsher 2270dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x10/0x20 of the EEPROM */ 2271dee1ad47SJeff Kirsher #define EEPROM_WORD1020_GIGA_DISABLE 0x0010 2272dee1ad47SJeff Kirsher #define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008 2273dee1ad47SJeff Kirsher 2274dee1ad47SJeff Kirsher /* Mask bits for fields in Word 0x1a of the EEPROM */ 2275dee1ad47SJeff Kirsher #define EEPROM_WORD1A_ASPM_MASK 0x000C 2276dee1ad47SJeff Kirsher 2277dee1ad47SJeff Kirsher /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 2278dee1ad47SJeff Kirsher #define EEPROM_SUM 0xBABA 2279dee1ad47SJeff Kirsher 2280dee1ad47SJeff Kirsher /* EEPROM Map defines (WORD OFFSETS)*/ 2281dee1ad47SJeff Kirsher #define EEPROM_NODE_ADDRESS_BYTE_0 0 2282dee1ad47SJeff Kirsher #define EEPROM_PBA_BYTE_1 8 2283dee1ad47SJeff Kirsher 2284dee1ad47SJeff Kirsher #define EEPROM_RESERVED_WORD 0xFFFF 2285dee1ad47SJeff Kirsher 2286dee1ad47SJeff Kirsher /* EEPROM Map Sizes (Byte Counts) */ 2287dee1ad47SJeff Kirsher #define PBA_SIZE 4 2288dee1ad47SJeff Kirsher 2289dee1ad47SJeff Kirsher /* Collision related configuration parameters */ 2290dee1ad47SJeff Kirsher #define E1000_COLLISION_THRESHOLD 15 2291dee1ad47SJeff Kirsher #define E1000_CT_SHIFT 4 2292dee1ad47SJeff Kirsher /* Collision distance is a 0-based value that applies to 2293dee1ad47SJeff Kirsher * half-duplex-capable hardware only. */ 2294dee1ad47SJeff Kirsher #define E1000_COLLISION_DISTANCE 63 2295dee1ad47SJeff Kirsher #define E1000_COLLISION_DISTANCE_82542 64 2296dee1ad47SJeff Kirsher #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 2297dee1ad47SJeff Kirsher #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 2298dee1ad47SJeff Kirsher #define E1000_COLD_SHIFT 12 2299dee1ad47SJeff Kirsher 2300dee1ad47SJeff Kirsher /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2301dee1ad47SJeff Kirsher #define REQ_TX_DESCRIPTOR_MULTIPLE 8 2302dee1ad47SJeff Kirsher #define REQ_RX_DESCRIPTOR_MULTIPLE 8 2303dee1ad47SJeff Kirsher 2304dee1ad47SJeff Kirsher /* Default values for the transmit IPG register */ 2305dee1ad47SJeff Kirsher #define DEFAULT_82542_TIPG_IPGT 10 2306dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGT_FIBER 9 2307dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGT_COPPER 8 2308dee1ad47SJeff Kirsher 2309dee1ad47SJeff Kirsher #define E1000_TIPG_IPGT_MASK 0x000003FF 2310dee1ad47SJeff Kirsher #define E1000_TIPG_IPGR1_MASK 0x000FFC00 2311dee1ad47SJeff Kirsher #define E1000_TIPG_IPGR2_MASK 0x3FF00000 2312dee1ad47SJeff Kirsher 2313dee1ad47SJeff Kirsher #define DEFAULT_82542_TIPG_IPGR1 2 2314dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGR1 8 2315dee1ad47SJeff Kirsher #define E1000_TIPG_IPGR1_SHIFT 10 2316dee1ad47SJeff Kirsher 2317dee1ad47SJeff Kirsher #define DEFAULT_82542_TIPG_IPGR2 10 2318dee1ad47SJeff Kirsher #define DEFAULT_82543_TIPG_IPGR2 6 2319dee1ad47SJeff Kirsher #define E1000_TIPG_IPGR2_SHIFT 20 2320dee1ad47SJeff Kirsher 2321dee1ad47SJeff Kirsher #define E1000_TXDMAC_DPP 0x00000001 2322dee1ad47SJeff Kirsher 2323dee1ad47SJeff Kirsher /* Adaptive IFS defines */ 2324dee1ad47SJeff Kirsher #define TX_THRESHOLD_START 8 2325dee1ad47SJeff Kirsher #define TX_THRESHOLD_INCREMENT 10 2326dee1ad47SJeff Kirsher #define TX_THRESHOLD_DECREMENT 1 2327dee1ad47SJeff Kirsher #define TX_THRESHOLD_STOP 190 2328dee1ad47SJeff Kirsher #define TX_THRESHOLD_DISABLE 0 2329dee1ad47SJeff Kirsher #define TX_THRESHOLD_TIMER_MS 10000 2330dee1ad47SJeff Kirsher #define MIN_NUM_XMITS 1000 2331dee1ad47SJeff Kirsher #define IFS_MAX 80 2332dee1ad47SJeff Kirsher #define IFS_STEP 10 2333dee1ad47SJeff Kirsher #define IFS_MIN 40 2334dee1ad47SJeff Kirsher #define IFS_RATIO 4 2335dee1ad47SJeff Kirsher 2336dee1ad47SJeff Kirsher /* Extended Configuration Control and Size */ 2337dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001 2338dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002 2339dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004 2340dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008 2341dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 2342dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 2343dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 2344dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000 2345dee1ad47SJeff Kirsher 2346dee1ad47SJeff Kirsher #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF 2347dee1ad47SJeff Kirsher #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 2348dee1ad47SJeff Kirsher #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 2349dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 2350dee1ad47SJeff Kirsher #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 2351dee1ad47SJeff Kirsher 2352dee1ad47SJeff Kirsher /* PBA constants */ 2353dee1ad47SJeff Kirsher #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ 2354dee1ad47SJeff Kirsher #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2355dee1ad47SJeff Kirsher #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2356dee1ad47SJeff Kirsher #define E1000_PBA_20K 0x0014 2357dee1ad47SJeff Kirsher #define E1000_PBA_22K 0x0016 2358dee1ad47SJeff Kirsher #define E1000_PBA_24K 0x0018 2359dee1ad47SJeff Kirsher #define E1000_PBA_30K 0x001E 2360dee1ad47SJeff Kirsher #define E1000_PBA_32K 0x0020 2361dee1ad47SJeff Kirsher #define E1000_PBA_34K 0x0022 2362dee1ad47SJeff Kirsher #define E1000_PBA_38K 0x0026 2363dee1ad47SJeff Kirsher #define E1000_PBA_40K 0x0028 2364dee1ad47SJeff Kirsher #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2365dee1ad47SJeff Kirsher 2366dee1ad47SJeff Kirsher #define E1000_PBS_16K E1000_PBA_16K 2367dee1ad47SJeff Kirsher 2368dee1ad47SJeff Kirsher /* Flow Control Constants */ 2369dee1ad47SJeff Kirsher #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 2370dee1ad47SJeff Kirsher #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 2371dee1ad47SJeff Kirsher #define FLOW_CONTROL_TYPE 0x8808 2372dee1ad47SJeff Kirsher 2373dee1ad47SJeff Kirsher /* The historical defaults for the flow control values are given below. */ 2374dee1ad47SJeff Kirsher #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 2375dee1ad47SJeff Kirsher #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 2376dee1ad47SJeff Kirsher #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 2377dee1ad47SJeff Kirsher 2378dee1ad47SJeff Kirsher /* PCIX Config space */ 2379dee1ad47SJeff Kirsher #define PCIX_COMMAND_REGISTER 0xE6 2380dee1ad47SJeff Kirsher #define PCIX_STATUS_REGISTER_LO 0xE8 2381dee1ad47SJeff Kirsher #define PCIX_STATUS_REGISTER_HI 0xEA 2382dee1ad47SJeff Kirsher 2383dee1ad47SJeff Kirsher #define PCIX_COMMAND_MMRBC_MASK 0x000C 2384dee1ad47SJeff Kirsher #define PCIX_COMMAND_MMRBC_SHIFT 0x2 2385dee1ad47SJeff Kirsher #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 2386dee1ad47SJeff Kirsher #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 2387dee1ad47SJeff Kirsher #define PCIX_STATUS_HI_MMRBC_4K 0x3 2388dee1ad47SJeff Kirsher #define PCIX_STATUS_HI_MMRBC_2K 0x2 2389dee1ad47SJeff Kirsher 2390dee1ad47SJeff Kirsher /* Number of bits required to shift right the "pause" bits from the 2391dee1ad47SJeff Kirsher * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. 2392dee1ad47SJeff Kirsher */ 2393dee1ad47SJeff Kirsher #define PAUSE_SHIFT 5 2394dee1ad47SJeff Kirsher 2395dee1ad47SJeff Kirsher /* Number of bits required to shift left the "SWDPIO" bits from the 2396dee1ad47SJeff Kirsher * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register. 2397dee1ad47SJeff Kirsher */ 2398dee1ad47SJeff Kirsher #define SWDPIO_SHIFT 17 2399dee1ad47SJeff Kirsher 2400dee1ad47SJeff Kirsher /* Number of bits required to shift left the "SWDPIO_EXT" bits from the 2401dee1ad47SJeff Kirsher * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register. 2402dee1ad47SJeff Kirsher */ 2403dee1ad47SJeff Kirsher #define SWDPIO__EXT_SHIFT 4 2404dee1ad47SJeff Kirsher 2405dee1ad47SJeff Kirsher /* Number of bits required to shift left the "ILOS" bit from the EEPROM 2406dee1ad47SJeff Kirsher * (bit 4) to the "ILOS" (bit 7) field in the CTRL register. 2407dee1ad47SJeff Kirsher */ 2408dee1ad47SJeff Kirsher #define ILOS_SHIFT 3 2409dee1ad47SJeff Kirsher 2410dee1ad47SJeff Kirsher #define RECEIVE_BUFFER_ALIGN_SIZE (256) 2411dee1ad47SJeff Kirsher 2412dee1ad47SJeff Kirsher /* Number of milliseconds we wait for auto-negotiation to complete */ 2413dee1ad47SJeff Kirsher #define LINK_UP_TIMEOUT 500 2414dee1ad47SJeff Kirsher 2415dee1ad47SJeff Kirsher /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ 2416dee1ad47SJeff Kirsher #define AUTO_READ_DONE_TIMEOUT 10 2417dee1ad47SJeff Kirsher /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2418dee1ad47SJeff Kirsher #define PHY_CFG_TIMEOUT 100 2419dee1ad47SJeff Kirsher 2420dee1ad47SJeff Kirsher #define E1000_TX_BUFFER_SIZE ((u32)1514) 2421dee1ad47SJeff Kirsher 2422dee1ad47SJeff Kirsher /* The carrier extension symbol, as received by the NIC. */ 2423dee1ad47SJeff Kirsher #define CARRIER_EXTENSION 0x0F 2424dee1ad47SJeff Kirsher 2425dee1ad47SJeff Kirsher /* TBI_ACCEPT macro definition: 2426dee1ad47SJeff Kirsher * 2427dee1ad47SJeff Kirsher * This macro requires: 2428dee1ad47SJeff Kirsher * adapter = a pointer to struct e1000_hw 2429dee1ad47SJeff Kirsher * status = the 8 bit status field of the RX descriptor with EOP set 2430dee1ad47SJeff Kirsher * error = the 8 bit error field of the RX descriptor with EOP set 2431dee1ad47SJeff Kirsher * length = the sum of all the length fields of the RX descriptors that 2432dee1ad47SJeff Kirsher * make up the current frame 2433dee1ad47SJeff Kirsher * last_byte = the last byte of the frame DMAed by the hardware 2434dee1ad47SJeff Kirsher * max_frame_length = the maximum frame length we want to accept. 2435dee1ad47SJeff Kirsher * min_frame_length = the minimum frame length we want to accept. 2436dee1ad47SJeff Kirsher * 2437dee1ad47SJeff Kirsher * This macro is a conditional that should be used in the interrupt 2438dee1ad47SJeff Kirsher * handler's Rx processing routine when RxErrors have been detected. 2439dee1ad47SJeff Kirsher * 2440dee1ad47SJeff Kirsher * Typical use: 2441dee1ad47SJeff Kirsher * ... 2442dee1ad47SJeff Kirsher * if (TBI_ACCEPT) { 2443dee1ad47SJeff Kirsher * accept_frame = true; 2444dee1ad47SJeff Kirsher * e1000_tbi_adjust_stats(adapter, MacAddress); 2445dee1ad47SJeff Kirsher * frame_length--; 2446dee1ad47SJeff Kirsher * } else { 2447dee1ad47SJeff Kirsher * accept_frame = false; 2448dee1ad47SJeff Kirsher * } 2449dee1ad47SJeff Kirsher * ... 2450dee1ad47SJeff Kirsher */ 2451dee1ad47SJeff Kirsher 2452dee1ad47SJeff Kirsher #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ 2453dee1ad47SJeff Kirsher ((adapter)->tbi_compatibility_on && \ 2454dee1ad47SJeff Kirsher (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ 2455dee1ad47SJeff Kirsher ((last_byte) == CARRIER_EXTENSION) && \ 2456dee1ad47SJeff Kirsher (((status) & E1000_RXD_STAT_VP) ? \ 2457dee1ad47SJeff Kirsher (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ 2458dee1ad47SJeff Kirsher ((length) <= ((adapter)->max_frame_size + 1))) : \ 2459dee1ad47SJeff Kirsher (((length) > (adapter)->min_frame_size) && \ 2460dee1ad47SJeff Kirsher ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) 2461dee1ad47SJeff Kirsher 2462dee1ad47SJeff Kirsher /* Structures, enums, and macros for the PHY */ 2463dee1ad47SJeff Kirsher 2464dee1ad47SJeff Kirsher /* Bit definitions for the Management Data IO (MDIO) and Management Data 2465dee1ad47SJeff Kirsher * Clock (MDC) pins in the Device Control Register. 2466dee1ad47SJeff Kirsher */ 2467dee1ad47SJeff Kirsher #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 2468dee1ad47SJeff Kirsher #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 2469dee1ad47SJeff Kirsher #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 2470dee1ad47SJeff Kirsher #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 2471dee1ad47SJeff Kirsher #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 2472dee1ad47SJeff Kirsher #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 2473dee1ad47SJeff Kirsher #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 2474dee1ad47SJeff Kirsher #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 2475dee1ad47SJeff Kirsher 2476dee1ad47SJeff Kirsher /* PHY 1000 MII Register/Bit Definitions */ 2477dee1ad47SJeff Kirsher /* PHY Registers defined by IEEE */ 2478dee1ad47SJeff Kirsher #define PHY_CTRL 0x00 /* Control Register */ 2479dee1ad47SJeff Kirsher #define PHY_STATUS 0x01 /* Status Register */ 2480dee1ad47SJeff Kirsher #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 2481dee1ad47SJeff Kirsher #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 2482dee1ad47SJeff Kirsher #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 2483dee1ad47SJeff Kirsher #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 2484dee1ad47SJeff Kirsher #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 2485dee1ad47SJeff Kirsher #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 2486dee1ad47SJeff Kirsher #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 2487dee1ad47SJeff Kirsher #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 2488dee1ad47SJeff Kirsher #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 2489dee1ad47SJeff Kirsher #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 2490dee1ad47SJeff Kirsher 2491dee1ad47SJeff Kirsher #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 2492dee1ad47SJeff Kirsher #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ 2493dee1ad47SJeff Kirsher 2494dee1ad47SJeff Kirsher /* M88E1000 Specific Registers */ 2495dee1ad47SJeff Kirsher #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 2496dee1ad47SJeff Kirsher #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 2497dee1ad47SJeff Kirsher #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 2498dee1ad47SJeff Kirsher #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 2499dee1ad47SJeff Kirsher #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 2500dee1ad47SJeff Kirsher #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 2501dee1ad47SJeff Kirsher 2502dee1ad47SJeff Kirsher #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 2503dee1ad47SJeff Kirsher #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 2504dee1ad47SJeff Kirsher #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 2505dee1ad47SJeff Kirsher #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 2506dee1ad47SJeff Kirsher #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 2507dee1ad47SJeff Kirsher 2508dee1ad47SJeff Kirsher #define IGP01E1000_IEEE_REGS_PAGE 0x0000 2509dee1ad47SJeff Kirsher #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 2510dee1ad47SJeff Kirsher #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 2511dee1ad47SJeff Kirsher 2512dee1ad47SJeff Kirsher /* IGP01E1000 Specific Registers */ 2513dee1ad47SJeff Kirsher #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 2514dee1ad47SJeff Kirsher #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 2515dee1ad47SJeff Kirsher #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 2516dee1ad47SJeff Kirsher #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 2517dee1ad47SJeff Kirsher #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 2518dee1ad47SJeff Kirsher #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 2519dee1ad47SJeff Kirsher #define IGP02E1000_PHY_POWER_MGMT 0x19 2520dee1ad47SJeff Kirsher #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 2521dee1ad47SJeff Kirsher 2522dee1ad47SJeff Kirsher /* IGP01E1000 AGC Registers - stores the cable length values*/ 2523dee1ad47SJeff Kirsher #define IGP01E1000_PHY_AGC_A 0x1172 2524dee1ad47SJeff Kirsher #define IGP01E1000_PHY_AGC_B 0x1272 2525dee1ad47SJeff Kirsher #define IGP01E1000_PHY_AGC_C 0x1472 2526dee1ad47SJeff Kirsher #define IGP01E1000_PHY_AGC_D 0x1872 2527dee1ad47SJeff Kirsher 2528dee1ad47SJeff Kirsher /* IGP02E1000 AGC Registers for cable length values */ 2529dee1ad47SJeff Kirsher #define IGP02E1000_PHY_AGC_A 0x11B1 2530dee1ad47SJeff Kirsher #define IGP02E1000_PHY_AGC_B 0x12B1 2531dee1ad47SJeff Kirsher #define IGP02E1000_PHY_AGC_C 0x14B1 2532dee1ad47SJeff Kirsher #define IGP02E1000_PHY_AGC_D 0x18B1 2533dee1ad47SJeff Kirsher 2534dee1ad47SJeff Kirsher /* IGP01E1000 DSP Reset Register */ 2535dee1ad47SJeff Kirsher #define IGP01E1000_PHY_DSP_RESET 0x1F33 2536dee1ad47SJeff Kirsher #define IGP01E1000_PHY_DSP_SET 0x1F71 2537dee1ad47SJeff Kirsher #define IGP01E1000_PHY_DSP_FFE 0x1F35 2538dee1ad47SJeff Kirsher 2539dee1ad47SJeff Kirsher #define IGP01E1000_PHY_CHANNEL_NUM 4 2540dee1ad47SJeff Kirsher #define IGP02E1000_PHY_CHANNEL_NUM 4 2541dee1ad47SJeff Kirsher 2542dee1ad47SJeff Kirsher #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 2543dee1ad47SJeff Kirsher #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 2544dee1ad47SJeff Kirsher #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 2545dee1ad47SJeff Kirsher #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 2546dee1ad47SJeff Kirsher 2547dee1ad47SJeff Kirsher #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 2548dee1ad47SJeff Kirsher #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 2549dee1ad47SJeff Kirsher 2550dee1ad47SJeff Kirsher #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 2551dee1ad47SJeff Kirsher #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 2552dee1ad47SJeff Kirsher #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 2553dee1ad47SJeff Kirsher #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 2554dee1ad47SJeff Kirsher 2555dee1ad47SJeff Kirsher #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A 2556dee1ad47SJeff Kirsher /* IGP01E1000 PCS Initialization register - stores the polarity status when 2557dee1ad47SJeff Kirsher * speed = 1000 Mbps. */ 2558dee1ad47SJeff Kirsher #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 2559dee1ad47SJeff Kirsher #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 2560dee1ad47SJeff Kirsher 2561dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 2562dee1ad47SJeff Kirsher 2563dee1ad47SJeff Kirsher /* PHY Control Register */ 2564dee1ad47SJeff Kirsher #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2565dee1ad47SJeff Kirsher #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 2566dee1ad47SJeff Kirsher #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 2567dee1ad47SJeff Kirsher #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 2568dee1ad47SJeff Kirsher #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 2569dee1ad47SJeff Kirsher #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 2570dee1ad47SJeff Kirsher #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 2571dee1ad47SJeff Kirsher #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2572dee1ad47SJeff Kirsher #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 2573dee1ad47SJeff Kirsher #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 2574dee1ad47SJeff Kirsher 2575dee1ad47SJeff Kirsher /* PHY Status Register */ 2576dee1ad47SJeff Kirsher #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 2577dee1ad47SJeff Kirsher #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 2578dee1ad47SJeff Kirsher #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 2579dee1ad47SJeff Kirsher #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 2580dee1ad47SJeff Kirsher #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 2581dee1ad47SJeff Kirsher #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 2582dee1ad47SJeff Kirsher #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 2583dee1ad47SJeff Kirsher #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 2584dee1ad47SJeff Kirsher #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 2585dee1ad47SJeff Kirsher #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 2586dee1ad47SJeff Kirsher #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 2587dee1ad47SJeff Kirsher #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 2588dee1ad47SJeff Kirsher #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 2589dee1ad47SJeff Kirsher #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 2590dee1ad47SJeff Kirsher #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 2591dee1ad47SJeff Kirsher 2592dee1ad47SJeff Kirsher /* Autoneg Advertisement Register */ 2593dee1ad47SJeff Kirsher #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 2594dee1ad47SJeff Kirsher #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 2595dee1ad47SJeff Kirsher #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 2596dee1ad47SJeff Kirsher #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 2597dee1ad47SJeff Kirsher #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 2598dee1ad47SJeff Kirsher #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 2599dee1ad47SJeff Kirsher #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 2600dee1ad47SJeff Kirsher #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 2601dee1ad47SJeff Kirsher #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 2602dee1ad47SJeff Kirsher #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2603dee1ad47SJeff Kirsher 2604dee1ad47SJeff Kirsher /* Link Partner Ability Register (Base Page) */ 2605dee1ad47SJeff Kirsher #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 2606dee1ad47SJeff Kirsher #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 2607dee1ad47SJeff Kirsher #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 2608dee1ad47SJeff Kirsher #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 2609dee1ad47SJeff Kirsher #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 2610dee1ad47SJeff Kirsher #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 2611dee1ad47SJeff Kirsher #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 2612dee1ad47SJeff Kirsher #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 2613dee1ad47SJeff Kirsher #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 2614dee1ad47SJeff Kirsher #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 2615dee1ad47SJeff Kirsher #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2616dee1ad47SJeff Kirsher 2617dee1ad47SJeff Kirsher /* Autoneg Expansion Register */ 2618dee1ad47SJeff Kirsher #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 2619dee1ad47SJeff Kirsher #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 2620dee1ad47SJeff Kirsher #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 2621dee1ad47SJeff Kirsher #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 2622dee1ad47SJeff Kirsher #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 2623dee1ad47SJeff Kirsher 2624dee1ad47SJeff Kirsher /* Next Page TX Register */ 2625dee1ad47SJeff Kirsher #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2626dee1ad47SJeff Kirsher #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 2627dee1ad47SJeff Kirsher * of different NP 2628dee1ad47SJeff Kirsher */ 2629dee1ad47SJeff Kirsher #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2630dee1ad47SJeff Kirsher * 0 = cannot comply with msg 2631dee1ad47SJeff Kirsher */ 2632dee1ad47SJeff Kirsher #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2633dee1ad47SJeff Kirsher #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2634dee1ad47SJeff Kirsher * 0 = sending last NP 2635dee1ad47SJeff Kirsher */ 2636dee1ad47SJeff Kirsher 2637dee1ad47SJeff Kirsher /* Link Partner Next Page Register */ 2638dee1ad47SJeff Kirsher #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2639dee1ad47SJeff Kirsher #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 2640dee1ad47SJeff Kirsher * of different NP 2641dee1ad47SJeff Kirsher */ 2642dee1ad47SJeff Kirsher #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2643dee1ad47SJeff Kirsher * 0 = cannot comply with msg 2644dee1ad47SJeff Kirsher */ 2645dee1ad47SJeff Kirsher #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2646dee1ad47SJeff Kirsher #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 2647dee1ad47SJeff Kirsher #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2648dee1ad47SJeff Kirsher * 0 = sending last NP 2649dee1ad47SJeff Kirsher */ 2650dee1ad47SJeff Kirsher 2651dee1ad47SJeff Kirsher /* 1000BASE-T Control Register */ 2652dee1ad47SJeff Kirsher #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 2653dee1ad47SJeff Kirsher #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 2654dee1ad47SJeff Kirsher #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 2655dee1ad47SJeff Kirsher #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 2656dee1ad47SJeff Kirsher /* 0=DTE device */ 2657dee1ad47SJeff Kirsher #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 2658dee1ad47SJeff Kirsher /* 0=Configure PHY as Slave */ 2659dee1ad47SJeff Kirsher #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 2660dee1ad47SJeff Kirsher /* 0=Automatic Master/Slave config */ 2661dee1ad47SJeff Kirsher #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 2662dee1ad47SJeff Kirsher #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 2663dee1ad47SJeff Kirsher #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 2664dee1ad47SJeff Kirsher #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 2665dee1ad47SJeff Kirsher #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 2666dee1ad47SJeff Kirsher 2667dee1ad47SJeff Kirsher /* 1000BASE-T Status Register */ 2668dee1ad47SJeff Kirsher #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 2669dee1ad47SJeff Kirsher #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 2670dee1ad47SJeff Kirsher #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 2671dee1ad47SJeff Kirsher #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 2672dee1ad47SJeff Kirsher #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 2673dee1ad47SJeff Kirsher #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 2674dee1ad47SJeff Kirsher #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 2675dee1ad47SJeff Kirsher #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 2676dee1ad47SJeff Kirsher #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 2677dee1ad47SJeff Kirsher #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 2678dee1ad47SJeff Kirsher #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 2679dee1ad47SJeff Kirsher #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 2680dee1ad47SJeff Kirsher #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 2681dee1ad47SJeff Kirsher 2682dee1ad47SJeff Kirsher /* Extended Status Register */ 2683dee1ad47SJeff Kirsher #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 2684dee1ad47SJeff Kirsher #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 2685dee1ad47SJeff Kirsher #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 2686dee1ad47SJeff Kirsher #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 2687dee1ad47SJeff Kirsher 2688dee1ad47SJeff Kirsher #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 2689dee1ad47SJeff Kirsher #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 2690dee1ad47SJeff Kirsher 2691dee1ad47SJeff Kirsher #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 2692dee1ad47SJeff Kirsher /* (0=enable, 1=disable) */ 2693dee1ad47SJeff Kirsher 2694dee1ad47SJeff Kirsher /* M88E1000 PHY Specific Control Register */ 2695dee1ad47SJeff Kirsher #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 2696dee1ad47SJeff Kirsher #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 2697dee1ad47SJeff Kirsher #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 2698dee1ad47SJeff Kirsher #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 2699dee1ad47SJeff Kirsher * 0=CLK125 toggling 2700dee1ad47SJeff Kirsher */ 2701dee1ad47SJeff Kirsher #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 2702dee1ad47SJeff Kirsher /* Manual MDI configuration */ 2703dee1ad47SJeff Kirsher #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 2704dee1ad47SJeff Kirsher #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 2705dee1ad47SJeff Kirsher * 100BASE-TX/10BASE-T: 2706dee1ad47SJeff Kirsher * MDI Mode 2707dee1ad47SJeff Kirsher */ 2708dee1ad47SJeff Kirsher #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 2709dee1ad47SJeff Kirsher * all speeds. 2710dee1ad47SJeff Kirsher */ 2711dee1ad47SJeff Kirsher #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 2712dee1ad47SJeff Kirsher /* 1=Enable Extended 10BASE-T distance 2713dee1ad47SJeff Kirsher * (Lower 10BASE-T RX Threshold) 2714dee1ad47SJeff Kirsher * 0=Normal 10BASE-T RX Threshold */ 2715dee1ad47SJeff Kirsher #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 2716dee1ad47SJeff Kirsher /* 1=5-Bit interface in 100BASE-TX 2717dee1ad47SJeff Kirsher * 0=MII interface in 100BASE-TX */ 2718dee1ad47SJeff Kirsher #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 2719dee1ad47SJeff Kirsher #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 2720dee1ad47SJeff Kirsher #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 2721dee1ad47SJeff Kirsher 2722dee1ad47SJeff Kirsher #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 2723dee1ad47SJeff Kirsher #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 2724dee1ad47SJeff Kirsher #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 2725dee1ad47SJeff Kirsher 2726dee1ad47SJeff Kirsher /* M88E1000 PHY Specific Status Register */ 2727dee1ad47SJeff Kirsher #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 2728dee1ad47SJeff Kirsher #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 2729dee1ad47SJeff Kirsher #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 2730dee1ad47SJeff Kirsher #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 2731dee1ad47SJeff Kirsher #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 2732dee1ad47SJeff Kirsher * 3=110-140M;4=>140M */ 2733dee1ad47SJeff Kirsher #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 2734dee1ad47SJeff Kirsher #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 2735dee1ad47SJeff Kirsher #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 2736dee1ad47SJeff Kirsher #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 2737dee1ad47SJeff Kirsher #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 2738dee1ad47SJeff Kirsher #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 2739dee1ad47SJeff Kirsher #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 2740dee1ad47SJeff Kirsher #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 2741dee1ad47SJeff Kirsher 2742dee1ad47SJeff Kirsher #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 2743dee1ad47SJeff Kirsher #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 2744dee1ad47SJeff Kirsher #define M88E1000_PSSR_MDIX_SHIFT 6 2745dee1ad47SJeff Kirsher #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 2746dee1ad47SJeff Kirsher 2747dee1ad47SJeff Kirsher /* M88E1000 Extended PHY Specific Control Register */ 2748dee1ad47SJeff Kirsher #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 2749dee1ad47SJeff Kirsher #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 2750dee1ad47SJeff Kirsher * Will assert lost lock and bring 2751dee1ad47SJeff Kirsher * link down if idle not seen 2752dee1ad47SJeff Kirsher * within 1ms in 1000BASE-T 2753dee1ad47SJeff Kirsher */ 2754dee1ad47SJeff Kirsher /* Number of times we will attempt to autonegotiate before downshifting if we 2755dee1ad47SJeff Kirsher * are the master */ 2756dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 2757dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 2758dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 2759dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 2760dee1ad47SJeff Kirsher #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 2761dee1ad47SJeff Kirsher /* Number of times we will attempt to autonegotiate before downshifting if we 2762dee1ad47SJeff Kirsher * are the slave */ 2763dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 2764dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 2765dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 2766dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 2767dee1ad47SJeff Kirsher #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 2768dee1ad47SJeff Kirsher #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 2769dee1ad47SJeff Kirsher #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2770dee1ad47SJeff Kirsher #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2771dee1ad47SJeff Kirsher 2772dee1ad47SJeff Kirsher /* M88EC018 Rev 2 specific DownShift settings */ 2773dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 2774dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 2775dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 2776dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 2777dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 2778dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 2779dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 2780dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 2781dee1ad47SJeff Kirsher #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 2782dee1ad47SJeff Kirsher 2783dee1ad47SJeff Kirsher /* IGP01E1000 Specific Port Config Register - R/W */ 2784dee1ad47SJeff Kirsher #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 2785dee1ad47SJeff Kirsher #define IGP01E1000_PSCFR_PRE_EN 0x0020 2786dee1ad47SJeff Kirsher #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 2787dee1ad47SJeff Kirsher #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 2788dee1ad47SJeff Kirsher #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 2789dee1ad47SJeff Kirsher #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 2790dee1ad47SJeff Kirsher 2791dee1ad47SJeff Kirsher /* IGP01E1000 Specific Port Status Register - R/O */ 2792dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 2793dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 2794dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C 2795dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 2796dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_LINK_UP 0x0400 2797dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_MDIX 0x0800 2798dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 2799dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 2800dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 2801dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 2802dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 2803dee1ad47SJeff Kirsher #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 2804dee1ad47SJeff Kirsher 2805dee1ad47SJeff Kirsher /* IGP01E1000 Specific Port Control Register - R/W */ 2806dee1ad47SJeff Kirsher #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 2807dee1ad47SJeff Kirsher #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 2808dee1ad47SJeff Kirsher #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 2809dee1ad47SJeff Kirsher #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 2810dee1ad47SJeff Kirsher #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 2811dee1ad47SJeff Kirsher #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 2812dee1ad47SJeff Kirsher 2813dee1ad47SJeff Kirsher /* IGP01E1000 Specific Port Link Health Register */ 2814dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 2815dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 2816dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_MASTER_FAULT 0x2000 2817dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 2818dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 2819dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 2820dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ 2821dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_DATA_ERR_0 0x0100 2822dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 2823dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 2824dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008 2825dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004 2826dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002 2827dee1ad47SJeff Kirsher #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001 2828dee1ad47SJeff Kirsher 2829dee1ad47SJeff Kirsher /* IGP01E1000 Channel Quality Register */ 2830dee1ad47SJeff Kirsher #define IGP01E1000_MSE_CHANNEL_D 0x000F 2831dee1ad47SJeff Kirsher #define IGP01E1000_MSE_CHANNEL_C 0x00F0 2832dee1ad47SJeff Kirsher #define IGP01E1000_MSE_CHANNEL_B 0x0F00 2833dee1ad47SJeff Kirsher #define IGP01E1000_MSE_CHANNEL_A 0xF000 2834dee1ad47SJeff Kirsher 2835dee1ad47SJeff Kirsher #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 2836dee1ad47SJeff Kirsher #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ 2837dee1ad47SJeff Kirsher #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ 2838dee1ad47SJeff Kirsher 2839dee1ad47SJeff Kirsher /* IGP01E1000 DSP reset macros */ 2840dee1ad47SJeff Kirsher #define DSP_RESET_ENABLE 0x0 2841dee1ad47SJeff Kirsher #define DSP_RESET_DISABLE 0x2 2842dee1ad47SJeff Kirsher #define E1000_MAX_DSP_RESETS 10 2843dee1ad47SJeff Kirsher 2844dee1ad47SJeff Kirsher /* IGP01E1000 & IGP02E1000 AGC Registers */ 2845dee1ad47SJeff Kirsher 2846dee1ad47SJeff Kirsher #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 2847dee1ad47SJeff Kirsher #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ 2848dee1ad47SJeff Kirsher 2849dee1ad47SJeff Kirsher /* IGP02E1000 AGC Register Length 9-bit mask */ 2850dee1ad47SJeff Kirsher #define IGP02E1000_AGC_LENGTH_MASK 0x7F 2851dee1ad47SJeff Kirsher 2852dee1ad47SJeff Kirsher /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ 2853dee1ad47SJeff Kirsher #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 2854dee1ad47SJeff Kirsher #define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113 2855dee1ad47SJeff Kirsher 2856dee1ad47SJeff Kirsher /* The precision error of the cable length is +/- 10 meters */ 2857dee1ad47SJeff Kirsher #define IGP01E1000_AGC_RANGE 10 2858dee1ad47SJeff Kirsher #define IGP02E1000_AGC_RANGE 15 2859dee1ad47SJeff Kirsher 2860dee1ad47SJeff Kirsher /* IGP01E1000 PCS Initialization register */ 2861dee1ad47SJeff Kirsher /* bits 3:6 in the PCS registers stores the channels polarity */ 2862dee1ad47SJeff Kirsher #define IGP01E1000_PHY_POLARITY_MASK 0x0078 2863dee1ad47SJeff Kirsher 2864dee1ad47SJeff Kirsher /* IGP01E1000 GMII FIFO Register */ 2865dee1ad47SJeff Kirsher #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 2866dee1ad47SJeff Kirsher * on Link-Up */ 2867dee1ad47SJeff Kirsher #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 2868dee1ad47SJeff Kirsher 2869dee1ad47SJeff Kirsher /* IGP01E1000 Analog Register */ 2870dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 2871dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 2872dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC 2873dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE 2874dee1ad47SJeff Kirsher 2875dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 2876dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 2877dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 2878dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 2879dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 2880dee1ad47SJeff Kirsher 2881dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 2882dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 2883dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 2884dee1ad47SJeff Kirsher #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 2885dee1ad47SJeff Kirsher 2886dee1ad47SJeff Kirsher /* Bit definitions for valid PHY IDs. */ 2887dee1ad47SJeff Kirsher /* I = Integrated 2888dee1ad47SJeff Kirsher * E = External 2889dee1ad47SJeff Kirsher */ 2890dee1ad47SJeff Kirsher #define M88_VENDOR 0x0141 2891dee1ad47SJeff Kirsher #define M88E1000_E_PHY_ID 0x01410C50 2892dee1ad47SJeff Kirsher #define M88E1000_I_PHY_ID 0x01410C30 2893dee1ad47SJeff Kirsher #define M88E1011_I_PHY_ID 0x01410C20 2894dee1ad47SJeff Kirsher #define IGP01E1000_I_PHY_ID 0x02A80380 2895dee1ad47SJeff Kirsher #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 2896dee1ad47SJeff Kirsher #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 2897dee1ad47SJeff Kirsher #define M88E1011_I_REV_4 0x04 2898dee1ad47SJeff Kirsher #define M88E1111_I_PHY_ID 0x01410CC0 2899dee1ad47SJeff Kirsher #define M88E1118_E_PHY_ID 0x01410E40 2900dee1ad47SJeff Kirsher #define L1LXT971A_PHY_ID 0x001378E0 2901dee1ad47SJeff Kirsher 2902dee1ad47SJeff Kirsher #define RTL8211B_PHY_ID 0x001CC910 2903dee1ad47SJeff Kirsher #define RTL8201N_PHY_ID 0x8200 2904dee1ad47SJeff Kirsher #define RTL_PHY_CTRL_FD 0x0100 /* Full duplex.0=half; 1=full */ 2905dee1ad47SJeff Kirsher #define RTL_PHY_CTRL_SPD_100 0x200000 /* Force 100Mb */ 2906dee1ad47SJeff Kirsher 2907dee1ad47SJeff Kirsher /* Bits... 2908dee1ad47SJeff Kirsher * 15-5: page 2909dee1ad47SJeff Kirsher * 4-0: register offset 2910dee1ad47SJeff Kirsher */ 2911dee1ad47SJeff Kirsher #define PHY_PAGE_SHIFT 5 2912dee1ad47SJeff Kirsher #define PHY_REG(page, reg) \ 2913dee1ad47SJeff Kirsher (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 2914dee1ad47SJeff Kirsher 2915dee1ad47SJeff Kirsher #define IGP3_PHY_PORT_CTRL \ 2916dee1ad47SJeff Kirsher PHY_REG(769, 17) /* Port General Configuration */ 2917dee1ad47SJeff Kirsher #define IGP3_PHY_RATE_ADAPT_CTRL \ 2918dee1ad47SJeff Kirsher PHY_REG(769, 25) /* Rate Adapter Control Register */ 2919dee1ad47SJeff Kirsher 2920dee1ad47SJeff Kirsher #define IGP3_KMRN_FIFO_CTRL_STATS \ 2921dee1ad47SJeff Kirsher PHY_REG(770, 16) /* KMRN FIFO's control/status register */ 2922dee1ad47SJeff Kirsher #define IGP3_KMRN_POWER_MNG_CTRL \ 2923dee1ad47SJeff Kirsher PHY_REG(770, 17) /* KMRN Power Management Control Register */ 2924dee1ad47SJeff Kirsher #define IGP3_KMRN_INBAND_CTRL \ 2925dee1ad47SJeff Kirsher PHY_REG(770, 18) /* KMRN Inband Control Register */ 2926dee1ad47SJeff Kirsher #define IGP3_KMRN_DIAG \ 2927dee1ad47SJeff Kirsher PHY_REG(770, 19) /* KMRN Diagnostic register */ 2928dee1ad47SJeff Kirsher #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ 2929dee1ad47SJeff Kirsher #define IGP3_KMRN_ACK_TIMEOUT \ 2930dee1ad47SJeff Kirsher PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ 2931dee1ad47SJeff Kirsher 2932dee1ad47SJeff Kirsher #define IGP3_VR_CTRL \ 2933dee1ad47SJeff Kirsher PHY_REG(776, 18) /* Voltage regulator control register */ 2934dee1ad47SJeff Kirsher #define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ 2935dee1ad47SJeff Kirsher #define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ 2936dee1ad47SJeff Kirsher 2937dee1ad47SJeff Kirsher #define IGP3_CAPABILITY \ 2938dee1ad47SJeff Kirsher PHY_REG(776, 19) /* IGP3 Capability Register */ 2939dee1ad47SJeff Kirsher 2940dee1ad47SJeff Kirsher /* Capabilities for SKU Control */ 2941dee1ad47SJeff Kirsher #define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ 2942dee1ad47SJeff Kirsher #define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ 2943dee1ad47SJeff Kirsher #define IGP3_CAP_ASF 0x0004 /* Support ASF */ 2944dee1ad47SJeff Kirsher #define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ 2945dee1ad47SJeff Kirsher #define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ 2946dee1ad47SJeff Kirsher #define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ 2947dee1ad47SJeff Kirsher #define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ 2948dee1ad47SJeff Kirsher #define IGP3_CAP_RSS 0x0080 /* Support RSS */ 2949dee1ad47SJeff Kirsher #define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ 2950dee1ad47SJeff Kirsher #define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ 2951dee1ad47SJeff Kirsher 2952dee1ad47SJeff Kirsher #define IGP3_PPC_JORDAN_EN 0x0001 2953dee1ad47SJeff Kirsher #define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 2954dee1ad47SJeff Kirsher 2955dee1ad47SJeff Kirsher #define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001 2956dee1ad47SJeff Kirsher #define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E 2957dee1ad47SJeff Kirsher #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 2958dee1ad47SJeff Kirsher #define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 2959dee1ad47SJeff Kirsher 2960dee1ad47SJeff Kirsher #define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ 2961dee1ad47SJeff Kirsher #define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ 2962dee1ad47SJeff Kirsher 2963dee1ad47SJeff Kirsher #define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) 2964dee1ad47SJeff Kirsher #define IGP3_KMRN_EC_DIS_INBAND 0x0080 2965dee1ad47SJeff Kirsher 2966dee1ad47SJeff Kirsher #define IGP03E1000_E_PHY_ID 0x02A80390 2967dee1ad47SJeff Kirsher #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ 2968dee1ad47SJeff Kirsher #define IFE_PLUS_E_PHY_ID 0x02A80320 2969dee1ad47SJeff Kirsher #define IFE_C_E_PHY_ID 0x02A80310 2970dee1ad47SJeff Kirsher 2971dee1ad47SJeff Kirsher #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ 2972dee1ad47SJeff Kirsher #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ 2973dee1ad47SJeff Kirsher #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ 2974dee1ad47SJeff Kirsher #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */ 2975dee1ad47SJeff Kirsher #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ 2976dee1ad47SJeff Kirsher #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ 2977dee1ad47SJeff Kirsher #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ 2978dee1ad47SJeff Kirsher #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ 2979dee1ad47SJeff Kirsher #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ 2980dee1ad47SJeff Kirsher #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ 2981dee1ad47SJeff Kirsher #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ 2982dee1ad47SJeff Kirsher #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ 2983dee1ad47SJeff Kirsher #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ 2984dee1ad47SJeff Kirsher 2985dee1ad47SJeff Kirsher #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */ 2986dee1ad47SJeff Kirsher #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ 2987dee1ad47SJeff Kirsher #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ 2988dee1ad47SJeff Kirsher #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ 2989dee1ad47SJeff Kirsher #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ 2990dee1ad47SJeff Kirsher #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ 2991dee1ad47SJeff Kirsher #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ 2992dee1ad47SJeff Kirsher #define IFE_PESC_POLARITY_REVERSED_SHIFT 8 2993dee1ad47SJeff Kirsher 2994dee1ad47SJeff Kirsher #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */ 2995dee1ad47SJeff Kirsher #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ 2996dee1ad47SJeff Kirsher #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ 2997dee1ad47SJeff Kirsher #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ 2998dee1ad47SJeff Kirsher #define IFE_PSC_FORCE_POLARITY_SHIFT 5 2999dee1ad47SJeff Kirsher #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 3000dee1ad47SJeff Kirsher 3001dee1ad47SJeff Kirsher #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ 3002dee1ad47SJeff Kirsher #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ 3003dee1ad47SJeff Kirsher #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 3004dee1ad47SJeff Kirsher #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ 3005dee1ad47SJeff Kirsher #define IFE_PMC_MDIX_MODE_SHIFT 6 3006dee1ad47SJeff Kirsher #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ 3007dee1ad47SJeff Kirsher 3008dee1ad47SJeff Kirsher #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ 3009dee1ad47SJeff Kirsher #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ 3010dee1ad47SJeff Kirsher #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ 3011dee1ad47SJeff Kirsher #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ 3012dee1ad47SJeff Kirsher #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ 3013dee1ad47SJeff Kirsher #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ 3014dee1ad47SJeff Kirsher #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ 3015dee1ad47SJeff Kirsher #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ 3016dee1ad47SJeff Kirsher #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ 3017dee1ad47SJeff Kirsher #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 3018dee1ad47SJeff Kirsher #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 3019dee1ad47SJeff Kirsher 3020dee1ad47SJeff Kirsher #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 3021dee1ad47SJeff Kirsher #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 3022dee1ad47SJeff Kirsher #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 3023dee1ad47SJeff Kirsher #define ICH_FLASH_SEG_SIZE_256 256 3024dee1ad47SJeff Kirsher #define ICH_FLASH_SEG_SIZE_4K 4096 3025dee1ad47SJeff Kirsher #define ICH_FLASH_SEG_SIZE_64K 65536 3026dee1ad47SJeff Kirsher 3027dee1ad47SJeff Kirsher #define ICH_CYCLE_READ 0x0 3028dee1ad47SJeff Kirsher #define ICH_CYCLE_RESERVED 0x1 3029dee1ad47SJeff Kirsher #define ICH_CYCLE_WRITE 0x2 3030dee1ad47SJeff Kirsher #define ICH_CYCLE_ERASE 0x3 3031dee1ad47SJeff Kirsher 3032dee1ad47SJeff Kirsher #define ICH_FLASH_GFPREG 0x0000 3033dee1ad47SJeff Kirsher #define ICH_FLASH_HSFSTS 0x0004 3034dee1ad47SJeff Kirsher #define ICH_FLASH_HSFCTL 0x0006 3035dee1ad47SJeff Kirsher #define ICH_FLASH_FADDR 0x0008 3036dee1ad47SJeff Kirsher #define ICH_FLASH_FDATA0 0x0010 3037dee1ad47SJeff Kirsher #define ICH_FLASH_FRACC 0x0050 3038dee1ad47SJeff Kirsher #define ICH_FLASH_FREG0 0x0054 3039dee1ad47SJeff Kirsher #define ICH_FLASH_FREG1 0x0058 3040dee1ad47SJeff Kirsher #define ICH_FLASH_FREG2 0x005C 3041dee1ad47SJeff Kirsher #define ICH_FLASH_FREG3 0x0060 3042dee1ad47SJeff Kirsher #define ICH_FLASH_FPR0 0x0074 3043dee1ad47SJeff Kirsher #define ICH_FLASH_FPR1 0x0078 3044dee1ad47SJeff Kirsher #define ICH_FLASH_SSFSTS 0x0090 3045dee1ad47SJeff Kirsher #define ICH_FLASH_SSFCTL 0x0092 3046dee1ad47SJeff Kirsher #define ICH_FLASH_PREOP 0x0094 3047dee1ad47SJeff Kirsher #define ICH_FLASH_OPTYPE 0x0096 3048dee1ad47SJeff Kirsher #define ICH_FLASH_OPMENU 0x0098 3049dee1ad47SJeff Kirsher 3050dee1ad47SJeff Kirsher #define ICH_FLASH_REG_MAPSIZE 0x00A0 3051dee1ad47SJeff Kirsher #define ICH_FLASH_SECTOR_SIZE 4096 3052dee1ad47SJeff Kirsher #define ICH_GFPREG_BASE_MASK 0x1FFF 3053dee1ad47SJeff Kirsher #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 3054dee1ad47SJeff Kirsher 3055dee1ad47SJeff Kirsher /* Miscellaneous PHY bit definitions. */ 3056dee1ad47SJeff Kirsher #define PHY_PREAMBLE 0xFFFFFFFF 3057dee1ad47SJeff Kirsher #define PHY_SOF 0x01 3058dee1ad47SJeff Kirsher #define PHY_OP_READ 0x02 3059dee1ad47SJeff Kirsher #define PHY_OP_WRITE 0x01 3060dee1ad47SJeff Kirsher #define PHY_TURNAROUND 0x02 3061dee1ad47SJeff Kirsher #define PHY_PREAMBLE_SIZE 32 3062dee1ad47SJeff Kirsher #define MII_CR_SPEED_1000 0x0040 3063dee1ad47SJeff Kirsher #define MII_CR_SPEED_100 0x2000 3064dee1ad47SJeff Kirsher #define MII_CR_SPEED_10 0x0000 3065dee1ad47SJeff Kirsher #define E1000_PHY_ADDRESS 0x01 3066dee1ad47SJeff Kirsher #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 3067dee1ad47SJeff Kirsher #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 3068dee1ad47SJeff Kirsher #define PHY_REVISION_MASK 0xFFFFFFF0 3069dee1ad47SJeff Kirsher #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 3070dee1ad47SJeff Kirsher #define REG4_SPEED_MASK 0x01E0 3071dee1ad47SJeff Kirsher #define REG9_SPEED_MASK 0x0300 3072dee1ad47SJeff Kirsher #define ADVERTISE_10_HALF 0x0001 3073dee1ad47SJeff Kirsher #define ADVERTISE_10_FULL 0x0002 3074dee1ad47SJeff Kirsher #define ADVERTISE_100_HALF 0x0004 3075dee1ad47SJeff Kirsher #define ADVERTISE_100_FULL 0x0008 3076dee1ad47SJeff Kirsher #define ADVERTISE_1000_HALF 0x0010 3077dee1ad47SJeff Kirsher #define ADVERTISE_1000_FULL 0x0020 3078dee1ad47SJeff Kirsher #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 3079dee1ad47SJeff Kirsher #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */ 3080dee1ad47SJeff Kirsher #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */ 3081dee1ad47SJeff Kirsher 3082dee1ad47SJeff Kirsher #endif /* _E1000_HW_H_ */ 3083