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Searched +full:rx +full:- +full:input (Results 1 – 25 of 201) sorted by relevance

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/openbmc/u-boot/board/freescale/common/
H A Dvsc3316_3308.c1 // SPDX-License-Identifier: GPL-2.0+
31 " for 2-wire interface\n", vsc_addr); in vsc_if_enable()
33 /* enable 2-wire Serial InterFace (I2C) */ in vsc_if_enable()
58 return -ENODEV; in vsc3316_config()
63 printf("VSC:0x%x could not configured for 2-wire I/F.\n", in vsc3316_config()
68 /* config connections - page 0x00 */ in vsc3316_config()
72 * input to output */ in vsc3316_config()
76 /* input state - page 0x13 */ in vsc3316_config()
78 /* Configuring the required input of the switch */ in vsc3316_config()
82 /* Setting Global Input LOS threshold value */ in vsc3316_config()
[all …]
/openbmc/qemu/tests/qtest/fuzz/
H A Dvirtio_net_fuzz.c2 * virtio-net Fuzzing Target
10 * See the COPYING file in the top-level directory.
15 #include "standard-headers/linux/virtio_config.h"
17 #include "tests/qtest/libqos/virtio-net.h"
38 uint8_t rx; in virtio_net_fuzz_multi() member
46 QVirtioDevice *dev = net_if->vdev; in virtio_net_fuzz_multi()
52 Size -= sizeof(vqa); in virtio_net_fuzz_multi()
54 q = net_if->queues[vqa.queue % 3]; in virtio_net_fuzz_multi()
60 * backend. Otherwise, always place the input on a virtqueue. in virtio_net_fuzz_multi()
62 if (vqa.rx && sockfds_initialized) { in virtio_net_fuzz_multi()
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/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md18 …<https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-spec…
29 MCTP-compliant endpoints must accept.
31 ### IBF: Input Buffer Full
33 A hardware-defined flag bit in a KCS device's Status Register (STR). The IBF
35 Input Data Register (IDR).
37 ### IDR: Input Data Register
42 ### KCS: Keyboard-Controller-Style
48 systems. This interface is available built-in to several commercially available
49 microcontrollers. Data is transferred across the KCS interface using a per-byte
68 values larger than the BTU may improve throughput for data-intensive transfers.
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/openbmc/u-boot/drivers/serial/
H A Dserial_pic32.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dt-bindings/clock/microchip,clock.h>
64 writel(div - 1, base + U_BRG); in pic32_serial_init()
66 /* enable the UART for TX and RX */ in pic32_serial_init()
74 /* Check whether any char pending in RX fifo */
77 /* check if rx buffer overrun error has occurred */ in pic32_uart_pending_input()
86 * chars in rx-fifo. Only it can be known whether there is any. in pic32_uart_pending_input()
91 static int pic32_uart_pending(struct udevice *dev, bool input) in pic32_uart_pending() argument
95 if (input) in pic32_uart_pending()
96 return pic32_uart_pending_input(priv->base); in pic32_uart_pending()
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H A Dserial_zynq.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
22 #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
25 #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
27 #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
32 u32 control; /* 0x0 - Control Register [8:0] */
33 u32 mode; /* 0x4 - Mode Register [10:0] */
35 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
37 u32 channel_sts; /* 0x2c - Channel Status [11:0] */
38 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
[all …]
H A Dlpc32xx_hsuart.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
21 struct hsuart_regs *hsuart = priv->hsuart; in lpc32xx_serial_setbrg()
25 div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1; in lpc32xx_serial_setbrg()
29 writel(div, &hsuart->rate); in lpc32xx_serial_setbrg()
37 struct hsuart_regs *hsuart = priv->hsuart; in lpc32xx_serial_getc()
39 if (!(readl(&hsuart->level) & HSUART_LEVEL_RX)) in lpc32xx_serial_getc()
40 return -EAGAIN; in lpc32xx_serial_getc()
42 return readl(&hsuart->rx) & HSUART_RX_DATA; in lpc32xx_serial_getc()
48 struct hsuart_regs *hsuart = priv->hsuart; in lpc32xx_serial_putc()
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H A Dserial_uniphier.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2015 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
22 u32 rx; /* In: Receive buffer */ member
23 #define tx rx /* Out: Transmit buffer */
43 ((struct uniphier_serial_priv *)dev_get_priv(dev))->membase
52 divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate); in uniphier_serial_setbrg()
54 writel(divisor, &port->dlr); in uniphier_serial_setbrg()
63 if (!(readl(&port->lsr) & UART_LSR_DR)) in uniphier_serial_getc()
64 return -EAGAIN; in uniphier_serial_getc()
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H A Daltera_uart.c1 // SPDX-License-Identifier: GPL-2.0+
18 #define ALTERA_UART_RRDY BIT(7) /* rx ready */
21 u32 rxdata; /* Rx data reg */
26 u32 endofpacket; /* End-of-packet reg */
36 struct altera_uart_platdata *plat = dev->platdata; in altera_uart_setbrg()
37 struct altera_uart_regs *const regs = plat->regs; in altera_uart_setbrg()
40 div = (plat->uartclk / baudrate) - 1; in altera_uart_setbrg()
41 writel(div, &regs->divisor); in altera_uart_setbrg()
48 struct altera_uart_platdata *plat = dev->platdata; in altera_uart_putc()
49 struct altera_uart_regs *const regs = plat->regs; in altera_uart_putc()
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H A Dserial_owl.c1 // SPDX-License-Identifier: GPL-2.0+
31 #define OWL_UART_STAT_RFFS BIT(9) /* RX FIFO full Status */
33 #define OWL_UART_STAT_RFEM BIT(5) /* RX FIFO Empty Status */
49 if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_RFEM) in owl_serial_getc()
50 return -EAGAIN; in owl_serial_getc()
52 return (int)(readl(priv->base + OWL_UART_RXDAT)); in owl_serial_getc()
59 if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_TFFU) in owl_serial_putc()
60 return -EAGAIN; in owl_serial_putc()
62 writel(ch, priv->base + OWL_UART_TXDAT); in owl_serial_putc()
67 static int owl_serial_pending(struct udevice *dev, bool input) in owl_serial_pending() argument
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H A Dserial_bcm6345.c1 // SPDX-License-Identifier: GPL-2.0+
89 /* enable rx & tx operation on uart */
96 /* disable rx & tx operation on uart */
103 /* clear all unread data in rx fifo and unsent data in tx fifo */
106 /* empty rx and tx fifo */ in bcm6345_serial_flush()
124 /* clear rx timeout */ in bcm6345_serial_init()
163 val = (val >> 1) - 1; in bcm6345_serial_init()
175 static int bcm6345_serial_pending(struct udevice *dev, bool input) in bcm6345_serial_pending() argument
178 u32 val = readl(priv->base + UART_IR_REG); in bcm6345_serial_pending()
180 if (input) in bcm6345_serial_pending()
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H A DKconfig11 Select a default baudrate, where "default" has a driver-specific
19 # non-dm serial code
34 in U-Boot.
41 In very space-constrained devices even the full UART driver is too
43 This option enables the full UART in U-Boot, so if is it disabled,
51 In very space-constrained devices even the full UART driver is too
61 In very space-constrained devices even the full UART driver is too
110 bool "Enable RX buffer for serial input"
113 Enable RX buffer support for the serial driver. This enables
114 pasting longer strings, even when the RX FIFO of the UART is
[all …]
H A Dserial_mpc8xx.c1 // SPDX-License-Identifier: GPL-2.0+
32 cbd_t rxbd; /* Rx BD */
35 uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
41 int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate; in serial_setdivisor()
51 out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN); in serial_setdivisor()
53 out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN | in serial_setdivisor()
65 cpm8xx_t __iomem *cp = &(im->im_cpm); in serial_mpc8xx_setbrg()
73 out_be32(&cp->cp_simode, 0); in serial_mpc8xx_setbrg()
85 cpm8xx_t __iomem *cp = &(im->im_cpm); in serial_mpc8xx_probe()
90 sp = cp->cp_smc + SMC_INDEX; in serial_mpc8xx_probe()
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/openbmc/u-boot/doc/device-tree-bindings/serial/
H A Domap_serial.txt4 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
5 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
6 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
7 - compatible : should be "ti,am4372-uart" for AM437x controllers
8 - compatible : should be "ti,am3352-uart" for AM335x controllers
9 - compatible : should be "ti,dra742-uart" for DRA7x controllers
10 - reg : address and length of the register space
11 - interrupts or interrupts-extended : Should contain the uart interrupt
15 - ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
18 - clock-frequency : frequency of the clock input to the UART
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 - 2015 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
38 wakeup-source;
45 wakeup-source;
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 - 2015 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
38 ps-clk-frequency = <33333333>;
43 phy-mode = "rgmii-id";
[all …]
H A Dkirkwood-blackarmor-nas220.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
13 #include "kirkwood-6192.dtsi"
17 compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192",
27 stdout-path = &uart0;
31 compatible = "gpio-poweroff";
36 compatible = "gpio-keys";
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H A Ddra7-evm-common.dtsi2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clk/ti-dra7-atl.h>
11 #include <dt-bindings/input/input.h>
15 stdout-path = &uart1;
19 compatible = "linux,extcon-usb-gpio";
20 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
24 compatible = "simple-audio-card";
25 simple-audio-card,name = "DRA7xx-EVM";
26 simple-audio-card,widgets =
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/openbmc/u-boot/doc/device-tree-bindings/adc/
H A Dst,stm32-adc.txt3 STM32 ADC is a successive approximation analog-to-digital converter.
4 It has several multiplexed input channels. Conversions can be performed
6 stored in a left-aligned or right-aligned 32-bit data register.
9 The analog watchdog feature allows the application to detect if the input
10 voltage goes beyond the user-defined, higher or lower thresholds.
16 - regular conversion can be done in sequence, running in background
17 - injected conversions have higher priority, and so have the ability to
22 -----------------------------------
24 - compatible: Should be one of:
25 "st,stm32f4-adc-core"
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/openbmc/phosphor-debug-collector/tools/dreport.d/
H A Ddreport14 -n, —-name <name> Name to be used for the archive.
16 -d, —-dir <directory> Archive directory to copy the compressed report.
18 -i, —-id <id> Dump identifier to associate with the archive.
21 -t, —-type <type> Data collection type. Valid types are
24 -p, —-path <path> Optional contents to be included in the archive.
25 Valid paths are absolute file path or d-bus path
27 -Absolute file path for "core" type.
28 -elog d-bus object for "elog" type.
29 -s, --size <size> Maximum allowed size(in KB) of the archive.
32 -v, —-verbose Increase logging verbosity.
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/openbmc/qemu/hw/net/
H A De1000x_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
115 * RW - register is both readable and writable
116 * RO - register is read only
117 * WO - register is write only
118 * R/clr - register is read only and is cleared when read
119 * A - register array
121 #define E1000_CTRL 0x00000 /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
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/openbmc/u-boot/include/
H A Dserial.h122 SERIAL_CHIP_UNKNOWN = -1,
132 * struct serial_device_info - structure to hold serial device info
155 * struct struct dm_serial_ops - Driver model serial operations
162 * setbrg() - Set up the baud rate generator
167 * available rate. or return -EINVAL if this is not possible.
171 * @return 0 if OK, -ve on error
175 * getc() - Read a character and return it
177 * If no character is available, this should return -EAGAIN without
181 * @return character (0..255), -ve on error
185 * putc() - Write a character
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos_mipi_dsi.txt1 Exynos MIPI-DSIM Controller
6 compatible: should be "samsung,exynos-mipi-dsi"
7 reg: Base address of MIPI-DSIM IP.
10 samsung,dsim-config-e-interface: interface to be used (RGB interface
12 samsung,dsim-config-e-virtual-ch: virtual channel number that main
14 samsung,dsim-config-e-pixel-format: pixel stream format for main
16 samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
17 in Non-burst mode, RGB data area is filled with RGB data and
18 NULL packets, according to input bandwidth of RGB interface.
19 samsung,dsim-config-e-no-data-lane: data lane count used by Master.
[all …]
/openbmc/u-boot/drivers/pinctrl/
H A Dpinctrl-sandbox.c1 // SPDX-License-Identifier: GPL-2.0+
16 "RX",
24 "Uart RX",
25 "1-wire gpio",
44 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
45 { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 },
46 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
47 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
48 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
49 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
[all …]
/openbmc/openbmc-test-automation/pldm/
H A Dtest_pldm_base.robot64 [Documentation] Verify supported PLDM version for oem-ibm type.
67 ${pldm_cmd}= Evaluate $CMD_GETPLDMVERSION % 'oem-ibm'
102 ${pldm_output}= Pldmtool base GetPLDMTypes -v
104 Should Contain ${pldm_output} pldmtool: Rx:
106 ${pldm_output}= Pldmtool bios GetDateTime -v
108 Should Contain ${pldm_output} pldmtool: Rx:
116 # pldmtool raw -d 0x80 0x00 0x04
118 # pldmtool: Rx: 00 00 04 00 1d 00 00 00 00 00 00 80
129 # pldmtool raw -d 0x80 0x00 0x04 -
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/openbmc/qemu/hw/char/
H A Dbcm2835_aux.c14 * At present only the core UART functions (data path for tx/rx) are
16 * - Line/modem control
17 * - Scratch register
18 * - Extra control
19 * - Baudrate
20 * - SPI interfaces
26 #include "hw/qdev-properties.h"
27 #include "hw/qdev-properties-system.h"
53 * 1. rx interrupt is enabled and we have a non-empty rx fifo, or in bcm2835_aux_update()
56 s->iir = 0; in bcm2835_aux_update()
[all …]

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