1 // SPDX-License-Identifier: GPL-2.0+
4  * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
22 #define ZYNQ_UART_SR_RXEMPTY	BIT(1) /* RX FIFO empty */
25 #define ZYNQ_UART_CR_RX_EN	BIT(2) /* RX enabled */
27 #define ZYNQ_UART_CR_RXRST	BIT(0) /* RX logic reset */
32 	u32 control; /* 0x0 - Control Register [8:0] */
33 	u32 mode; /* 0x4 - Mode Register [10:0] */
35 	u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
37 	u32 channel_sts; /* 0x2c - Channel Status [11:0] */
38 	u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
39 	u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
54 	/* Covering case where input clock is so slow */  in _uart_zynq_serial_setbrg()
59 	 * Baud rate = ------------------  in _uart_zynq_serial_setbrg()
76 			calc_bauderror = baud - calc_baud;  in _uart_zynq_serial_setbrg()
78 			calc_bauderror = calc_baud - baud;  in _uart_zynq_serial_setbrg()
83 	writel(bdiv, &regs->baud_rate_divider);  in _uart_zynq_serial_setbrg()
84 	writel(bgen, &regs->baud_rate_gen);  in _uart_zynq_serial_setbrg()
90 	/* RX/TX enabled & reset */  in _uart_zynq_serial_init()
92 					ZYNQ_UART_CR_RXRST, &regs->control);  in _uart_zynq_serial_init()
93 	writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */  in _uart_zynq_serial_init()
98 	if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)  in _uart_zynq_serial_putc()
99 		return -EAGAIN;  in _uart_zynq_serial_putc()
101 	writel(c, &regs->tx_rx_fifo);  in _uart_zynq_serial_putc()
128 	if (ret && ret != -ENOSYS) {  in zynq_serial_setbrg()
133 	_uart_zynq_serial_setbrg(platdata->regs, clock, baudrate);  in zynq_serial_setbrg()
143 	if (gd->flags & GD_FLG_RELOC)  in zynq_serial_probe()
146 	_uart_zynq_serial_init(platdata->regs);  in zynq_serial_probe()
154 	struct uart_zynq *regs = platdata->regs;  in zynq_serial_getc()
156 	if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)  in zynq_serial_getc()
157 		return -EAGAIN;  in zynq_serial_getc()
159 	return readl(&regs->tx_rx_fifo);  in zynq_serial_getc()
166 	return _uart_zynq_serial_putc(platdata->regs, ch);  in zynq_serial_putc()
169 static int zynq_serial_pending(struct udevice *dev, bool input)  in zynq_serial_pending()  argument
172 	struct uart_zynq *regs = platdata->regs;  in zynq_serial_pending()
174 	if (input)  in zynq_serial_pending()
175 		return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);  in zynq_serial_pending()
177 		return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);  in zynq_serial_pending()
184 	platdata->regs = (struct uart_zynq *)dev_read_addr(dev);  in zynq_serial_ofdata_to_platdata()
185 	if (IS_ERR(platdata->regs))  in zynq_serial_ofdata_to_platdata()
186 		return PTR_ERR(platdata->regs);  in zynq_serial_ofdata_to_platdata()
200 	{ .compatible = "cdns,uart-r1p8" },
201 	{ .compatible = "cdns,uart-r1p12" },
229 	while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)  in _debug_uart_putc()