1 // SPDX-License-Identifier: GPL-2.0+
18 #define ALTERA_UART_RRDY	BIT(7)	/* rx ready */
21 	u32	rxdata;		/* Rx data reg */
26 	u32	endofpacket;	/* End-of-packet reg */
36 	struct altera_uart_platdata *plat = dev->platdata;  in altera_uart_setbrg()
37 	struct altera_uart_regs *const regs = plat->regs;  in altera_uart_setbrg()
40 	div = (plat->uartclk / baudrate) - 1;  in altera_uart_setbrg()
41 	writel(div, &regs->divisor);  in altera_uart_setbrg()
48 	struct altera_uart_platdata *plat = dev->platdata;  in altera_uart_putc()
49 	struct altera_uart_regs *const regs = plat->regs;  in altera_uart_putc()
51 	if (!(readl(&regs->status) & ALTERA_UART_TRDY))  in altera_uart_putc()
52 		return -EAGAIN;  in altera_uart_putc()
54 	writel(ch, &regs->txdata);  in altera_uart_putc()
59 static int altera_uart_pending(struct udevice *dev, bool input)  in altera_uart_pending()  argument
61 	struct altera_uart_platdata *plat = dev->platdata;  in altera_uart_pending()
62 	struct altera_uart_regs *const regs = plat->regs;  in altera_uart_pending()
63 	u32 st = readl(&regs->status);  in altera_uart_pending()
65 	if (input)  in altera_uart_pending()
73 	struct altera_uart_platdata *plat = dev->platdata;  in altera_uart_getc()
74 	struct altera_uart_regs *const regs = plat->regs;  in altera_uart_getc()
76 	if (!(readl(&regs->status) & ALTERA_UART_RRDY))  in altera_uart_getc()
77 		return -EAGAIN;  in altera_uart_getc()
79 	return readl(&regs->rxdata) & 0xff;  in altera_uart_getc()
91 	plat->regs = map_physmem(devfdt_get_addr(dev),  in altera_uart_ofdata_to_platdata()
94 	plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),  in altera_uart_ofdata_to_platdata()
95 		"clock-frequency", 0);  in altera_uart_ofdata_to_platdata()
108 	{ .compatible = "altr,uart-1.0" },
131 	div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1;  in _debug_uart_init()
132 	writel(div, &regs->divisor);  in _debug_uart_init()
140 		u32 st = readl(&regs->status);  in _debug_uart_putc()
146 	writel(ch, &regs->txdata);  in _debug_uart_putc()