14  * At present only the core UART functions (data path for tx/rx) are
16  *  - Line/modem control
17  *  - Scratch register
18  *  - Extra control
19  *  - Baudrate
20  *  - SPI interfaces
26 #include "hw/qdev-properties.h"
27 #include "hw/qdev-properties-system.h"
53      * 1. rx interrupt is enabled and we have a non-empty rx fifo, or  in bcm2835_aux_update()
56     s->iir = 0;  in bcm2835_aux_update()
57     if ((s->ier & RX_INT) && s->read_count != 0) {  in bcm2835_aux_update()
58         s->iir |= RX_INT;  in bcm2835_aux_update()
60     if (s->ier & TX_INT) {  in bcm2835_aux_update()
61         s->iir |= TX_INT;  in bcm2835_aux_update()
63     qemu_set_irq(s->irq, s->iir != 0);  in bcm2835_aux_update()
73         return s->iir != 0;  in bcm2835_aux_read()
80         c = s->read_fifo[s->read_pos];  in bcm2835_aux_read()
81         if (s->read_count > 0) {  in bcm2835_aux_read()
82             s->read_count--;  in bcm2835_aux_read()
83             if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) {  in bcm2835_aux_read()
84                 s->read_pos = 0;  in bcm2835_aux_read()
87         qemu_chr_fe_accept_input(&s->chr);  in bcm2835_aux_read()
93         return 0xc0 | s->ier; /* FIFO enables always read 1 */  in bcm2835_aux_read()
97         /* The spec is unclear on what happens when both tx and rx  in bcm2835_aux_read()
99          * present, we choose to prioritise the rx interrupt, since  in bcm2835_aux_read()
101         if ((s->iir & RX_INT) && s->read_count != 0) {  in bcm2835_aux_read()
106         if (s->iir == 0) {  in bcm2835_aux_read()
121         if (s->read_count != 0) {  in bcm2835_aux_read()
135         return 0x3; /* tx, rx enabled */  in bcm2835_aux_read()
138         res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */  in bcm2835_aux_read()
139         if (s->read_count > 0) {  in bcm2835_aux_read()
140             res |= 0x1; /* data in input buffer */  in bcm2835_aux_read()
141             assert(s->read_count <= BCM2835_AUX_RX_FIFO_LEN);  in bcm2835_aux_read()
142             res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */  in bcm2835_aux_read()
177         qemu_chr_fe_write_all(&s->chr, &ch, 1);  in bcm2835_aux_write()
182         s->ier = value & (TX_INT | RX_INT);  in bcm2835_aux_write()
188             s->read_count = 0;  in bcm2835_aux_write()
224     return BCM2835_AUX_RX_FIFO_LEN - s->read_count;  in bcm2835_aux_can_receive()
232     slot = s->read_pos + s->read_count;  in bcm2835_aux_put_fifo()
234         slot -= BCM2835_AUX_RX_FIFO_LEN;  in bcm2835_aux_put_fifo()
236     s->read_fifo[slot] = value;  in bcm2835_aux_put_fifo()
237     s->read_count++;  in bcm2835_aux_put_fifo()
238     if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) {  in bcm2835_aux_put_fifo()
281     memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,  in bcm2835_aux_init()
283     sysbus_init_mmio(sbd, &s->iomem);  in bcm2835_aux_init()
284     sysbus_init_irq(sbd, &s->irq);  in bcm2835_aux_init()
291     qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,  in bcm2835_aux_realize()
303     dc->realize = bcm2835_aux_realize;  in bcm2835_aux_class_init()
304     dc->vmsd = &vmstate_bcm2835_aux;  in bcm2835_aux_class_init()
305     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);  in bcm2835_aux_class_init()