183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2194846f3SMichal Simek /*
3194846f3SMichal Simek * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4194846f3SMichal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
5194846f3SMichal Simek */
6194846f3SMichal Simek
759da82efSMichal Simek #include <clk.h>
8194846f3SMichal Simek #include <common.h>
942800ffaSSimon Glass #include <debug_uart.h>
1042800ffaSSimon Glass #include <dm.h>
11c54c0a4cSSimon Glass #include <errno.h>
12c9416b92SMichal Simek #include <fdtdec.h>
13194846f3SMichal Simek #include <watchdog.h>
14194846f3SMichal Simek #include <asm/io.h>
15194846f3SMichal Simek #include <linux/compiler.h>
16194846f3SMichal Simek #include <serial.h>
17194846f3SMichal Simek
18a6730255SMichal Simek DECLARE_GLOBAL_DATA_PTR;
19a6730255SMichal Simek
20c9a2c47bSMichal Simek #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
21e90d2659SMichal Simek #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
22c9a2c47bSMichal Simek #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
23194846f3SMichal Simek
24c9a2c47bSMichal Simek #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
25c9a2c47bSMichal Simek #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
26c9a2c47bSMichal Simek #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
27c9a2c47bSMichal Simek #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
28194846f3SMichal Simek
29194846f3SMichal Simek #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
30194846f3SMichal Simek
31194846f3SMichal Simek struct uart_zynq {
32a2425e62SMichal Simek u32 control; /* 0x0 - Control Register [8:0] */
33a2425e62SMichal Simek u32 mode; /* 0x4 - Mode Register [10:0] */
34194846f3SMichal Simek u32 reserved1[4];
35a2425e62SMichal Simek u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
36194846f3SMichal Simek u32 reserved2[4];
37a2425e62SMichal Simek u32 channel_sts; /* 0x2c - Channel Status [11:0] */
38a2425e62SMichal Simek u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
39a2425e62SMichal Simek u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
40194846f3SMichal Simek };
41194846f3SMichal Simek
42*6bdf0a99SMichal Simek struct zynq_uart_platdata {
4342800ffaSSimon Glass struct uart_zynq *regs;
44194846f3SMichal Simek };
45194846f3SMichal Simek
46194846f3SMichal Simek /* Set up the baud rate in gd struct */
_uart_zynq_serial_setbrg(struct uart_zynq * regs,unsigned long clock,unsigned long baud)47c54c0a4cSSimon Glass static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
48c54c0a4cSSimon Glass unsigned long clock, unsigned long baud)
49194846f3SMichal Simek {
50194846f3SMichal Simek /* Calculation results. */
51194846f3SMichal Simek unsigned int calc_bauderror, bdiv, bgen;
52194846f3SMichal Simek unsigned long calc_baud = 0;
53194846f3SMichal Simek
5404bc5c93SMichal Simek /* Covering case where input clock is so slow */
55c54c0a4cSSimon Glass if (clock < 1000000 && baud > 4800)
56c54c0a4cSSimon Glass baud = 4800;
5704bc5c93SMichal Simek
58194846f3SMichal Simek /* master clock
59194846f3SMichal Simek * Baud rate = ------------------
60194846f3SMichal Simek * bgen * (bdiv + 1)
61194846f3SMichal Simek *
62194846f3SMichal Simek * Find acceptable values for baud generation.
63194846f3SMichal Simek */
64194846f3SMichal Simek for (bdiv = 4; bdiv < 255; bdiv++) {
65194846f3SMichal Simek bgen = clock / (baud * (bdiv + 1));
66194846f3SMichal Simek if (bgen < 2 || bgen > 65535)
67194846f3SMichal Simek continue;
68194846f3SMichal Simek
69194846f3SMichal Simek calc_baud = clock / (bgen * (bdiv + 1));
70194846f3SMichal Simek
71194846f3SMichal Simek /*
72194846f3SMichal Simek * Use first calculated baudrate with
73194846f3SMichal Simek * an acceptable (<3%) error
74194846f3SMichal Simek */
75194846f3SMichal Simek if (baud > calc_baud)
76194846f3SMichal Simek calc_bauderror = baud - calc_baud;
77194846f3SMichal Simek else
78194846f3SMichal Simek calc_bauderror = calc_baud - baud;
79194846f3SMichal Simek if (((calc_bauderror * 100) / baud) < 3)
80194846f3SMichal Simek break;
81194846f3SMichal Simek }
82194846f3SMichal Simek
83194846f3SMichal Simek writel(bdiv, ®s->baud_rate_divider);
84194846f3SMichal Simek writel(bgen, ®s->baud_rate_gen);
85194846f3SMichal Simek }
86194846f3SMichal Simek
87c54c0a4cSSimon Glass /* Initialize the UART, with...some settings. */
_uart_zynq_serial_init(struct uart_zynq * regs)88c54c0a4cSSimon Glass static void _uart_zynq_serial_init(struct uart_zynq *regs)
89c54c0a4cSSimon Glass {
90c54c0a4cSSimon Glass /* RX/TX enabled & reset */
91c54c0a4cSSimon Glass writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
92c54c0a4cSSimon Glass ZYNQ_UART_CR_RXRST, ®s->control);
93c54c0a4cSSimon Glass writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
94c54c0a4cSSimon Glass }
95c54c0a4cSSimon Glass
_uart_zynq_serial_putc(struct uart_zynq * regs,const char c)96c54c0a4cSSimon Glass static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
97c54c0a4cSSimon Glass {
98e90d2659SMichal Simek if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
99c54c0a4cSSimon Glass return -EAGAIN;
100c54c0a4cSSimon Glass
101c54c0a4cSSimon Glass writel(c, ®s->tx_rx_fifo);
102c54c0a4cSSimon Glass
103c54c0a4cSSimon Glass return 0;
104c54c0a4cSSimon Glass }
105c54c0a4cSSimon Glass
zynq_serial_setbrg(struct udevice * dev,int baudrate)106b729ed0dSMichal Simek static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
107194846f3SMichal Simek {
108*6bdf0a99SMichal Simek struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
10959da82efSMichal Simek unsigned long clock;
110194846f3SMichal Simek
11159da82efSMichal Simek int ret;
11259da82efSMichal Simek struct clk clk;
11359da82efSMichal Simek
11459da82efSMichal Simek ret = clk_get_by_index(dev, 0, &clk);
11559da82efSMichal Simek if (ret < 0) {
11659da82efSMichal Simek dev_err(dev, "failed to get clock\n");
11759da82efSMichal Simek return ret;
11859da82efSMichal Simek }
11959da82efSMichal Simek
12059da82efSMichal Simek clock = clk_get_rate(&clk);
12159da82efSMichal Simek if (IS_ERR_VALUE(clock)) {
12259da82efSMichal Simek dev_err(dev, "failed to get rate\n");
12359da82efSMichal Simek return clock;
12459da82efSMichal Simek }
12559da82efSMichal Simek debug("%s: CLK %ld\n", __func__, clock);
12659da82efSMichal Simek
12759da82efSMichal Simek ret = clk_enable(&clk);
12859da82efSMichal Simek if (ret && ret != -ENOSYS) {
12959da82efSMichal Simek dev_err(dev, "failed to enable clock\n");
13059da82efSMichal Simek return ret;
13159da82efSMichal Simek }
132781745bdSStefan Herbrechtsmeier
133*6bdf0a99SMichal Simek _uart_zynq_serial_setbrg(platdata->regs, clock, baudrate);
134194846f3SMichal Simek
13542800ffaSSimon Glass return 0;
136194846f3SMichal Simek }
137194846f3SMichal Simek
zynq_serial_probe(struct udevice * dev)13842800ffaSSimon Glass static int zynq_serial_probe(struct udevice *dev)
139194846f3SMichal Simek {
140*6bdf0a99SMichal Simek struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
14142800ffaSSimon Glass
142a6730255SMichal Simek /* No need to reinitialize the UART after relocation */
143a6730255SMichal Simek if (gd->flags & GD_FLG_RELOC)
144a6730255SMichal Simek return 0;
145a6730255SMichal Simek
146*6bdf0a99SMichal Simek _uart_zynq_serial_init(platdata->regs);
14742800ffaSSimon Glass
14842800ffaSSimon Glass return 0;
149194846f3SMichal Simek }
150194846f3SMichal Simek
zynq_serial_getc(struct udevice * dev)15142800ffaSSimon Glass static int zynq_serial_getc(struct udevice *dev)
152194846f3SMichal Simek {
153*6bdf0a99SMichal Simek struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
154*6bdf0a99SMichal Simek struct uart_zynq *regs = platdata->regs;
155194846f3SMichal Simek
15642800ffaSSimon Glass if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
15742800ffaSSimon Glass return -EAGAIN;
158194846f3SMichal Simek
159194846f3SMichal Simek return readl(®s->tx_rx_fifo);
160194846f3SMichal Simek }
161194846f3SMichal Simek
zynq_serial_putc(struct udevice * dev,const char ch)16242800ffaSSimon Glass static int zynq_serial_putc(struct udevice *dev, const char ch)
163c9416b92SMichal Simek {
164*6bdf0a99SMichal Simek struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
165c9416b92SMichal Simek
166*6bdf0a99SMichal Simek return _uart_zynq_serial_putc(platdata->regs, ch);
167c9416b92SMichal Simek }
16851d8102fSTom Rini
zynq_serial_pending(struct udevice * dev,bool input)16942800ffaSSimon Glass static int zynq_serial_pending(struct udevice *dev, bool input)
17051d8102fSTom Rini {
171*6bdf0a99SMichal Simek struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
172*6bdf0a99SMichal Simek struct uart_zynq *regs = platdata->regs;
17342800ffaSSimon Glass
17442800ffaSSimon Glass if (input)
17542800ffaSSimon Glass return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
17642800ffaSSimon Glass else
17742800ffaSSimon Glass return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
17851d8102fSTom Rini }
179c54c0a4cSSimon Glass
zynq_serial_ofdata_to_platdata(struct udevice * dev)18042800ffaSSimon Glass static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
18142800ffaSSimon Glass {
182*6bdf0a99SMichal Simek struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
18342800ffaSSimon Glass
184*6bdf0a99SMichal Simek platdata->regs = (struct uart_zynq *)dev_read_addr(dev);
185*6bdf0a99SMichal Simek if (IS_ERR(platdata->regs))
186*6bdf0a99SMichal Simek return PTR_ERR(platdata->regs);
18742800ffaSSimon Glass
18842800ffaSSimon Glass return 0;
18942800ffaSSimon Glass }
19042800ffaSSimon Glass
19142800ffaSSimon Glass static const struct dm_serial_ops zynq_serial_ops = {
19242800ffaSSimon Glass .putc = zynq_serial_putc,
19342800ffaSSimon Glass .pending = zynq_serial_pending,
19442800ffaSSimon Glass .getc = zynq_serial_getc,
19542800ffaSSimon Glass .setbrg = zynq_serial_setbrg,
19642800ffaSSimon Glass };
19742800ffaSSimon Glass
19842800ffaSSimon Glass static const struct udevice_id zynq_serial_ids[] = {
19942800ffaSSimon Glass { .compatible = "xlnx,xuartps" },
20042800ffaSSimon Glass { .compatible = "cdns,uart-r1p8" },
201a2533183SMichal Simek { .compatible = "cdns,uart-r1p12" },
20242800ffaSSimon Glass { }
20342800ffaSSimon Glass };
20442800ffaSSimon Glass
2056bf87dacSMichal Simek U_BOOT_DRIVER(serial_zynq) = {
20642800ffaSSimon Glass .name = "serial_zynq",
20742800ffaSSimon Glass .id = UCLASS_SERIAL,
20842800ffaSSimon Glass .of_match = zynq_serial_ids,
20942800ffaSSimon Glass .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
210*6bdf0a99SMichal Simek .platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata),
21142800ffaSSimon Glass .probe = zynq_serial_probe,
21242800ffaSSimon Glass .ops = &zynq_serial_ops,
21342800ffaSSimon Glass };
21442800ffaSSimon Glass
215c54c0a4cSSimon Glass #ifdef CONFIG_DEBUG_UART_ZYNQ
_debug_uart_init(void)21680dc9997SMichal Simek static inline void _debug_uart_init(void)
217c54c0a4cSSimon Glass {
218c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
219c54c0a4cSSimon Glass
220c54c0a4cSSimon Glass _uart_zynq_serial_init(regs);
221c54c0a4cSSimon Glass _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
222c54c0a4cSSimon Glass CONFIG_BAUDRATE);
223c54c0a4cSSimon Glass }
224c54c0a4cSSimon Glass
_debug_uart_putc(int ch)225c54c0a4cSSimon Glass static inline void _debug_uart_putc(int ch)
226c54c0a4cSSimon Glass {
227c54c0a4cSSimon Glass struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
228c54c0a4cSSimon Glass
229c54c0a4cSSimon Glass while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
230c54c0a4cSSimon Glass WATCHDOG_RESET();
231c54c0a4cSSimon Glass }
232c54c0a4cSSimon Glass
233c54c0a4cSSimon Glass DEBUG_UART_FUNCS
234c54c0a4cSSimon Glass
235c54c0a4cSSimon Glass #endif
236