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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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/openbmc/u-boot/board/xes/xpedite537x/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
20 * There are four board-specific SDRAM timing parameters which must be
22 * 1.) CPO (Read Capture Delay)
23 * - TIMING_CFG_2 register
25 * chip-specific internal delays.
26 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
27 * - TIMING_CFG_2 register
31 * of 1/2 clock delay.
33 * - DDR_SDRAM_CLK_CNTL register
36 * - TIMING_CFG_2 register
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
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H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-dw-mshc
19 - samsung,exynos4412-dw-mshc
20 - samsung,exynos5250-dw-mshc
21 - samsung,exynos5420-dw-mshc
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H A Dsdhci-sprd.txt1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
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/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610-calibration.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
15 #include "ddrmc-vf610-calibration.h"
32 * Use those functions to determine those values on new HW, read the
36 * SW leveling supported operations - CR93[SW_LVL_MODE]:
38 * - 0x0 (b'00) - No leveling
40 * - 0x1 (b'01) - WRLVL_DL_X - It is not recommended to perform this tuning
41 * on HW designs utilizing non-flyback topology
50 * - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
51 * to the DQ signals so that the strobe edge is
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/openbmc/linux/drivers/media/usb/au0828/
H A Dau0828-i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/delay.h>
17 #include <media/v4l2-common.h>
28 struct au0828_dev *dev = i2c_adap->algo_data; in i2c_slave_did_read_ack()
51 struct au0828_dev *dev = i2c_adap->algo_data; in i2c_is_read_busy()
74 struct au0828_dev *dev = i2c_adap->algo_data; in i2c_is_write_done()
97 struct au0828_dev *dev = i2c_adap->algo_data; in i2c_is_busy()
122 int i, strobe = 0; in i2c_sendbytes() local
123 struct au0828_dev *dev = i2c_adap->algo_data; in i2c_sendbytes()
124 u8 i2c_speed = dev->board.i2c_clk_divider; in i2c_sendbytes()
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/openbmc/linux/sound/drivers/
H A Dportman2x4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) by Levent Guendogdu <levon@feature-it.com>
9 * - cleanup and rewrite
11 * - source code cleanup
13 * - fixed compilation problem with alsa 1.0.6a (removed MODULE_CLASSES,
17 * - added 2.6 kernel support
19 …* - added parport_unregister_driver to the startup routine if the driver fails to detect a po…
20 * - added support for all 4 output ports in portman_putmidi
22 * - added checks for opened input device in interrupt handler
24 * - ported from alsa 0.5 to 1.0
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/openbmc/linux/include/linux/
H A Dlp.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * usr/include/linux/lp.h c.1991-1992 James Wiegand
16 /* Magic numbers for defining port-device mappings */
17 #define LP_PARPORT_UNSPEC -4
18 #define LP_PARPORT_AUTO -3
19 #define LP_PARPORT_OFF -2
20 #define LP_PARPORT_NONE -1
25 #define LP_WAIT(minor) lp_table[(minor)].wait /* strobe wait */
26 #define LP_IRQ(minor) lp_table[(minor)].dev->port->irq /* interrupt # */
33 #define LP_BASE(x) lp_table[(x)].dev->port->base
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/openbmc/u-boot/include/
H A Dddr_spd.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
10 * Format from "JEDEC Standard No. 21-C,
37 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
39 Clk @ CL=X-0.5 (tAC) */
40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */
41 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
44 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
49 unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */
50 unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */
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/openbmc/u-boot/board/samtec/vining_2000/
H A Dimximage.cfg1 /* SPDX-License-Identifier: GPL-2.0+ */
24 * Addr-type Address Value
27 * Addr-type register length (1,2 or 4 bytes)
42 /* IOMUX - DDR IO Type */
62 /* Data Strobe */
80 /* Calibrations - ZQ */
87 /* DQS Read Gate */
91 /* Read/Write Delay */
95 /* Read data bit delay */
104 /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
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/openbmc/u-boot/board/freescale/mx6sxsabreauto/
H A Dimximage.cfg1 /* SPDX-License-Identifier: GPL-2.0+ */
24 * Addr-type Address Value
27 * Addr-type register length (1,2 or 4 bytes)
42 /* IOMUX - DDR IO Type */
62 /* Data Strobe */
80 /* Calibrations - ZQ */
87 /* DQS Read Gate */
91 /* Read/Write Delay */
97 /* read data bit delay */
106 /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
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/openbmc/u-boot/board/freescale/mx6sxsabresd/
H A Dimximage.cfg1 /* SPDX-License-Identifier: GPL-2.0+ */
24 * Addr-type Address Value
27 * Addr-type register length (1,2 or 4 bytes)
42 /* IOMUX - DDR IO Type */
62 /* Data Strobe */
80 /* Calibrations - ZQ */
87 /* DQS Read Gate */
91 /* Read/Write Delay */
95 /* Read data bit delay */
104 /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
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/openbmc/linux/drivers/media/i2c/
H A Dlm3646.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Ldd-Mlp <ldd-mlp@list.ti.com>
12 #include <linux/delay.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
78 container_of(_ctrl->handler, struct lm3646_flash, ctrls_led)
86 return regmap_write(flash->regmap, in lm3646_mode_ctrl()
87 REG_ENABLE, flash->mode_reg | MODE_SHDN); in lm3646_mode_ctrl()
89 return regmap_write(flash->regmap, in lm3646_mode_ctrl()
90 REG_ENABLE, flash->mode_reg | MODE_TORCH); in lm3646_mode_ctrl()
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/openbmc/u-boot/board/keymile/kmp204x/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
27 /* automatic calibration for nb of cycles between read and DQS pre */ in fsl_ddr_board_options()
28 popts->cpo_override = 0xFF; in fsl_ddr_board_options()
30 /* 1/2 clk delay between wr command and data strobe */ in fsl_ddr_board_options()
31 popts->write_data_delay = 4; in fsl_ddr_board_options()
33 popts->clk_adjust = 4; in fsl_ddr_board_options()
35 popts->twot_en = 0; in fsl_ddr_board_options()
38 popts->half_strength_driver_enable = 1; in fsl_ddr_board_options()
41 popts->wrlvl_override = 1; in fsl_ddr_board_options()
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/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-exynos.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "dw_mmc-pltfm.h"
20 #include "dw_mmc-exynos.h"
22 /* Variations in Exynos specific dw-mshc controller */
53 .compatible = "samsung,exynos4210-dw-mshc",
56 .compatible = "samsung,exynos4412-dw-mshc",
59 .compatible = "samsung,exynos5250-dw-mshc",
62 .compatible = "samsung,exynos5420-dw-mshc",
65 .compatible = "samsung,exynos5420-dw-mshc-smu",
68 .compatible = "samsung,exynos7-dw-mshc",
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H A Dsdhci-esdhc-imx.c1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
14 #include <linux/delay.h>
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
84 /* strobe dll register */
140 * open ended multi-blk IO. Otherwise the TC INT wouldn't
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/openbmc/u-boot/board/xes/xpedite517x/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
19 * There are four board-specific SDRAM timing parameters which must be
21 * 1.) CPO (Read Capture Delay)
22 * - TIMING_CFG_2 register
24 * chip-specific internal delays.
25 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
26 * - TIMING_CFG_2 register
30 * of 1/2 clock delay.
32 * - DDR_SDRAM_CLK_CNTL register
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/openbmc/u-boot/board/seco/mx6quq7/
H A Dmx6quq7-2g.cfg1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Refer doc/README.imximage for more details about how-to configure
22 #include "asm/arch/mx6-ddr.h"
30 /* DATA STROBE */
77 * Read Data Bit Delay
95 /* DQS gating, read delay, write delay calibration values */
101 /* Read calibration */
115 * in DDR3, 64-bit mode, only MMDC0 is init
129 /* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
132 /* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
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/openbmc/linux/drivers/parport/
H A Dieee1284_ops.c1 // SPDX-License-Identifier: GPL-2.0
2 /* IEEE-1284 operations for parport.
5 * they are used by the low-level drivers. If they have a special way
7 * the function pointers in port->ops); if not, they can just use these
20 #include <linux/delay.h>
31 * One-way data transfer functions. *
43 struct pardevice *dev = port->physport->cad; in parport_ieee1284_write_compat()
47 if (port->irq != PARPORT_IRQ_NONE) { in parport_ieee1284_write_compat()
52 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_write_compat()
56 unsigned long expire = jiffies + dev->timeout; in parport_ieee1284_write_compat()
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/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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/openbmc/linux/drivers/staging/media/atomisp/i2c/
H A Datomisp-lm3554.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved.
21 #include <linux/delay.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
84 struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); in lm3554_write()
89 dev_dbg(&client->dev, "Write Addr:%02X Val:%02X %s\n", addr, val, in lm3554_write()
98 struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); in lm3554_read()
103 dev_dbg(&client->dev, "Read Addr:%02X Val:%02X %s\n", addr, ret, in lm3554_read()
109 /* -----------------------------------------------------------------------------
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/openbmc/u-boot/drivers/misc/
H A Drockchip-efuse.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Written by Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
15 #include <linux/delay.h>
37 /* 0x14 efuse strobe finish control register */
52 * be read. in dump_efuses()
63 printf("%s: no misc-device found\n", __func__); in dump_efuses()
73 printf("efuse-contents:\n"); in dump_efuses()
91 (struct rockchip_efuse_regs *)plat->base; in rockchip_rk3399_efuse_read()
108 &efuse->ctrl); in rockchip_rk3399_efuse_read()
111 setbits_le32(&efuse->ctrl, in rockchip_rk3399_efuse_read()
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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/
H A DDimm.interface.yaml4 - name: MemoryDataWidth
8 - name: MemorySizeInKB
12 - name: MemoryDeviceLocator
16 - name: MemoryType
20 - name: MemoryTypeDetail
24 - name: MaxMemorySpeedInMhz
28 - name: MemoryAttributes
33 - name: MemoryConfiguredSpeedInMhz
37 - name: ECC
40 Error-Correcting Code.
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/openbmc/linux/Documentation/devicetree/bindings/leds/
H A Dcommon.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
16 blinking patterns, flash timeout, flash faults and external flash strobe mode.
25 led-sources:
30 $ref: /schemas/types.yaml#/definitions/uint32-array
35 from the header include/dt-bindings/leds/common.h. If there is no
42 the header include/dt-bindings/leds/common.h. If there is no matching
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