Lines Matching +full:read +full:- +full:strobe +full:- +full:delay

1 // SPDX-License-Identifier: GPL-2.0+
4  * Copyright 2007-2008 Freescale Semiconductor, Inc.
19  * There are four board-specific SDRAM timing parameters which must be
21  *   1.) CPO (Read Capture Delay)
22  *           - TIMING_CFG_2 register
24  *                   chip-specific internal delays.
25  *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
26  *           - TIMING_CFG_2 register
30  *                   of 1/2 clock delay.
32  *           - DDR_SDRAM_CLK_CNTL register
35  *           - TIMING_CFG_2 register
37  *           Usually only needed with heavy load/very high speed (>DDR2-800)
112 			popts->clk_adjust = bopts[i].clk_adjust;  in fsl_ddr_board_options()
113 			popts->cpo_override = bopts[i].cpo_override;  in fsl_ddr_board_options()
114 			popts->write_data_delay = bopts[i].write_data_delay;  in fsl_ddr_board_options()
119 	 * Factors to consider for half-strength driver enable:  in fsl_ddr_board_options()
120 	 *	- number of DIMMs installed  in fsl_ddr_board_options()
122 	popts->half_strength_driver_enable = 0;  in fsl_ddr_board_options()