Lines Matching +full:read +full:- +full:strobe +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
14 #include <linux/delay.h>
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
84 /* strobe dll register */
140 * open ended multi-blk IO. Otherwise the TC INT wouldn't
162 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
218 * struct esdhc_platform_data - platform data for esdhc on i.MX
231 unsigned int tuning_step; /* The delay cell steps in tuning procedure */
232 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */
233 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */
350 * the card init, but at this stage, mmc_host->card is not
366 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
367 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
368 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
369 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
370 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
371 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
372 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
373 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
374 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
375 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
376 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
377 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
378 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
379 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
380 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
387 return data->socdata == &esdhc_imx25_data; in is_imx25_esdhc()
392 return data->socdata == &esdhc_imx53_data; in is_imx53_esdhc()
397 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); in esdhc_is_usdhc()
402 void __iomem *base = host->ioaddr + (reg & ~0x3); in esdhc_clrset_le()
408 #define DRIVER_NAME "sdhci-esdhc-imx"
410 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
429 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); in esdhc_dump_debug_regs()
441 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, in esdhc_wait_for_card_clock_gate_off()
443 if (ret == -ETIMEDOUT) in esdhc_wait_for_card_clock_gate_off()
444 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); in esdhc_wait_for_card_clock_gate_off()
455 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL)); in usdhc_auto_tuning_mode_sel_and_en()
475 * DAT[1], and adjust the delay cell wrongly. in usdhc_auto_tuning_mode_sel_and_en()
480 if (imx_data->init_card_type == MMC_TYPE_SDIO) in usdhc_auto_tuning_mode_sel_and_en()
487 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in usdhc_auto_tuning_mode_sel_and_en()
489 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in usdhc_auto_tuning_mode_sel_and_en()
496 u32 val = readl(host->ioaddr + reg); in esdhc_readl_le()
502 /* move dat[0-3] bits */ in esdhc_readl_le()
509 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ in esdhc_readl_le()
510 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
528 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
529 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; in esdhc_readl_le()
542 if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) in esdhc_readl_le()
544 if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) in esdhc_readl_le()
566 if ((imx_data->multiblock_status == WAIT_FOR_INT) && in esdhc_readl_le()
569 writel(SDHCI_INT_RESPONSE, host->ioaddr + in esdhc_readl_le()
571 imx_data->multiblock_status = NO_CMD_PENDING; in esdhc_readl_le()
591 * and set D3CD bit will make eSDHC re-sample the card in esdhc_writel_le()
593 * re-sample it by the following steps. in esdhc_writel_le()
595 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
597 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
599 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
608 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writel_le()
612 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
614 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
616 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) in esdhc_writel_le()
621 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writel_le()
622 imx_data->multiblock_status = WAIT_FOR_INT; in esdhc_writel_le()
626 writel(val, host->ioaddr + reg); in esdhc_writel_le()
648 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_readw_le()
653 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in esdhc_readw_le()
654 val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
655 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) in esdhc_readw_le()
657 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_readw_le()
672 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
680 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_readw_le()
686 return readw(host->ioaddr + reg); in esdhc_readw_le()
697 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
702 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
707 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
712 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
713 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_writew_le()
714 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
715 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
730 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
731 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
735 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writew_le()
736 && (host->cmd->opcode == SD_IO_RW_EXTENDED) in esdhc_writew_le()
737 && (host->cmd->data->blocks > 1) in esdhc_writew_le()
738 && (host->cmd->data->flags & MMC_DATA_READ)) { in esdhc_writew_le()
740 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
742 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
747 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
754 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
760 m = readl(host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
783 writel(m, host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
789 imx_data->scratchpad = val; in esdhc_writew_le()
793 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) in esdhc_writew_le()
796 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && in esdhc_writew_le()
797 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) in esdhc_writew_le()
798 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; in esdhc_writew_le()
802 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
804 writel(val << 16 | imx_data->scratchpad, in esdhc_writew_le()
805 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
821 val = readl(host->ioaddr + reg); in esdhc_readb_le()
830 return readb(host->ioaddr + reg); in esdhc_readb_le()
870 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writeb_le()
895 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
897 host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
898 imx_data->is_ddr = 0; in esdhc_writeb_le()
916 return pltfm_host->clock; in esdhc_pltfm_get_max_clock()
923 return pltfm_host->clock / 256 / 16; in esdhc_pltfm_get_min_clock()
931 unsigned int host_clock = pltfm_host->clock; in esdhc_pltfm_set_clock()
932 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; in esdhc_pltfm_set_clock()
939 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
941 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
946 host->mmc->actual_clock = 0; in esdhc_pltfm_set_clock()
956 val = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
957 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
958 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
959 writel(val, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
969 if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) && in esdhc_pltfm_set_clock()
970 (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) { in esdhc_pltfm_set_clock()
973 max_clock = imx_data->is_ddr ? 45000000 : 150000000; in esdhc_pltfm_set_clock()
985 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); in esdhc_pltfm_set_clock()
986 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_pltfm_set_clock()
987 clock, host->mmc->actual_clock); in esdhc_pltfm_set_clock()
990 div--; in esdhc_pltfm_set_clock()
999 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, in esdhc_pltfm_set_clock()
1001 if (ret == -ETIMEDOUT) in esdhc_pltfm_set_clock()
1002 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); in esdhc_pltfm_set_clock()
1005 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
1007 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
1016 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_pltfm_get_ro()
1018 switch (boarddata->wp_type) { in esdhc_pltfm_get_ro()
1020 return mmc_gpio_get_ro(host->mmc); in esdhc_pltfm_get_ro()
1022 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & in esdhc_pltfm_get_ro()
1028 return -ENOSYS; in esdhc_pltfm_get_ro()
1060 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1062 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_reset_tuning()
1065 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1066 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_reset_tuning()
1067 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_reset_tuning()
1068 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1069 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1072 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1074 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, in esdhc_reset_tuning()
1076 if (ret == -ETIMEDOUT) in esdhc_reset_tuning()
1077 dev_warn(mmc_dev(host->mmc), in esdhc_reset_tuning()
1084 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1086 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1097 imx_data->init_card_type = card->type; in usdhc_init_card()
1109 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
1115 * correct delay cell. in usdhc_execute_tuning()
1120 if (!err && !host->tuning_err) in usdhc_execute_tuning()
1132 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ in esdhc_prepare_tuning()
1137 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, in esdhc_prepare_tuning()
1139 if (ret == -ETIMEDOUT) in esdhc_prepare_tuning()
1140 dev_warn(mmc_dev(host->mmc), in esdhc_prepare_tuning()
1143 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
1146 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
1147 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_prepare_tuning()
1148 dev_dbg(mmc_dev(host->mmc), in esdhc_prepare_tuning()
1149 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", in esdhc_prepare_tuning()
1150 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); in esdhc_prepare_tuning()
1157 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1159 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1166 /* find the mininum delay first which can pass tuning */ in esdhc_executing_tuning()
1170 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in esdhc_executing_tuning()
1175 /* find the maxinum delay which can not pass tuning */ in esdhc_executing_tuning()
1179 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in esdhc_executing_tuning()
1180 max -= ESDHC_TUNE_CTRL_STEP; in esdhc_executing_tuning()
1186 /* use average delay to get the best timing */ in esdhc_executing_tuning()
1189 ret = mmc_send_tuning(host->mmc, opcode, NULL); in esdhc_executing_tuning()
1192 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", in esdhc_executing_tuning()
1203 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1204 if (ios->enhanced_strobe) in esdhc_hs400_enhanced_strobe()
1208 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1218 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); in esdhc_change_pinstate()
1220 if (IS_ERR(imx_data->pinctrl) || in esdhc_change_pinstate()
1221 IS_ERR(imx_data->pins_100mhz) || in esdhc_change_pinstate()
1222 IS_ERR(imx_data->pins_200mhz)) in esdhc_change_pinstate()
1223 return -EINVAL; in esdhc_change_pinstate()
1228 pinctrl = imx_data->pins_100mhz; in esdhc_change_pinstate()
1233 pinctrl = imx_data->pins_200mhz; in esdhc_change_pinstate()
1237 return pinctrl_select_default_state(mmc_dev(host->mmc)); in esdhc_change_pinstate()
1240 return pinctrl_select_state(imx_data->pinctrl, pinctrl); in esdhc_change_pinstate()
1248 * edge of data_strobe line. Due to the time delay between CLK line and
1249 * data_strobe line, if the delay time is larger than one clock cycle,
1250 * then CLK and data_strobe line will be misaligned, read error shows up.
1260 /* disable clock before enabling strobe dll */ in esdhc_set_strobe_dll()
1261 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & in esdhc_set_strobe_dll()
1263 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_set_strobe_dll()
1266 /* force a reset on strobe dll */ in esdhc_set_strobe_dll()
1268 host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1269 /* clear the reset bit on strobe dll before any setting */ in esdhc_set_strobe_dll()
1270 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1273 * enable strobe dll ctrl and adjust the delay target in esdhc_set_strobe_dll()
1274 * for the uSDHC loopback read clock in esdhc_set_strobe_dll()
1276 if (imx_data->boarddata.strobe_dll_delay_target) in esdhc_set_strobe_dll()
1277 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; in esdhc_set_strobe_dll()
1283 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1286 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, in esdhc_set_strobe_dll()
1288 if (ret == -ETIMEDOUT) in esdhc_set_strobe_dll()
1289 dev_warn(mmc_dev(host->mmc), in esdhc_set_strobe_dll()
1290 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); in esdhc_set_strobe_dll()
1298 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_set_uhs_signaling()
1301 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1303 imx_data->is_ddr = 0; in esdhc_set_uhs_signaling()
1312 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1317 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1318 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1319 if (boarddata->delay_line) { in esdhc_set_uhs_signaling()
1321 v = boarddata->delay_line << in esdhc_set_uhs_signaling()
1326 writel(v, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_set_uhs_signaling()
1331 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1332 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1333 /* update clock after enable DDR for strobe DLL lock */ in esdhc_set_uhs_signaling()
1334 host->ops->set_clock(host, host->clock); in esdhc_set_uhs_signaling()
1350 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
1351 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
1382 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in esdhc_cqhci_irq()
1419 struct cqhci_host *cq_host = host->mmc->cqe_private; in sdhci_esdhc_imx_hwinit()
1427 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); in sdhci_esdhc_imx_hwinit()
1440 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) in sdhci_esdhc_imx_hwinit()
1442 host->ioaddr + SDHCI_HOST_CONTROL); in sdhci_esdhc_imx_hwinit()
1448 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) { in sdhci_esdhc_imx_hwinit()
1449 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), in sdhci_esdhc_imx_hwinit()
1450 host->ioaddr + 0x6c); in sdhci_esdhc_imx_hwinit()
1453 /* disable DLL_CTRL delay line settings */ in sdhci_esdhc_imx_hwinit()
1454 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); in sdhci_esdhc_imx_hwinit()
1465 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_hwinit()
1466 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1468 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1470 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; in sdhci_esdhc_imx_hwinit()
1473 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in sdhci_esdhc_imx_hwinit()
1474 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1482 if (imx_data->boarddata.tuning_start_tap) in sdhci_esdhc_imx_hwinit()
1483 tmp |= imx_data->boarddata.tuning_start_tap; in sdhci_esdhc_imx_hwinit()
1487 if (imx_data->boarddata.tuning_step) { in sdhci_esdhc_imx_hwinit()
1488 tmp |= imx_data->boarddata.tuning_step in sdhci_esdhc_imx_hwinit()
1496 * add some delay after every tuning command, because in sdhci_esdhc_imx_hwinit()
1500 * the buffer read ready interrupt immediately. If usdhc send in sdhci_esdhc_imx_hwinit()
1506 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1507 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in sdhci_esdhc_imx_hwinit()
1513 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1515 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1538 struct cqhci_host *cq_host = mmc->cqe_private; in esdhc_cqe_enable()
1544 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be in esdhc_cqe_enable()
1551 if (count-- == 0) { in esdhc_cqe_enable()
1552 dev_warn(mmc_dev(host->mmc), in esdhc_cqe_enable()
1553 "CQE may get stuck because the Buffer Read Enable bit is set\n"); in esdhc_cqe_enable()
1565 if (host->flags & SDHCI_REQ_USE_DMA) in esdhc_cqe_enable()
1567 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) in esdhc_cqe_enable()
1579 dev_err(mmc_dev(host->mmc), in esdhc_cqe_enable()
1602 struct device_node *np = pdev->dev.of_node; in sdhci_esdhc_imx_probe_dt()
1603 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_dt()
1606 if (of_property_read_bool(np, "fsl,wp-controller")) in sdhci_esdhc_imx_probe_dt()
1607 boarddata->wp_type = ESDHC_WP_CONTROLLER; in sdhci_esdhc_imx_probe_dt()
1614 if (of_property_read_bool(np, "wp-gpios")) in sdhci_esdhc_imx_probe_dt()
1615 boarddata->wp_type = ESDHC_WP_GPIO; in sdhci_esdhc_imx_probe_dt()
1617 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); in sdhci_esdhc_imx_probe_dt()
1618 of_property_read_u32(np, "fsl,tuning-start-tap", in sdhci_esdhc_imx_probe_dt()
1619 &boarddata->tuning_start_tap); in sdhci_esdhc_imx_probe_dt()
1621 of_property_read_u32(np, "fsl,strobe-dll-delay-target", in sdhci_esdhc_imx_probe_dt()
1622 &boarddata->strobe_dll_delay_target); in sdhci_esdhc_imx_probe_dt()
1623 if (of_property_read_bool(np, "no-1-8-v")) in sdhci_esdhc_imx_probe_dt()
1624 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; in sdhci_esdhc_imx_probe_dt()
1626 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) in sdhci_esdhc_imx_probe_dt()
1627 boarddata->delay_line = 0; in sdhci_esdhc_imx_probe_dt()
1629 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); in sdhci_esdhc_imx_probe_dt()
1631 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { in sdhci_esdhc_imx_probe_dt()
1632 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1634 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1639 ret = mmc_of_parse(host->mmc); in sdhci_esdhc_imx_probe_dt()
1644 if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA)) in sdhci_esdhc_imx_probe_dt()
1645 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); in sdhci_esdhc_imx_probe_dt()
1647 if (mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_esdhc_imx_probe_dt()
1648 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_dt()
1670 imx_data->socdata = device_get_match_data(&pdev->dev); in sdhci_esdhc_imx_probe()
1672 host->quirks |= imx_data->socdata->quirks; in sdhci_esdhc_imx_probe()
1673 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1674 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_imx_probe()
1676 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdhci_esdhc_imx_probe()
1677 if (IS_ERR(imx_data->clk_ipg)) { in sdhci_esdhc_imx_probe()
1678 err = PTR_ERR(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1682 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdhci_esdhc_imx_probe()
1683 if (IS_ERR(imx_data->clk_ahb)) { in sdhci_esdhc_imx_probe()
1684 err = PTR_ERR(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1688 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); in sdhci_esdhc_imx_probe()
1689 if (IS_ERR(imx_data->clk_per)) { in sdhci_esdhc_imx_probe()
1690 err = PTR_ERR(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1694 pltfm_host->clk = imx_data->clk_per; in sdhci_esdhc_imx_probe()
1695 pltfm_host->clock = clk_get_rate(pltfm_host->clk); in sdhci_esdhc_imx_probe()
1696 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1699 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1702 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1706 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); in sdhci_esdhc_imx_probe()
1707 if (IS_ERR(imx_data->pinctrl)) in sdhci_esdhc_imx_probe()
1708 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); in sdhci_esdhc_imx_probe()
1711 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_esdhc_imx_probe()
1712 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; in sdhci_esdhc_imx_probe()
1715 host->mmc->caps |= MMC_CAP_CD_WAKE; in sdhci_esdhc_imx_probe()
1717 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) in sdhci_esdhc_imx_probe()
1718 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; in sdhci_esdhc_imx_probe()
1721 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); in sdhci_esdhc_imx_probe()
1722 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in sdhci_esdhc_imx_probe()
1723 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in sdhci_esdhc_imx_probe()
1729 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; in sdhci_esdhc_imx_probe()
1735 host->mmc_host_ops.init_card = usdhc_init_card; in sdhci_esdhc_imx_probe()
1738 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in sdhci_esdhc_imx_probe()
1742 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) in sdhci_esdhc_imx_probe()
1743 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; in sdhci_esdhc_imx_probe()
1745 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in sdhci_esdhc_imx_probe()
1746 host->mmc->caps2 |= MMC_CAP2_HS400; in sdhci_esdhc_imx_probe()
1748 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) in sdhci_esdhc_imx_probe()
1749 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; in sdhci_esdhc_imx_probe()
1751 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { in sdhci_esdhc_imx_probe()
1752 host->mmc->caps2 |= MMC_CAP2_HS400_ES; in sdhci_esdhc_imx_probe()
1753 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_esdhc_imx_probe()
1757 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_probe()
1758 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_esdhc_imx_probe()
1759 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in sdhci_esdhc_imx_probe()
1761 err = -ENOMEM; in sdhci_esdhc_imx_probe()
1765 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; in sdhci_esdhc_imx_probe()
1766 cq_host->ops = &esdhc_cqhci_ops; in sdhci_esdhc_imx_probe()
1768 err = cqhci_init(cq_host, host->mmc, false); in sdhci_esdhc_imx_probe()
1787 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) && in sdhci_esdhc_imx_probe()
1788 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)) in sdhci_esdhc_imx_probe()
1789 device_set_wakeup_capable(&pdev->dev, true); in sdhci_esdhc_imx_probe()
1791 pm_runtime_set_active(&pdev->dev); in sdhci_esdhc_imx_probe()
1792 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sdhci_esdhc_imx_probe()
1793 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_esdhc_imx_probe()
1794 pm_suspend_ignore_children(&pdev->dev, 1); in sdhci_esdhc_imx_probe()
1795 pm_runtime_enable(&pdev->dev); in sdhci_esdhc_imx_probe()
1800 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1802 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1804 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1806 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1807 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_probe()
1819 pm_runtime_get_sync(&pdev->dev); in sdhci_esdhc_imx_remove()
1820 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); in sdhci_esdhc_imx_remove()
1821 pm_runtime_disable(&pdev->dev); in sdhci_esdhc_imx_remove()
1822 pm_runtime_put_noidle(&pdev->dev); in sdhci_esdhc_imx_remove()
1826 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_remove()
1827 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_remove()
1828 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_remove()
1830 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_remove()
1831 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_remove()
1844 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_suspend()
1845 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_suspend()
1850 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && in sdhci_esdhc_suspend()
1851 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { in sdhci_esdhc_suspend()
1852 mmc_retune_timer_stop(host->mmc); in sdhci_esdhc_suspend()
1853 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1856 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_suspend()
1857 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1867 ret = mmc_gpio_set_cd_wake(host->mmc, true); in sdhci_esdhc_suspend()
1881 /* re-initialize hw state in case it's lost in low power mode */ in sdhci_esdhc_resume()
1888 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_resume()
1889 ret = cqhci_resume(host->mmc); in sdhci_esdhc_resume()
1892 ret = mmc_gpio_set_cd_wake(host->mmc, false); in sdhci_esdhc_resume()
1906 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_runtime_suspend()
1907 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_runtime_suspend()
1916 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_runtime_suspend()
1917 mmc_retune_needed(host->mmc); in sdhci_esdhc_runtime_suspend()
1919 imx_data->actual_clock = host->mmc->actual_clock; in sdhci_esdhc_runtime_suspend()
1921 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_suspend()
1922 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_suspend()
1923 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_suspend()
1925 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_suspend()
1926 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_suspend()
1938 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1939 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_runtime_resume()
1941 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) in sdhci_esdhc_runtime_resume()
1942 clk_set_rate(imx_data->clk_per, pltfm_host->clock); in sdhci_esdhc_runtime_resume()
1944 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1948 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1952 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1956 esdhc_pltfm_set_clock(host, imx_data->actual_clock); in sdhci_esdhc_runtime_resume()
1962 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_runtime_resume()
1963 err = cqhci_resume(host->mmc); in sdhci_esdhc_runtime_resume()
1968 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1970 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1972 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1974 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1975 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_resume()
1988 .name = "sdhci-esdhc-imx",