xes/xpedite537x/ddr.c

1 // SPDX-License-Identifier: GPL-2.0+
20  * There are four board-specific SDRAM timing parameters which must be
22  *   1.) CPO (Read Capture Delay)
23  *           - TIMING_CFG_2 register
25  *                   chip-specific internal delays.
26  *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
27  *           - TIMING_CFG_2 register
31  *                   of 1/2 clock delay.
33  *           - DDR_SDRAM_CLK_CNTL register
36  *           - TIMING_CFG_2 register
38  *           Usually only needed with heavy load/very high speed (>DDR2-800)
40  *     ====== XPedite5370 DDR2-600 read delay calculations ======
43  *     contains the chip-specific delays for 8548E, 8572, etc.
46  *     Minimum chip delay (Ch 0): 1.372ns
47  *     Maximum chip delay (Ch 0): 2.914ns
48  *     Minimum chip delay (Ch 1): 1.220ns
49  *     Maximum chip delay (Ch 1): 2.595ns
53  *     Minimum delay calc (Ch 0):
54  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
55  *     2.3" * 180 - 400ps     + 1.9" * 180         + 2080ps     + 1372ps
59  *     Maximum delay calc (Ch 0):
60  *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
65  *     Minimum delay calc (Ch 1):
66  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
67  *     1.46" * 180- 400ps     + 0.7" * 180         + 2080ps     + 1220ps
71  *     Maximum delay calc (Ch 1):
72  *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
77  *     Ch.0: 3.808ns to 6.240ns additional delay needed  (pick 5ns as target)
79  *     Ch.1: 3.288ns to 5.536ns additional delay needed  (pick 4.4ns as target)
83  *     ====== XPedite5370 DDR2-800 read delay calculations ======
86  *     contains the chip-specific delays for 8548E, 8572, etc.
89  *     Minimum chip delay (Ch 0): 1.372ns
90  *     Maximum chip delay (Ch 0): 2.914ns
91  *     Minimum chip delay (Ch 1): 1.220ns
92  *     Maximum chip delay (Ch 1): 2.595ns
96  *     Minimum delay calc (Ch 0):
97  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
98  *     2.3" * 180 - 350ps     + 1.9" * 180         + 1563ps     + 1372ps
102  *     Maximum delay calc (Ch 0):
103  *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
108  *     Minimum delay calc (Ch 1):
109  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
110  *     1.46" * 180- 350ps     + 0.7" * 180         + 1563ps     + 1220ps
114  *     Maximum delay calc (Ch 1):
115  *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
120  *     Ch.0: 3.341ns to 5.673ns additional delay needed  (pick 4.5ns as target)
122  *     Ch.1: 2.822ns to 4.968ns additional delay needed  (pick 3.9ns as target)
143  *      period at DDR2-600 or DDR2-800, so no additional delay is needed over
145  *      exactly WL (CAS latency minus one cycle) after the CAS strobe.
146  *      See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
147  *      terminology corresponds to exactly one clock period delay after
148  *      the CAS strobe. (due to the fact that the "delay" is referenced
150  *      which the CAS strobe is latched on.
222 			popts->clk_adjust = bopts[i].clk_adjust;  in fsl_ddr_board_options()
223 			popts->cpo_override = bopts[i].cpo_override;  in fsl_ddr_board_options()
224 			popts->write_data_delay = bopts[i].write_data_delay;  in fsl_ddr_board_options()
229 	 * Factors to consider for half-strength driver enable:  in fsl_ddr_board_options()
230 	 *	- number of DIMMs installed  in fsl_ddr_board_options()
232 	popts->half_strength_driver_enable = 0;  in fsl_ddr_board_options()