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/openbmc/u-boot/arch/x86/cpu/quark/
H A Dmrc_util.h83 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
85 void set_rcvn(uint8_t channel, uint8_t rank,
87 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
88 void set_rdqs(uint8_t channel, uint8_t rank,
90 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
91 void set_wdqs(uint8_t channel, uint8_t rank,
93 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
94 void set_wdq(uint8_t channel, uint8_t rank,
96 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
99 void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
[all …]
H A Dmrc_util.c126 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane) in training_message() argument
129 DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane); in training_message()
135 * (currently doesn't comprehend rank)
137 void set_rcvn(uint8_t channel, uint8_t rank, in set_rcvn() argument
147 channel, rank, byte_lane, pi_count); in set_rcvn()
200 training_message(channel, rank, byte_lane); in set_rcvn()
209 * channel, rank, byte_lane as an absolute PI count.
211 * (currently doesn't comprehend rank)
213 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_rcvn() argument
259 * (currently doesn't comprehend rank)
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H A Dhte.c79 * @addr: memory adress being tested (must hit specific channel/rank)
131 * @addr: memory adress being tested (must hit specific channel/rank)
201 * @return: errors register showing HTE failures. Also prints out which rank
202 * failed the HTE test if failure occurs. For rank detection to work,
290 * @addr: memory adress being tested (must hit specific channel/rank)
320 * @addr: memory adress being tested (must hit specific channel/rank)
361 * @addr: memory adress being tested (must hit specific channel/rank)
H A Dsmc.c210 * Training performed in address mode 0, rank population has limited in prog_decode_before_jedec()
211 * impact, however simulator complains if enabled non-existing rank. in prog_decode_before_jedec()
256 uint8_t rk; /* rank counter */ in ddrphy_init()
1150 uint8_t twr, wl, rank; in perform_jedec_init() local
1178 * then send NOP to each rank (#4550197) in perform_jedec_init()
1190 for (rank = 0; rank < NUM_RANKS; rank++) { in perform_jedec_init()
1191 /* Skip to next populated rank */ in perform_jedec_init()
1192 if ((mrc_params->rank_enables & (1 << rank)) == 0) in perform_jedec_init()
1195 dram_init_command(DCMD_NOP(rank)); in perform_jedec_init()
1299 for (rank = 0; rank < NUM_RANKS; rank++) { in perform_jedec_init()
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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Control/
H A DPowerSupplyRedundancy.interface.yaml22 The rank order for each PSU, 0 means will not go into cold standby
28 Specific, and rotation is enabled, BMC will change PSU rank order
52 1 to the rank order in each PSU and change the last rank order
53 to the first rank order.
58 will update the rank order to PSU.
/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dddrphy-training.c21 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
29 /* Specify the rank that should be write leveled */ in ddrphy_prepare_training()
31 tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) & in ddrphy_prepare_training()
38 /* Specify the rank used during data bit deskew and eye centering */ in ddrphy_prepare_training()
40 tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK; in ddrphy_prepare_training()
43 /* Specify the rank enabled for data-training */ in ddrphy_prepare_training()
45 tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK; in ddrphy_prepare_training()
H A Dcmd_ddrphy.c142 int rank; in __wld_dump() local
146 for (rank = 0; rank < 4; rank++) { in __wld_dump()
147 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ in __wld_dump()
148 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ in __wld_dump()
165 int rank; in __dqsgd_dump() local
169 for (rank = 0; rank < 4; rank++) { in __dqsgd_dump()
170 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ in __dqsgd_dump()
171 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ in __dqsgd_dump()
H A Dcmd_ddrmphy.c168 int rank; in __wld_dump() local
172 for (rank = 0; rank < 4; rank++) { in __wld_dump()
173 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ in __wld_dump()
174 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ in __wld_dump()
191 int rank; in __dqsgd_dump() local
195 for (rank = 0; rank < 4; rank++) { in __dqsgd_dump()
196 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ in __dqsgd_dump()
197 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ in __dqsgd_dump()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a33.c26 u8 rank; member
42 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
48 u8 orig_rank = para->rank; in auto_detect_dram_size()
55 para->rank = 1; in auto_detect_dram_size()
72 para->rank = orig_rank; in auto_detect_dram_size()
150 /* Set two rank timing and exit self-refresh timing */ in auto_set_timing_para()
184 if (para->rank == 2) in mctl_data_train_cfg()
230 /* Auto detect dram config, set 2 rank and 16bit bus-width */ in mctl_channel_init()
232 para->rank = 2; in mctl_channel_init()
258 /* DRAM has only one rank */ in mctl_channel_init()
[all …]
H A Ddram_sun8i_a83t.c24 u8 rank; member
41 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
47 u8 orig_rank = para->rank; in auto_detect_dram_size()
54 para->rank = 1; in auto_detect_dram_size()
71 para->rank = orig_rank; in auto_detect_dram_size()
182 /* Set two rank timing and exit self-refresh timing */ in auto_set_timing_para()
216 if (para->rank == 2) in mctl_data_train_cfg()
313 /* Auto detect dram config, set 2 rank and 16bit bus-width */ in mctl_channel_init()
315 para->rank = 2; in mctl_channel_init()
350 /* DRAM has only one rank */ in mctl_channel_init()
[all …]
H A Ddram_sun6i.c24 u8 rank; member
91 static bool mctl_rank_detect(u32 *gsr0, int rank) in mctl_rank_detect() argument
93 const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; in mctl_rank_detect()
94 const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; in mctl_rank_detect()
164 /* rank detect */ in mctl_channel_init()
166 para->rank = 1; in mctl_channel_init()
171 * channel detect, check channel 1 dx0 and dx1 have rank 0, if not in mctl_channel_init()
180 /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */ in mctl_channel_init()
274 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); in mctl_com_init()
339 .rank = 2, in sunxi_dram_init()
[all …]
/openbmc/u-boot/doc/
H A DREADME.fsl-ddr28 | | Rank Interleaving |
49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
50 from each controller. {CS2+CS3} on each controller are only rank
157 For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
167 | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
172 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+--…
176 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+--…
180 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+--…
184 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+--…
187 | Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
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/openbmc/u-boot/arch/arm/mach-rockchip/
H A Dsdram_common.c16 u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
27 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & in rockchip_sdram_size()
42 if (rank > 1) in rockchip_sdram_size()
47 debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", in rockchip_sdram_size()
48 rank, col, bk, cs0_row, bw, row_3_4); in rockchip_sdram_size()
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c309 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
312 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
319 u32 rank, u32 cmd, u32 ma, u32 op) in send_command_op() argument
321 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
419 u32 rank; in data_training() local
430 rank = sdram_params->ch[channel].rank | 1; in data_training()
444 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
445 != rank) in data_training()
447 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
448 != rank) in data_training()
[all …]
H A Dsdram_rk3288.c367 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
370 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
377 u32 rank, u32 cmd, u32 ma, u32 op) in send_command_op() argument
379 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
477 u32 rank; in data_training() local
488 rank = sdram_params->ch[channel].rank | 1; in data_training()
502 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
503 != rank) in data_training()
505 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
506 != rank) in data_training()
[all …]
H A Dsdram_rk3399.c130 cs_map = (sdram_ch->rank > 1) ? 3 : 1; in set_memory_map()
151 if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) in set_memory_map()
477 /* rank count need to set for init */ in pctl_cfg()
565 u32 rank) in select_per_cs_training_index() argument
575 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); in select_per_cs_training_index()
576 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); in select_per_cs_training_index()
577 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); in select_per_cs_training_index()
578 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); in select_per_cs_training_index()
618 u32 rank = sdram_params->ch[channel].rank; in data_training_ca() local
620 for (i = 0; i < rank; i++) { in data_training_ca()
[all …]
/openbmc/u-boot/board/freescale/ls2080a/
H A Dddr.h27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
39 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
50 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
63 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
/openbmc/u-boot/board/freescale/ls2080aqds/
H A Dddr.h27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
41 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
54 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
68 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
/openbmc/openbmc/meta-ampere/meta-common/recipes-ampere/host/ac01-boot-progress/
H A Ddimm_train_fail_log.sh92 rank=$(((data & 0x1C) >> 2))
112 #smg=$("DDR training: MCU rank $rank: $fType: $redfisMsg")
115 $redfisComp "Slot $channel MCU rank $rank: $fType: $redfisMsg"
/openbmc/u-boot/board/freescale/ls2080ardb/
H A Dddr.h27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
41 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
54 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
/openbmc/intel-ipmi-oem/src/
H A Dipmi_to_redfish_hooks.cpp109 messageArgs.push_back("Rank Sparing"); in biosMessageHook()
227 messageArgs.push_back("Rank Sparing"); in biosMessageHook()
245 messageArgs.push_back("Rank Sparing"); in biosMessageHook()
350 // rank = eventData2 bits [1:0] in biosSMIMessageHook()
351 int rank = selData.eventData2 & 0x03; in biosSMIMessageHook() local
367 messageArgs.push_back(std::to_string(rank)); in biosSMIMessageHook()
397 // rank = eventData2 bits [3:0] in biosSMIMessageHook()
398 int rank = selData.eventData2 & 0x0F; in biosSMIMessageHook() local
411 messageArgs.push_back(std::to_string(rank)); in biosSMIMessageHook()
624 // rank = eventData2 bits [1:0] in biosSMIMessageHook()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sunxi_dw.h19 u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */
70 * parameters for rank 1. Bits [11:0] have the same meaning as the bits in
71 * MCTL_CR, but they apply to rank 1 only. This implies we can have
72 * different chips for rank 1 than rank 0.
74 * As address line A15 and CS1 chip select for rank 1 are muxed on the same
75 * pin, if single rank is used, A15 must be muxed in.
/openbmc/openbmc/poky/scripts/
H A Doe-pkgdata-browser45 rank = 0
47 rank = int((math.log10(nbytes)) / 3)
48 rank = min(rank, len(suffixes) - 1)
49 human = nbytes / (1000.0 ** rank)
51 return '%s %s' % (f, suffixes[rank])
/openbmc/u-boot/board/freescale/ls1046ardb/
H A Dddr.h29 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
46 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
/openbmc/qemu/hw/mem/
H A Dcxl_type3_stubs.c21 bool has_rank, uint8_t rank, in qmp_cxl_inject_general_media_event() argument
30 bool has_rank, uint8_t rank, in qmp_cxl_inject_dram_event() argument

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