xref: /openbmc/u-boot/doc/README.fsl-ddr (revision 55926ddd189546742a4496e6690c2b62958cd7cd)
1a4c66509SYork SunTable of interleaving 2-4 controllers
2a4c66509SYork Sun=====================================
3a4c66509SYork Sun  +--------------+-----------------------------------------------------------+
4a4c66509SYork Sun  |Configuration |                    Memory Controller                      |
5a4c66509SYork Sun  |              |       1              2              3             4       |
6a4c66509SYork Sun  |--------------+--------------+--------------+-----------------------------+
7a4c66509SYork Sun  | Two memory   | Not Intlv'ed | Not Intlv'ed |                             |
8a4c66509SYork Sun  | complexes    +--------------+--------------+                             |
9a4c66509SYork Sun  |              |      2-way Intlv'ed         |                             |
10a4c66509SYork Sun  |--------------+--------------+--------------+--------------+              |
11a4c66509SYork Sun  |              | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |              |
12a4c66509SYork Sun  | Three memory +--------------+--------------+--------------+              |
13a4c66509SYork Sun  | complexes    |         2-way Intlv'ed      | Not Intlv'ed |              |
14a4c66509SYork Sun  |              +-----------------------------+--------------+              |
15a4c66509SYork Sun  |              |                  3-way Intlv'ed            |              |
16a4c66509SYork Sun  +--------------+--------------+--------------+--------------+--------------+
17a4c66509SYork Sun  |              | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
18a4c66509SYork Sun  | Four memory  +--------------+--------------+--------------+--------------+
19a4c66509SYork Sun  | complexes    |       2-way Intlv'ed        |       2-way Intlv'ed        |
20a4c66509SYork Sun  |              +-----------------------------+-----------------------------+
21a4c66509SYork Sun  |              |                      4-way Intlv'ed                       |
22a4c66509SYork Sun  +--------------+-----------------------------------------------------------+
23c9ffd839SHaiying Wang
24a4c66509SYork Sun
25a4c66509SYork SunTable of 2-way interleaving modes supported in cpu/8xxx/ddr/
26c9ffd839SHaiying Wang======================================================
27c9ffd839SHaiying Wang  +-------------+---------------------------------------------------------+
28c9ffd839SHaiying Wang  |		|		    Rank Interleaving			  |
29c9ffd839SHaiying Wang  |		+--------+-----------+-----------+------------+-----------+
30c9ffd839SHaiying Wang  |Memory	|	 |	     |		 |    2x2     |    4x1	  |
31c9ffd839SHaiying Wang  |Controller	|  None  | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32c9ffd839SHaiying Wang  |Interleaving |	 | {CS0+CS1} | {CS2+CS3} | {CS2+CS3}  |  CS2+CS3} |
33c9ffd839SHaiying Wang  +-------------+--------+-----------+-----------+------------+-----------+
34c9ffd839SHaiying Wang  |None		|  Yes	 | Yes	     | Yes	 | Yes	      | Yes	  |
35c9ffd839SHaiying Wang  +-------------+--------+-----------+-----------+------------+-----------+
36c9ffd839SHaiying Wang  |Cacheline	|  Yes	 | Yes	     | No	 | No, Only(*)| Yes	  |
37c9ffd839SHaiying Wang  |		|CS0 Only|	     |		 | {CS0+CS1}  |		  |
38c9ffd839SHaiying Wang  +-------------+--------+-----------+-----------+------------+-----------+
39c9ffd839SHaiying Wang  |Page		|  Yes	 | Yes	     | No	 | No, Only(*)| Yes	  |
40c9ffd839SHaiying Wang  |		|CS0 Only|	     |		 | {CS0+CS1}  |		  |
41c9ffd839SHaiying Wang  +-------------+--------+-----------+-----------+------------+-----------+
42c9ffd839SHaiying Wang  |Bank		|  Yes	 | Yes	     | No	 | No, Only(*)| Yes	  |
43c9ffd839SHaiying Wang  |		|CS0 Only|	     |		 | {CS0+CS1}  |		  |
44c9ffd839SHaiying Wang  +-------------+--------+-----------+-----------+------------+-----------+
45c9ffd839SHaiying Wang  |Superbank	|  No	 | Yes	     | No	 | No, Only(*)| Yes	  |
46c9ffd839SHaiying Wang  |		|	 |	     |		 | {CS0+CS1}  |		  |
47c9ffd839SHaiying Wang  +-------------+--------+-----------+-----------+------------+-----------+
48c9ffd839SHaiying Wang (*) Although the hardware can be configured with memory controller
49c9ffd839SHaiying Wang interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
50c9ffd839SHaiying Wang from each controller. {CS2+CS3} on each controller are only rank
51c9ffd839SHaiying Wang interleaved on that controller.
52c9ffd839SHaiying Wang
53076bff8fSyork For memory controller interleaving, identical DIMMs are suggested. Software
54076bff8fSyork doesn't check the size or organization of interleaved DIMMs.
55076bff8fSyork
56c9ffd839SHaiying WangThe ways to configure the ddr interleaving mode
57c9ffd839SHaiying Wang==============================================
58c9ffd839SHaiying Wang1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
59c9ffd839SHaiying Wang   under "CONFIG_EXTRA_ENV_SETTINGS", like:
60c9ffd839SHaiying Wang	#define CONFIG_EXTRA_ENV_SETTINGS				\
6179e4e648SKumar Gala	 "hwconfig=fsl_ddr:ctlr_intlv=bank"			\
62c9ffd839SHaiying Wang	 ......
63c9ffd839SHaiying Wang
64a187559eSBin Meng2. Run U-Boot "setenv" command to configure the memory interleaving mode.
65c9ffd839SHaiying Wang   Either numerical or string value is accepted.
66c9ffd839SHaiying Wang
67c9ffd839SHaiying Wang  # disable memory controller interleaving
6879e4e648SKumar Gala  setenv hwconfig "fsl_ddr:ctlr_intlv=null"
69c9ffd839SHaiying Wang
70c9ffd839SHaiying Wang  # cacheline interleaving
7179e4e648SKumar Gala  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
72c9ffd839SHaiying Wang
73c9ffd839SHaiying Wang  # page interleaving
7479e4e648SKumar Gala  setenv hwconfig "fsl_ddr:ctlr_intlv=page"
75c9ffd839SHaiying Wang
76c9ffd839SHaiying Wang  # bank interleaving
7779e4e648SKumar Gala  setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
78c9ffd839SHaiying Wang
79c9ffd839SHaiying Wang  # superbank
8079e4e648SKumar Gala  setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
81c9ffd839SHaiying Wang
82a4c66509SYork Sun  # 1KB 3-way interleaving
83a4c66509SYork Sun  setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
84a4c66509SYork Sun
85a4c66509SYork Sun  # 4KB 3-way interleaving
86a4c66509SYork Sun  setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
87a4c66509SYork Sun
88a4c66509SYork Sun  # 8KB 3-way interleaving
89a4c66509SYork Sun  setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
90a4c66509SYork Sun
91c9ffd839SHaiying Wang  # disable bank (chip-select) interleaving
9279e4e648SKumar Gala  setenv hwconfig "fsl_ddr:bank_intlv=null"
93c9ffd839SHaiying Wang
94c9ffd839SHaiying Wang  # bank(chip-select) interleaving cs0+cs1
9579e4e648SKumar Gala  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
96c9ffd839SHaiying Wang
97c9ffd839SHaiying Wang  # bank(chip-select) interleaving cs2+cs3
9879e4e648SKumar Gala  setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
99c9ffd839SHaiying Wang
100c9ffd839SHaiying Wang  # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
10179e4e648SKumar Gala  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
102c9ffd839SHaiying Wang
103c9ffd839SHaiying Wang  # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
10479e4e648SKumar Gala  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
10579e4e648SKumar Gala
10689b78095SYork Sun  # bank(chip-select) interleaving (auto)
10789b78095SYork Sun  setenv hwconfig "fsl_ddr:bank_intlv=auto"
10889b78095SYork Sun  This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
10989b78095SYork Sun  on DIMMs.
11089b78095SYork Sun
1117fd101c9SyorkMemory controller address hashing
1127fd101c9Syork==================================
1137fd101c9SyorkIf the DDR controller supports address hashing, it can be enabled by hwconfig.
1147fd101c9Syork
1157fd101c9SyorkSyntax is:
1167fd101c9Syorkhwconfig=fsl_ddr:addr_hash=true
1177fd101c9Syork
11847df8f03SYork SunMemory controller ECC on/off
11947df8f03SYork Sun============================
12047df8f03SYork SunIf ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
12147df8f03SYork SunECC can be turned on/off by hwconfig.
12247df8f03SYork Sun
12347df8f03SYork SunSyntax is
12447df8f03SYork Sunhwconfig=fsl_ddr:ecc=off
125ebbe11ddSYork Sun
126*eb118807SShengzhou Liu
127*eb118807SShengzhou LiuMemory address parity on/off
128*eb118807SShengzhou Liu============================
129*eb118807SShengzhou Liuaddress parity can be turned on/off by hwconfig.
130*eb118807SShengzhou LiuSyntax is:
131*eb118807SShengzhou Liuhwconfig=fsl_ddr:parity=on
132*eb118807SShengzhou Liu
133*eb118807SShengzhou Liu
134ebbe11ddSYork SunMemory testing options for mpc85xx
135ebbe11ddSYork Sun==================================
136a187559eSBin Meng1. Memory test can be done once U-Boot prompt comes up using mtest, or
137ebbe11ddSYork Sun2. Memory test can be done with Power-On-Self-Test function, activated at
138ebbe11ddSYork Sun   compile time.
139ebbe11ddSYork Sun
140ebbe11ddSYork Sun   In order to enable the POST memory test, CONFIG_POST needs to be
141ebbe11ddSYork Sun   defined in board configuraiton header file. By default, POST memory test
142ebbe11ddSYork Sun   performs a fast test. A slow test can be enabled by changing the flag at
143ebbe11ddSYork Sun   compiling time. To test memory bigger than 2GB, 36BIT support is needed.
144ebbe11ddSYork Sun   Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
145ebbe11ddSYork Sun   window to physical address so that all physical memory can be tested.
146ebbe11ddSYork Sun
1477fd101c9SyorkCombination of hwconfig
1487fd101c9Syork=======================
1497fd101c9SyorkHwconfig can be combined with multiple parameters, for example, on a supported
1507fd101c9Syorkplatform
1517fd101c9Syork
152e1fd16b6SYork Sunhwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
153e1fd16b6SYork Sun
154*eb118807SShengzhou Liu
155e1fd16b6SYork SunTable for dynamic ODT for DDR3
156e1fd16b6SYork Sun==============================
157e1fd16b6SYork SunFor single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
158e1fd16b6SYork Sunbe needed, depending on the configuration. The numbers in the following tables are
159e1fd16b6SYork Sunin Ohms.
160e1fd16b6SYork Sun
161e1fd16b6SYork Sun* denotes dynamic ODT
162e1fd16b6SYork Sun
163e1fd16b6SYork SunTwo slots system
164e1fd16b6SYork Sun+-----------------------+----------+---------------+-----------------------------+-----------------------------+
165e1fd16b6SYork Sun|     Configuration	|	   |DRAM controller|	       Slot 1		 |	      Slot 2	       |
166e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
167e1fd16b6SYork Sun|	    |		|	   |	   |	   |	 Rank 1   |	Rank 2	 |   Rank 1	|    Rank 2    |
168e1fd16b6SYork Sun+  Slot 1   |	Slot 2	|Write/Read| Write | Read  |-------+------+-------+------+-------+------+-------+------+
169e1fd16b6SYork Sun|	    |		|	   |	   |	   | Write | Read | Write | Read | Write | Read | Write | Read |
170e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
171e1fd16b6SYork Sun|	    |		|  Slot 1  |  off  | 75    | 120   | off  | off   | off  | off	 | off	| 30	| 30   |
172e1fd16b6SYork Sun| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
173e1fd16b6SYork Sun|	    |		|  Slot 2  |  off  | 75    | off   | off  | 30	  | 30	 | 120	 | off	| off	| off  |
174e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
175e1fd16b6SYork Sun|	    |		|  Slot 1  |  off  | 75    | 120   | off  | off   | off  | 20	 | 20	|	|      |
176e1fd16b6SYork Sun| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
177e1fd16b6SYork Sun|	    |		|  Slot 2  |  off  | 75    | off   | off  | 20	  | 20	 | 120	*| off	|	|      |
178e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
179e1fd16b6SYork Sun|	    |		|  Slot 1  |  off  | 75    | 120  *| off  |	  |	 | off	 | off	| 20	| 20   |
180e1fd16b6SYork Sun|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
181e1fd16b6SYork Sun|	    |		|  Slot 2  |  off  | 75    | 20    | 20   |	  |	 | 120	 | off	| off	| off  |
182e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
183e1fd16b6SYork Sun|	    |		|  Slot 1  |  off  | 75    | 120  *| off  |	  |	 | 30	 | 30	|	|      |
184e1fd16b6SYork Sun|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
185e1fd16b6SYork Sun|	    |		|  Slot 2  |  off  | 75    | 30    | 30   |	  |	 | 120	*| off	|	|      |
186e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
187e1fd16b6SYork Sun| Dual Rank |	Empty	|  Slot 1  |  off  | 75    | 40    | off  | off   | off  |	 |	|	|      |
188e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
189e1fd16b6SYork Sun|   Empty   | Dual Rank |  Slot 2  |  off  | 75    |	   |	  |	  |	 | 40	 | off	| off	| off  |
190e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
191e1fd16b6SYork Sun|Single Rank|	Empty	|  Slot 1  |  off  | 75    | 40    | off  |	  |	 |	 |	|	|      |
192e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
193e1fd16b6SYork Sun|   Empty   |Single Rank|  Slot 2  |  off  | 75    |	   |	  |	  |	 | 40	 | off	|	|      |
194e1fd16b6SYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
195e1fd16b6SYork Sun
196e1fd16b6SYork SunSingle slot system
197e1fd16b6SYork Sun+-------------+------------+---------------+-----------------------------+-----------------------------+
198e1fd16b6SYork Sun|	      |		   |DRAM controller|	 Rank 1   |    Rank 2	 |    Rank 3	|    Rank 4    |
199e1fd16b6SYork Sun|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
200e1fd16b6SYork Sun|	      |		   | Write | Read  | Write | Read | Write | Read | Write | Read | Write | Read |
201e1fd16b6SYork Sun+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
202e1fd16b6SYork Sun|	      |   R1	   | off   | 75    | 120  *| off  | off   | off  | 20	 | 20	| off	| off  |
203e1fd16b6SYork Sun|	      |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
204e1fd16b6SYork Sun|	      |   R2	   | off   | 75    | off   | 20   | 120   | off  | 20	 | 20	| off	| off  |
205e1fd16b6SYork Sun|  Quad Rank  |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
206e1fd16b6SYork Sun|	      |   R3	   | off   | 75    | 20    | 20   | off   | off  | 120	*| off	| off	| off  |
207e1fd16b6SYork Sun|	      |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
208e1fd16b6SYork Sun|	      |   R4	   | off   | 75    | 20    | 20   | off   | off  | off	 | 20	| 120	| off  |
209e1fd16b6SYork Sun+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
210e1fd16b6SYork Sun|	      |   R1	   | off   | 75    | 40    | off  | off   | off  |
211e1fd16b6SYork Sun|  Dual Rank  |------------+-------+-------+-------+------+-------+------+
212e1fd16b6SYork Sun|	      |   R2	   | off   | 75    | 40    | off  | off   | off  |
213e1fd16b6SYork Sun+-------------+------------+-------+-------+-------+------+-------+------+
214e1fd16b6SYork Sun| Single Rank |   R1	   | off   | 75    | 40    | off  |
215e1fd16b6SYork Sun+-------------+------------+-------+-------+-------+------+
216e1fd16b6SYork Sun
217e1fd16b6SYork SunReference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
218e1fd16b6SYork Sun	  http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
2194e57382fSYork Sun
2204e57382fSYork Sun
2214e57382fSYork SunTable for ODT for DDR2
2224e57382fSYork Sun======================
2234e57382fSYork SunTwo slots system
2244e57382fSYork Sun+-----------------------+----------+---------------+-----------------------------+-----------------------------+
2254e57382fSYork Sun|     Configuration     |          |DRAM controller|           Slot 1            |            Slot 2           |
2264e57382fSYork Sun+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
2274e57382fSYork Sun|           |           |          |       |       |     Rank 1   |     Rank 2   |   Rank 1     |    Rank 2    |
2284e57382fSYork Sun+  Slot 1   |   Slot 2  |Write/Read| Write | Read  |-------+------+-------+------+-------+------+-------+------+
2294e57382fSYork Sun|           |           |          |       |       | Write | Read | Write | Read | Write | Read | Write | Read |
2304e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2314e57382fSYork Sun|           |           |  Slot 1  |  off  | 150   | off   | off  | off   | off  | 75    | 75   | off   | off  |
2324e57382fSYork Sun| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2334e57382fSYork Sun|           |           |  Slot 2  |  off  | 150   | 75    | 75   | off   | off  | off   | off  | off   | off  |
2344e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2354e57382fSYork Sun|           |           |  Slot 1  |  off  | 150   | off   | off  | off   | off  | 75    | 75   |       |      |
2364e57382fSYork Sun| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2374e57382fSYork Sun|           |           |  Slot 2  |  off  | 150   | 75    | 75   | off   | off  | off   | off  |       |      |
2384e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2394e57382fSYork Sun|           |           |  Slot 1  |  off  | 150   | off   | off  |       |      | 75    | 75   | off   | off  |
2404e57382fSYork Sun|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2414e57382fSYork Sun|           |           |  Slot 2  |  off  | 150   | 75    | 75   |       |      | off   | off  | off   | off  |
2424e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2434e57382fSYork Sun|           |           |  Slot 1  |  off  | 150   | off   | off  |       |      | 75    | 75   |       |      |
2444e57382fSYork Sun|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2454e57382fSYork Sun|           |           |  Slot 2  |  off  | 150   | 75    | 75   |       |      | off   | off  |       |      |
2464e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2474e57382fSYork Sun| Dual Rank |   Empty   |  Slot 1  |  off  | 75    | 150   | off  | off   | off  |       |      |       |      |
2484e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2494e57382fSYork Sun|   Empty   | Dual Rank |  Slot 2  |  off  | 75    |       |      |       |      | 150   | off  | off   | off  |
2504e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2514e57382fSYork Sun|Single Rank|   Empty   |  Slot 1  |  off  | 75    | 150   | off  |       |      |       |      |       |      |
2524e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2534e57382fSYork Sun|   Empty   |Single Rank|  Slot 2  |  off  | 75    |       |      |       |      | 150   | off  |       |      |
2544e57382fSYork Sun+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
2554e57382fSYork Sun
2564e57382fSYork SunSingle slot system
2574e57382fSYork Sun+-------------+------------+---------------+-----------------------------+
2584e57382fSYork Sun|             |            |DRAM controller|     Rank 1   |    Rank 2    |
2594e57382fSYork Sun|Configuration| Write/Read |-------+-------+-------+------+-------+------+
2604e57382fSYork Sun|             |            | Write | Read  | Write | Read | Write | Read |
2614e57382fSYork Sun+-------------+------------+-------+-------+-------+------+-------+------+
2624e57382fSYork Sun|             |   R1       | off   | 75    | 150   | off  | off   | off  |
2634e57382fSYork Sun|  Dual Rank  |------------+-------+-------+-------+------+-------+------+
2644e57382fSYork Sun|             |   R2       | off   | 75    | 150   | off  | off   | off  |
2654e57382fSYork Sun+-------------+------------+-------+-------+-------+------+-------+------+
2664e57382fSYork Sun| Single Rank |   R1       | off   | 75    | 150   | off  |
2674e57382fSYork Sun+-------------+------------+-------+-------+-------+------+
2684e57382fSYork Sun
2694e57382fSYork SunReference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
2704e57382fSYork Sun
2716f5e1dc5SYork Sun
2726f5e1dc5SYork SunInteractive DDR debugging
2736f5e1dc5SYork Sun===========================
2746f5e1dc5SYork Sun
27502a9ce71SJames YangFor DDR parameter tuning up and debugging, the interactive DDR debugger can
27602a9ce71SJames Yangbe activated by setting the environment variable "ddr_interactive" to any
27702a9ce71SJames Yangvalue.  (The value of ddr_interactive may have a meaning in the future, but,
27802a9ce71SJames Yangfor now, the presence of the variable will cause the debugger to run.)  Once
279a187559eSBin Mengactivated, U-Boot will show the prompt "FSL DDR>" before enabling the DDR
28002a9ce71SJames Yangcontroller.  The available commands are printed by typing "help".
2816f5e1dc5SYork Sun
28202a9ce71SJames YangAnother way to enter the interactive DDR debugger without setting the
28302a9ce71SJames Yangenvironment variable is to send the 'd' character early during the boot
28402a9ce71SJames Yangprocess.  To save booting time, no additional delay is added, so the window
28502a9ce71SJames Yangto send the key press is very short -- basically, it is the time before the
28602a9ce71SJames Yangmemory controller code starts to run.  For example, when rebooting from
287a187559eSBin Mengwithin U-Boot, the user must press 'd' IMMEDIATELY after hitting enter to
28802a9ce71SJames Yanginitiate a 'reset' command.  In case of power on/reset, the user can hold
28902a9ce71SJames Yangdown the 'd' key while applying power or hitting the board's reset button.
290e750cfaaSYork Sun
2916f5e1dc5SYork SunThe example flow of using interactive debugging is
2926f5e1dc5SYork Suntype command "compute" to calculate the parameters from the default
2936f5e1dc5SYork Suntype command "print" with arguments to show SPD, options, registers
2946f5e1dc5SYork Suntype command "edit" with arguments to change any if desired
2955926ee38SJames Yangtype command "copy" with arguments to copy controller/dimm settings
2966f5e1dc5SYork Suntype command "go" to continue calculation and enable DDR controller
29702a9ce71SJames Yang
29802a9ce71SJames YangAdditional commands to restart the debugging are:
2996f5e1dc5SYork Suntype command "reset" to reset the board
3006f5e1dc5SYork Suntype command "recompute" to reload SPD and start over
3016f5e1dc5SYork Sun
3026f5e1dc5SYork SunNote, check "next_step" to show the flow. For example, after edit opts, the
3036f5e1dc5SYork Sunnext_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
30402a9ce71SJames YangSTEP_PROGRAM_REGS.  Upon issuing command "go", the debugger will program the
30502a9ce71SJames YangDDR controller with the current setting without further calculation and then
30602a9ce71SJames Yangexit to resume the booting of the machine.
3076f5e1dc5SYork Sun
3086f5e1dc5SYork SunThe detail syntax for each commands are
3096f5e1dc5SYork Sun
3106f5e1dc5SYork Sunprint [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
3116f5e1dc5SYork Sun	c<n>		- the controller number, eg. c0, c1
3126f5e1dc5SYork Sun	d<n>		- the DIMM number, eg. d0, d1
3136f5e1dc5SYork Sun	spd		- print SPD data
314c46bf09eSThomas Weber	dimmparms	- DIMM parameters, calculated from SPD
3156f5e1dc5SYork Sun	commonparms	- lowest common parameters for all DIMMs
3166f5e1dc5SYork Sun	opts		- options
3176f5e1dc5SYork Sun	addresses	- address assignment (not implemented yet)
3186f5e1dc5SYork Sun	regs		- controller registers
3196f5e1dc5SYork Sun
3206f5e1dc5SYork Sunedit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
3216f5e1dc5SYork Sun	c<n>		- the controller number, eg. c0, c1
3226f5e1dc5SYork Sun	d<n>		- the DIMM number, eg. d0, d1
3236f5e1dc5SYork Sun	spd		- print SPD data
324c46bf09eSThomas Weber	dimmparms	- DIMM parameters, calculated from SPD
3256f5e1dc5SYork Sun	commonparms	- lowest common parameters for all DIMMs
3266f5e1dc5SYork Sun	opts		- options
3276f5e1dc5SYork Sun	addresses	- address assignment (not implemented yet)
3286f5e1dc5SYork Sun	regs		- controller registers
3296f5e1dc5SYork Sun	<element>	- name of the modified element
3306f5e1dc5SYork Sun			  byte number if the object is SPD
3316f5e1dc5SYork Sun	<value>		- decimal or heximal (prefixed with 0x) numbers
3326f5e1dc5SYork Sun
3335926ee38SJames Yangcopy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
3345926ee38SJames Yang	same as for "edit" command
3355926ee38SJames Yang	DIMM numbers ignored for commonparms, opts, and regs
3365926ee38SJames Yang
3376f5e1dc5SYork Sunreset
3386f5e1dc5SYork Sun	no arguement	- reset the board
3396f5e1dc5SYork Sun
3406f5e1dc5SYork Sunrecompute
3416f5e1dc5SYork Sun	no argument	- reload SPD and start over
3426f5e1dc5SYork Sun
3436f5e1dc5SYork Suncompute
3446f5e1dc5SYork Sun	no argument	- recompute from current next_step
3456f5e1dc5SYork Sun
3466f5e1dc5SYork Sunnext_step
3476f5e1dc5SYork Sun	no argument	- show current next_step
3486f5e1dc5SYork Sun
3496f5e1dc5SYork Sunhelp
3506f5e1dc5SYork Sun	no argument	- print a list of all commands
3516f5e1dc5SYork Sun
3526f5e1dc5SYork Sungo
353a187559eSBin Meng	no argument	- program memory controller(s) and continue with U-Boot
3546f5e1dc5SYork Sun
3556f5e1dc5SYork SunExamples of debugging flow
3566f5e1dc5SYork Sun
3576f5e1dc5SYork Sun	FSL DDR>compute
3586f5e1dc5SYork Sun	Detected UDIMM UG51U6400N8SU-ACF
35902a9ce71SJames Yang	FSL DDR>print
3606f5e1dc5SYork Sun	print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
3616f5e1dc5SYork Sun	FSL DDR>print dimmparms
3626f5e1dc5SYork Sun	DIMM parameters:  Controller=0 DIMM=0
3636f5e1dc5SYork Sun	DIMM organization parameters:
3646f5e1dc5SYork Sun	module part name = UG51U6400N8SU-ACF
3656f5e1dc5SYork Sun	rank_density = 2147483648 bytes (2048 megabytes)
3666f5e1dc5SYork Sun	capacity = 4294967296 bytes (4096 megabytes)
3676f5e1dc5SYork Sun	burst_lengths_bitmask = 0C
3686f5e1dc5SYork Sun	base_addresss = 0 (00000000 00000000)
3696f5e1dc5SYork Sun	n_ranks = 2
3706f5e1dc5SYork Sun	data_width = 64
3716f5e1dc5SYork Sun	primary_sdram_width = 64
3726f5e1dc5SYork Sun	ec_sdram_width = 0
3736f5e1dc5SYork Sun	registered_dimm = 0
3746f5e1dc5SYork Sun	n_row_addr = 15
3756f5e1dc5SYork Sun	n_col_addr = 10
3766f5e1dc5SYork Sun	edc_config = 0
3776f5e1dc5SYork Sun	n_banks_per_sdram_device = 8
3786f5e1dc5SYork Sun	tCKmin_X_ps = 1500
3796f5e1dc5SYork Sun	tCKmin_X_minus_1_ps = 0
3806f5e1dc5SYork Sun	tCKmin_X_minus_2_ps = 0
3816f5e1dc5SYork Sun	tCKmax_ps = 0
3826f5e1dc5SYork Sun	caslat_X = 960
3836f5e1dc5SYork Sun	tAA_ps = 13125
3846f5e1dc5SYork Sun	caslat_X_minus_1 = 0
3856f5e1dc5SYork Sun	caslat_X_minus_2 = 0
3866f5e1dc5SYork Sun	caslat_lowest_derated = 0
3876f5e1dc5SYork Sun	tRCD_ps = 13125
3886f5e1dc5SYork Sun	tRP_ps = 13125
3896f5e1dc5SYork Sun	tRAS_ps = 36000
3906f5e1dc5SYork Sun	tWR_ps = 15000
3916f5e1dc5SYork Sun	tWTR_ps = 7500
3926f5e1dc5SYork Sun	tRFC_ps = 160000
3936f5e1dc5SYork Sun	tRRD_ps = 6000
3946f5e1dc5SYork Sun	tRC_ps = 49125
3956f5e1dc5SYork Sun	refresh_rate_ps = 7800000
3966f5e1dc5SYork Sun	tIS_ps = 0
3976f5e1dc5SYork Sun	tIH_ps = 0
3986f5e1dc5SYork Sun	tDS_ps = 0
3996f5e1dc5SYork Sun	tDH_ps = 0
4006f5e1dc5SYork Sun	tRTP_ps = 7500
4016f5e1dc5SYork Sun	tDQSQ_max_ps = 0
4026f5e1dc5SYork Sun	tQHS_ps = 0
4036f5e1dc5SYork Sun	FSL DDR>edit c0 opts ECC_mode 0
4046f5e1dc5SYork Sun	FSL DDR>edit c0 regs cs0_bnds 0x000000FF
4056f5e1dc5SYork Sun	FSL DDR>go
4066f5e1dc5SYork Sun	2 GiB left unmapped
4076f5e1dc5SYork Sun	4 GiB (DDR3, 64-bit, CL=9, ECC off)
4086f5e1dc5SYork Sun	       DDR Chip-Select Interleaving Mode: CS0+CS1
4096f5e1dc5SYork Sun	Testing 0x00000000 - 0x7fffffff
4106f5e1dc5SYork Sun	Testing 0x80000000 - 0xffffffff
4116f5e1dc5SYork Sun	Remap DDR 2 GiB left unmapped
4126f5e1dc5SYork Sun
4136f5e1dc5SYork Sun	POST memory PASSED
4146f5e1dc5SYork Sun	Flash: 128 MiB
4156f5e1dc5SYork Sun	L2:    128 KB enabled
4166f5e1dc5SYork Sun	Corenet Platform Cache: 1024 KB enabled
4176f5e1dc5SYork Sun	SERDES: timeout resetting bank 3
4186f5e1dc5SYork Sun	SRIO1: disabled
4196f5e1dc5SYork Sun	SRIO2: disabled
4206f5e1dc5SYork Sun	MMC:  FSL_ESDHC: 0
4216f5e1dc5SYork Sun	EEPROM: Invalid ID (ff ff ff ff)
4226f5e1dc5SYork Sun	PCIe1: disabled
4236f5e1dc5SYork Sun	PCIe2: Root Complex, x1, regs @ 0xfe201000
4246f5e1dc5SYork Sun	  01:00.0     - 8086:10d3 - Network controller
4256f5e1dc5SYork Sun	PCIe2: Bus 00 - 01
4266f5e1dc5SYork Sun	PCIe3: disabled
4276f5e1dc5SYork Sun	In:    serial
4286f5e1dc5SYork Sun	Out:   serial
4296f5e1dc5SYork Sun	Err:   serial
4306f5e1dc5SYork Sun	Net:   Initializing Fman
4316f5e1dc5SYork Sun	Fman1: Uploading microcode version 101.8.0
4326f5e1dc5SYork Sun	e1000: 00:1b:21:81:d2:e0
4336f5e1dc5SYork Sun	FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
4346f5e1dc5SYork Sun	Warning: e1000#0 MAC addresses don't match:
4356f5e1dc5SYork Sun	Address in SROM is         00:1b:21:81:d2:e0
4366f5e1dc5SYork Sun	Address in environment is  00:e0:0c:00:ea:05
4376f5e1dc5SYork Sun
4386f5e1dc5SYork Sun	Hit any key to stop autoboot:  0
4396f5e1dc5SYork Sun	=>
440