1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
244937214SPrabhakar Kushwaha /*
344937214SPrabhakar Kushwaha  * Copyright 2015 Freescale Semiconductor, Inc.
444937214SPrabhakar Kushwaha  */
544937214SPrabhakar Kushwaha 
644937214SPrabhakar Kushwaha #ifndef __DDR_H__
744937214SPrabhakar Kushwaha #define __DDR_H__
844937214SPrabhakar Kushwaha struct board_specific_parameters {
944937214SPrabhakar Kushwaha 	u32 n_ranks;
1044937214SPrabhakar Kushwaha 	u32 datarate_mhz_high;
1144937214SPrabhakar Kushwaha 	u32 rank_gb;
1244937214SPrabhakar Kushwaha 	u32 clk_adjust;
1344937214SPrabhakar Kushwaha 	u32 wrlvl_start;
1444937214SPrabhakar Kushwaha 	u32 wrlvl_ctl_2;
1544937214SPrabhakar Kushwaha 	u32 wrlvl_ctl_3;
1644937214SPrabhakar Kushwaha };
1744937214SPrabhakar Kushwaha 
1844937214SPrabhakar Kushwaha /*
1944937214SPrabhakar Kushwaha  * These tables contain all valid speeds we want to override with board
2044937214SPrabhakar Kushwaha  * specific parameters. datarate_mhz_high values need to be in ascending order
2144937214SPrabhakar Kushwaha  * for each n_ranks group.
2244937214SPrabhakar Kushwaha  */
2344937214SPrabhakar Kushwaha 
2444937214SPrabhakar Kushwaha static const struct board_specific_parameters udimm0[] = {
2544937214SPrabhakar Kushwaha 	/*
2644937214SPrabhakar Kushwaha 	 * memory controller 0
2744937214SPrabhakar Kushwaha 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
2844937214SPrabhakar Kushwaha 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
2944937214SPrabhakar Kushwaha 	 */
30e04f9d0cSShengzhou Liu 	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
31e04f9d0cSShengzhou Liu 	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
32e04f9d0cSShengzhou Liu 	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
33e04f9d0cSShengzhou Liu 	{2,  2300, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
3444937214SPrabhakar Kushwaha 	{}
3544937214SPrabhakar Kushwaha };
3644937214SPrabhakar Kushwaha 
3744937214SPrabhakar Kushwaha /* DP-DDR DIMM */
3844937214SPrabhakar Kushwaha static const struct board_specific_parameters udimm2[] = {
3944937214SPrabhakar Kushwaha 	/*
4044937214SPrabhakar Kushwaha 	 * memory controller 2
4144937214SPrabhakar Kushwaha 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
4244937214SPrabhakar Kushwaha 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
4344937214SPrabhakar Kushwaha 	 */
44e04f9d0cSShengzhou Liu 	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
45e04f9d0cSShengzhou Liu 	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
46e04f9d0cSShengzhou Liu 	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
47e04f9d0cSShengzhou Liu 	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
4844937214SPrabhakar Kushwaha 	{}
4944937214SPrabhakar Kushwaha };
5044937214SPrabhakar Kushwaha 
5144937214SPrabhakar Kushwaha static const struct board_specific_parameters rdimm0[] = {
5244937214SPrabhakar Kushwaha 	/*
5344937214SPrabhakar Kushwaha 	 * memory controller 0
5444937214SPrabhakar Kushwaha 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
5544937214SPrabhakar Kushwaha 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
5644937214SPrabhakar Kushwaha 	 */
57e04f9d0cSShengzhou Liu 	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
58e04f9d0cSShengzhou Liu 	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
59e04f9d0cSShengzhou Liu 	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
60e04f9d0cSShengzhou Liu 	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
6144937214SPrabhakar Kushwaha 	{}
6244937214SPrabhakar Kushwaha };
6344937214SPrabhakar Kushwaha 
6444937214SPrabhakar Kushwaha /* DP-DDR DIMM */
6544937214SPrabhakar Kushwaha static const struct board_specific_parameters rdimm2[] = {
6644937214SPrabhakar Kushwaha 	/*
6744937214SPrabhakar Kushwaha 	 * memory controller 2
6844937214SPrabhakar Kushwaha 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
6944937214SPrabhakar Kushwaha 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
7044937214SPrabhakar Kushwaha 	 */
71e04f9d0cSShengzhou Liu 	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
72e04f9d0cSShengzhou Liu 	{2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
73e04f9d0cSShengzhou Liu 	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
74e04f9d0cSShengzhou Liu 	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
7544937214SPrabhakar Kushwaha 	{}
7644937214SPrabhakar Kushwaha };
7744937214SPrabhakar Kushwaha 
7844937214SPrabhakar Kushwaha static const struct board_specific_parameters *udimms[] = {
7944937214SPrabhakar Kushwaha 	udimm0,
8044937214SPrabhakar Kushwaha 	udimm0,
8144937214SPrabhakar Kushwaha 	udimm2,
8244937214SPrabhakar Kushwaha };
8344937214SPrabhakar Kushwaha 
8444937214SPrabhakar Kushwaha static const struct board_specific_parameters *rdimms[] = {
8544937214SPrabhakar Kushwaha 	rdimm0,
8644937214SPrabhakar Kushwaha 	rdimm0,
8744937214SPrabhakar Kushwaha 	rdimm2,
8844937214SPrabhakar Kushwaha };
8944937214SPrabhakar Kushwaha 
9044937214SPrabhakar Kushwaha 
9144937214SPrabhakar Kushwaha #endif
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