1*83d290c5STom Rini // SPDX-License-Identifier: Intel
238ad43e4SBin Meng /*
338ad43e4SBin Meng * Copyright (C) 2013, Intel Corporation
438ad43e4SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
538ad43e4SBin Meng *
638ad43e4SBin Meng * Ported from Intel released Quark UEFI BIOS
738ad43e4SBin Meng * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
838ad43e4SBin Meng */
938ad43e4SBin Meng
1038ad43e4SBin Meng #include <common.h>
1138ad43e4SBin Meng #include <asm/arch/mrc.h>
1238ad43e4SBin Meng #include <asm/arch/msg_port.h>
1338ad43e4SBin Meng #include "mrc_util.h"
1438ad43e4SBin Meng #include "hte.h"
1538ad43e4SBin Meng
1638ad43e4SBin Meng /**
1738ad43e4SBin Meng * Enable HTE to detect all possible errors for the given training parameters
1838ad43e4SBin Meng * (per-bit or full byte lane).
1938ad43e4SBin Meng */
hte_enable_all_errors(void)2038ad43e4SBin Meng static void hte_enable_all_errors(void)
2138ad43e4SBin Meng {
22312cc39eSBin Meng msg_port_write(HTE, 0x000200a2, 0xffffffff);
23312cc39eSBin Meng msg_port_write(HTE, 0x000200a3, 0x000000ff);
24312cc39eSBin Meng msg_port_write(HTE, 0x000200a4, 0x00000000);
2538ad43e4SBin Meng }
2638ad43e4SBin Meng
2738ad43e4SBin Meng /**
2838ad43e4SBin Meng * Go and read the HTE register in order to find any error
2938ad43e4SBin Meng *
3038ad43e4SBin Meng * @return: The errors detected in the HTE status register
3138ad43e4SBin Meng */
hte_check_errors(void)3238ad43e4SBin Meng static u32 hte_check_errors(void)
3338ad43e4SBin Meng {
34312cc39eSBin Meng return msg_port_read(HTE, 0x000200a7);
3538ad43e4SBin Meng }
3638ad43e4SBin Meng
3738ad43e4SBin Meng /**
3838ad43e4SBin Meng * Wait until HTE finishes
3938ad43e4SBin Meng */
hte_wait_for_complete(void)4038ad43e4SBin Meng static void hte_wait_for_complete(void)
4138ad43e4SBin Meng {
4238ad43e4SBin Meng u32 tmp;
4338ad43e4SBin Meng
4438ad43e4SBin Meng ENTERFN();
4538ad43e4SBin Meng
46312cc39eSBin Meng do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0);
4738ad43e4SBin Meng
4838ad43e4SBin Meng tmp = msg_port_read(HTE, 0x00020011);
49312cc39eSBin Meng tmp |= (1 << 9);
50312cc39eSBin Meng tmp &= ~((1 << 12) | (1 << 13));
5138ad43e4SBin Meng msg_port_write(HTE, 0x00020011, tmp);
5238ad43e4SBin Meng
5338ad43e4SBin Meng LEAVEFN();
5438ad43e4SBin Meng }
5538ad43e4SBin Meng
5638ad43e4SBin Meng /**
5738ad43e4SBin Meng * Clear registers related with errors in the HTE
5838ad43e4SBin Meng */
hte_clear_error_regs(void)5938ad43e4SBin Meng static void hte_clear_error_regs(void)
6038ad43e4SBin Meng {
6138ad43e4SBin Meng u32 tmp;
6238ad43e4SBin Meng
6338ad43e4SBin Meng /*
6438ad43e4SBin Meng * Clear all HTE errors and enable error checking
6538ad43e4SBin Meng * for burst and chunk.
6638ad43e4SBin Meng */
67312cc39eSBin Meng tmp = msg_port_read(HTE, 0x000200a1);
68312cc39eSBin Meng tmp |= (1 << 8);
69312cc39eSBin Meng msg_port_write(HTE, 0x000200a1, tmp);
7038ad43e4SBin Meng }
7138ad43e4SBin Meng
7238ad43e4SBin Meng /**
7338ad43e4SBin Meng * Execute a basic single-cache-line memory write/read/verify test using simple
7438ad43e4SBin Meng * constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
7538ad43e4SBin Meng *
7638ad43e4SBin Meng * See hte_basic_write_read() which is the external visible wrapper.
7738ad43e4SBin Meng *
7838ad43e4SBin Meng * @mrc_params: host structure for all MRC global data
7938ad43e4SBin Meng * @addr: memory adress being tested (must hit specific channel/rank)
8038ad43e4SBin Meng * @first_run: if set then the HTE registers are configured, otherwise it is
8138ad43e4SBin Meng * assumed configuration is done and we just re-run the test
8238ad43e4SBin Meng * @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
8338ad43e4SBin Meng *
8438ad43e4SBin Meng * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
8538ad43e4SBin Meng */
hte_basic_data_cmp(struct mrc_params * mrc_params,u32 addr,u8 first_run,u8 mode)8638ad43e4SBin Meng static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
8738ad43e4SBin Meng u8 first_run, u8 mode)
8838ad43e4SBin Meng {
8938ad43e4SBin Meng u32 pattern;
9038ad43e4SBin Meng u32 offset;
9138ad43e4SBin Meng
9238ad43e4SBin Meng if (first_run) {
93312cc39eSBin Meng msg_port_write(HTE, 0x00020020, 0x01b10021);
9438ad43e4SBin Meng msg_port_write(HTE, 0x00020021, 0x06000000);
9538ad43e4SBin Meng msg_port_write(HTE, 0x00020022, addr >> 6);
9638ad43e4SBin Meng msg_port_write(HTE, 0x00020062, 0x00800015);
97312cc39eSBin Meng msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
98312cc39eSBin Meng msg_port_write(HTE, 0x00020064, 0xcccccccc);
99312cc39eSBin Meng msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
10038ad43e4SBin Meng msg_port_write(HTE, 0x00020061, 0x00030008);
10138ad43e4SBin Meng
10238ad43e4SBin Meng if (mode == WRITE_TRAIN)
103312cc39eSBin Meng pattern = 0xc33c0000;
10438ad43e4SBin Meng else /* READ_TRAIN */
105312cc39eSBin Meng pattern = 0xaa5555aa;
10638ad43e4SBin Meng
107312cc39eSBin Meng for (offset = 0x80; offset <= 0x8f; offset++)
10838ad43e4SBin Meng msg_port_write(HTE, offset, pattern);
10938ad43e4SBin Meng }
11038ad43e4SBin Meng
111312cc39eSBin Meng msg_port_write(HTE, 0x000200a1, 0xffff1000);
11238ad43e4SBin Meng msg_port_write(HTE, 0x00020011, 0x00011000);
11338ad43e4SBin Meng msg_port_write(HTE, 0x00020011, 0x00011100);
11438ad43e4SBin Meng
11538ad43e4SBin Meng hte_wait_for_complete();
11638ad43e4SBin Meng
11738ad43e4SBin Meng /*
11838ad43e4SBin Meng * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
11938ad43e4SBin Meng * any bytelane errors.
12038ad43e4SBin Meng */
121312cc39eSBin Meng return (hte_check_errors() >> 8) & 0xff;
12238ad43e4SBin Meng }
12338ad43e4SBin Meng
12438ad43e4SBin Meng /**
12538ad43e4SBin Meng * Examine a single-cache-line memory with write/read/verify test using multiple
12638ad43e4SBin Meng * data patterns (victim-aggressor algorithm).
12738ad43e4SBin Meng *
12838ad43e4SBin Meng * See hte_write_stress_bit_lanes() which is the external visible wrapper.
12938ad43e4SBin Meng *
13038ad43e4SBin Meng * @mrc_params: host structure for all MRC global data
13138ad43e4SBin Meng * @addr: memory adress being tested (must hit specific channel/rank)
13238ad43e4SBin Meng * @loop_cnt: number of test iterations
13338ad43e4SBin Meng * @seed_victim: victim data pattern seed
13438ad43e4SBin Meng * @seed_aggressor: aggressor data pattern seed
13538ad43e4SBin Meng * @victim_bit: should be 0 as auto-rotate feature is in use
13638ad43e4SBin Meng * @first_run: if set then the HTE registers are configured, otherwise it is
13738ad43e4SBin Meng * assumed configuration is done and we just re-run the test
13838ad43e4SBin Meng *
13938ad43e4SBin Meng * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
14038ad43e4SBin Meng */
hte_rw_data_cmp(struct mrc_params * mrc_params,u32 addr,u8 loop_cnt,u32 seed_victim,u32 seed_aggressor,u8 victim_bit,u8 first_run)14138ad43e4SBin Meng static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
14238ad43e4SBin Meng u8 loop_cnt, u32 seed_victim, u32 seed_aggressor,
14338ad43e4SBin Meng u8 victim_bit, u8 first_run)
14438ad43e4SBin Meng {
14538ad43e4SBin Meng u32 offset;
14638ad43e4SBin Meng u32 tmp;
14738ad43e4SBin Meng
14838ad43e4SBin Meng if (first_run) {
14938ad43e4SBin Meng msg_port_write(HTE, 0x00020020, 0x00910024);
15038ad43e4SBin Meng msg_port_write(HTE, 0x00020023, 0x00810024);
15138ad43e4SBin Meng msg_port_write(HTE, 0x00020021, 0x06070000);
15238ad43e4SBin Meng msg_port_write(HTE, 0x00020024, 0x06070000);
15338ad43e4SBin Meng msg_port_write(HTE, 0x00020022, addr >> 6);
15438ad43e4SBin Meng msg_port_write(HTE, 0x00020025, addr >> 6);
155312cc39eSBin Meng msg_port_write(HTE, 0x00020062, 0x0000002a);
15638ad43e4SBin Meng msg_port_write(HTE, 0x00020063, seed_victim);
15738ad43e4SBin Meng msg_port_write(HTE, 0x00020064, seed_aggressor);
15838ad43e4SBin Meng msg_port_write(HTE, 0x00020065, seed_victim);
15938ad43e4SBin Meng
16038ad43e4SBin Meng /*
16138ad43e4SBin Meng * Write the pattern buffers to select the victim bit
16238ad43e4SBin Meng *
16338ad43e4SBin Meng * Start with bit0
16438ad43e4SBin Meng */
165312cc39eSBin Meng for (offset = 0x80; offset <= 0x8f; offset++) {
16638ad43e4SBin Meng if ((offset % 8) == victim_bit)
16738ad43e4SBin Meng msg_port_write(HTE, offset, 0x55555555);
16838ad43e4SBin Meng else
169312cc39eSBin Meng msg_port_write(HTE, offset, 0xcccccccc);
17038ad43e4SBin Meng }
17138ad43e4SBin Meng
17238ad43e4SBin Meng msg_port_write(HTE, 0x00020061, 0x00000000);
17338ad43e4SBin Meng msg_port_write(HTE, 0x00020066, 0x03440000);
174312cc39eSBin Meng msg_port_write(HTE, 0x000200a1, 0xffff1000);
17538ad43e4SBin Meng }
17638ad43e4SBin Meng
17738ad43e4SBin Meng tmp = 0x10001000 | (loop_cnt << 16);
17838ad43e4SBin Meng msg_port_write(HTE, 0x00020011, tmp);
179312cc39eSBin Meng msg_port_write(HTE, 0x00020011, tmp | (1 << 8));
18038ad43e4SBin Meng
18138ad43e4SBin Meng hte_wait_for_complete();
18238ad43e4SBin Meng
18338ad43e4SBin Meng /*
18438ad43e4SBin Meng * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
18538ad43e4SBin Meng * any bytelane errors.
18638ad43e4SBin Meng */
187312cc39eSBin Meng return (hte_check_errors() >> 8) & 0xff;
18838ad43e4SBin Meng }
18938ad43e4SBin Meng
19038ad43e4SBin Meng /**
19138ad43e4SBin Meng * Use HW HTE engine to initialize or test all memory attached to a given DUNIT.
19238ad43e4SBin Meng * If flag is MRC_MEM_INIT, this routine writes 0s to all memory locations to
19338ad43e4SBin Meng * initialize ECC. If flag is MRC_MEM_TEST, this routine will send an 5AA55AA5
19438ad43e4SBin Meng * pattern to all memory locations on the RankMask and then read it back.
19538ad43e4SBin Meng * Then it sends an A55AA55A pattern to all memory locations on the RankMask
19638ad43e4SBin Meng * and reads it back.
19738ad43e4SBin Meng *
19838ad43e4SBin Meng * @mrc_params: host structure for all MRC global data
19938ad43e4SBin Meng * @flag: MRC_MEM_INIT or MRC_MEM_TEST
20038ad43e4SBin Meng *
20138ad43e4SBin Meng * @return: errors register showing HTE failures. Also prints out which rank
20238ad43e4SBin Meng * failed the HTE test if failure occurs. For rank detection to work,
20338ad43e4SBin Meng * the address map must be left in its default state. If MRC changes
20438ad43e4SBin Meng * the address map, this function must be modified to change it back
20538ad43e4SBin Meng * to default at the beginning, then restore it at the end.
20638ad43e4SBin Meng */
hte_mem_init(struct mrc_params * mrc_params,u8 flag)20738ad43e4SBin Meng u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
20838ad43e4SBin Meng {
20938ad43e4SBin Meng u32 offset;
21038ad43e4SBin Meng int test_num;
21138ad43e4SBin Meng int i;
21238ad43e4SBin Meng
21338ad43e4SBin Meng /*
21438ad43e4SBin Meng * Clear out the error registers at the start of each memory
21538ad43e4SBin Meng * init or memory test run.
21638ad43e4SBin Meng */
21738ad43e4SBin Meng hte_clear_error_regs();
21838ad43e4SBin Meng
21938ad43e4SBin Meng msg_port_write(HTE, 0x00020062, 0x00000015);
22038ad43e4SBin Meng
221312cc39eSBin Meng for (offset = 0x80; offset <= 0x8f; offset++)
222312cc39eSBin Meng msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5));
22338ad43e4SBin Meng
22438ad43e4SBin Meng msg_port_write(HTE, 0x00020021, 0x00000000);
22538ad43e4SBin Meng msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1);
226312cc39eSBin Meng msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
227312cc39eSBin Meng msg_port_write(HTE, 0x00020064, 0xcccccccc);
228312cc39eSBin Meng msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
22938ad43e4SBin Meng msg_port_write(HTE, 0x00020066, 0x03000000);
23038ad43e4SBin Meng
23138ad43e4SBin Meng switch (flag) {
23238ad43e4SBin Meng case MRC_MEM_INIT:
23338ad43e4SBin Meng /*
23438ad43e4SBin Meng * Only 1 write pass through memory is needed
23538ad43e4SBin Meng * to initialize ECC
23638ad43e4SBin Meng */
23738ad43e4SBin Meng test_num = 1;
23838ad43e4SBin Meng break;
23938ad43e4SBin Meng case MRC_MEM_TEST:
24038ad43e4SBin Meng /* Write/read then write/read with inverted pattern */
24138ad43e4SBin Meng test_num = 4;
24238ad43e4SBin Meng break;
24338ad43e4SBin Meng default:
24438ad43e4SBin Meng DPF(D_INFO, "Unknown parameter for flag: %d\n", flag);
245312cc39eSBin Meng return 0xffffffff;
24638ad43e4SBin Meng }
24738ad43e4SBin Meng
24838ad43e4SBin Meng DPF(D_INFO, "hte_mem_init");
24938ad43e4SBin Meng
25038ad43e4SBin Meng for (i = 0; i < test_num; i++) {
25138ad43e4SBin Meng DPF(D_INFO, ".");
25238ad43e4SBin Meng
25338ad43e4SBin Meng if (i == 0) {
25438ad43e4SBin Meng msg_port_write(HTE, 0x00020061, 0x00000000);
25538ad43e4SBin Meng msg_port_write(HTE, 0x00020020, 0x00110010);
25638ad43e4SBin Meng } else if (i == 1) {
25738ad43e4SBin Meng msg_port_write(HTE, 0x00020061, 0x00000000);
25838ad43e4SBin Meng msg_port_write(HTE, 0x00020020, 0x00010010);
25938ad43e4SBin Meng } else if (i == 2) {
26038ad43e4SBin Meng msg_port_write(HTE, 0x00020061, 0x00010100);
26138ad43e4SBin Meng msg_port_write(HTE, 0x00020020, 0x00110010);
26238ad43e4SBin Meng } else {
26338ad43e4SBin Meng msg_port_write(HTE, 0x00020061, 0x00010100);
26438ad43e4SBin Meng msg_port_write(HTE, 0x00020020, 0x00010010);
26538ad43e4SBin Meng }
26638ad43e4SBin Meng
26738ad43e4SBin Meng msg_port_write(HTE, 0x00020011, 0x00111000);
26838ad43e4SBin Meng msg_port_write(HTE, 0x00020011, 0x00111100);
26938ad43e4SBin Meng
27038ad43e4SBin Meng hte_wait_for_complete();
27138ad43e4SBin Meng
27238ad43e4SBin Meng /* If this is a READ pass, check for errors at the end */
27338ad43e4SBin Meng if ((i % 2) == 1) {
27438ad43e4SBin Meng /* Return immediately if error */
27538ad43e4SBin Meng if (hte_check_errors())
27638ad43e4SBin Meng break;
27738ad43e4SBin Meng }
27838ad43e4SBin Meng }
27938ad43e4SBin Meng
28038ad43e4SBin Meng DPF(D_INFO, "done\n");
28138ad43e4SBin Meng
28238ad43e4SBin Meng return hte_check_errors();
28338ad43e4SBin Meng }
28438ad43e4SBin Meng
28538ad43e4SBin Meng /**
28638ad43e4SBin Meng * Execute a basic single-cache-line memory write/read/verify test using simple
28738ad43e4SBin Meng * constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
28838ad43e4SBin Meng *
28938ad43e4SBin Meng * @mrc_params: host structure for all MRC global data
29038ad43e4SBin Meng * @addr: memory adress being tested (must hit specific channel/rank)
29138ad43e4SBin Meng * @first_run: if set then the HTE registers are configured, otherwise it is
29238ad43e4SBin Meng * assumed configuration is done and we just re-run the test
29338ad43e4SBin Meng * @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
29438ad43e4SBin Meng *
29538ad43e4SBin Meng * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
29638ad43e4SBin Meng */
hte_basic_write_read(struct mrc_params * mrc_params,u32 addr,u8 first_run,u8 mode)29738ad43e4SBin Meng u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
29838ad43e4SBin Meng u8 first_run, u8 mode)
29938ad43e4SBin Meng {
30038ad43e4SBin Meng u16 errors;
30138ad43e4SBin Meng
30238ad43e4SBin Meng ENTERFN();
30338ad43e4SBin Meng
30438ad43e4SBin Meng /* Enable all error reporting in preparation for HTE test */
30538ad43e4SBin Meng hte_enable_all_errors();
30638ad43e4SBin Meng hte_clear_error_regs();
30738ad43e4SBin Meng
30838ad43e4SBin Meng errors = hte_basic_data_cmp(mrc_params, addr, first_run, mode);
30938ad43e4SBin Meng
31038ad43e4SBin Meng LEAVEFN();
31138ad43e4SBin Meng
31238ad43e4SBin Meng return errors;
31338ad43e4SBin Meng }
31438ad43e4SBin Meng
31538ad43e4SBin Meng /**
31638ad43e4SBin Meng * Examine a single-cache-line memory with write/read/verify test using multiple
31738ad43e4SBin Meng * data patterns (victim-aggressor algorithm).
31838ad43e4SBin Meng *
31938ad43e4SBin Meng * @mrc_params: host structure for all MRC global data
32038ad43e4SBin Meng * @addr: memory adress being tested (must hit specific channel/rank)
32138ad43e4SBin Meng * @first_run: if set then the HTE registers are configured, otherwise it is
32238ad43e4SBin Meng * assumed configuration is done and we just re-run the test
32338ad43e4SBin Meng *
32438ad43e4SBin Meng * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
32538ad43e4SBin Meng */
hte_write_stress_bit_lanes(struct mrc_params * mrc_params,u32 addr,u8 first_run)32638ad43e4SBin Meng u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
32738ad43e4SBin Meng u32 addr, u8 first_run)
32838ad43e4SBin Meng {
32938ad43e4SBin Meng u16 errors;
33038ad43e4SBin Meng u8 victim_bit = 0;
33138ad43e4SBin Meng
33238ad43e4SBin Meng ENTERFN();
33338ad43e4SBin Meng
33438ad43e4SBin Meng /* Enable all error reporting in preparation for HTE test */
33538ad43e4SBin Meng hte_enable_all_errors();
33638ad43e4SBin Meng hte_clear_error_regs();
33738ad43e4SBin Meng
33838ad43e4SBin Meng /*
33938ad43e4SBin Meng * Loop through each bit in the bytelane.
34038ad43e4SBin Meng *
34138ad43e4SBin Meng * Each pass creates a victim bit while keeping all other bits the same
34238ad43e4SBin Meng * as aggressors. AVN HTE adds an auto-rotate feature which allows us
34338ad43e4SBin Meng * to program the entire victim/aggressor sequence in 1 step.
34438ad43e4SBin Meng *
34538ad43e4SBin Meng * The victim bit rotates on each pass so no need to have software
34638ad43e4SBin Meng * implement a victim bit loop like on VLV.
34738ad43e4SBin Meng */
34838ad43e4SBin Meng errors = hte_rw_data_cmp(mrc_params, addr, HTE_LOOP_CNT,
34938ad43e4SBin Meng HTE_LFSR_VICTIM_SEED, HTE_LFSR_AGRESSOR_SEED,
35038ad43e4SBin Meng victim_bit, first_run);
35138ad43e4SBin Meng
35238ad43e4SBin Meng LEAVEFN();
35338ad43e4SBin Meng
35438ad43e4SBin Meng return errors;
35538ad43e4SBin Meng }
35638ad43e4SBin Meng
35738ad43e4SBin Meng /**
35838ad43e4SBin Meng * Execute a basic single-cache-line memory write or read.
35938ad43e4SBin Meng * This is just for receive enable / fine write-levelling purpose.
36038ad43e4SBin Meng *
36138ad43e4SBin Meng * @addr: memory adress being tested (must hit specific channel/rank)
36238ad43e4SBin Meng * @first_run: if set then the HTE registers are configured, otherwise it is
36338ad43e4SBin Meng * assumed configuration is done and we just re-run the test
36438ad43e4SBin Meng * @is_write: when non-zero memory write operation executed, otherwise read
36538ad43e4SBin Meng */
hte_mem_op(u32 addr,u8 first_run,u8 is_write)36638ad43e4SBin Meng void hte_mem_op(u32 addr, u8 first_run, u8 is_write)
36738ad43e4SBin Meng {
36838ad43e4SBin Meng u32 offset;
36938ad43e4SBin Meng u32 tmp;
37038ad43e4SBin Meng
37138ad43e4SBin Meng hte_enable_all_errors();
37238ad43e4SBin Meng hte_clear_error_regs();
37338ad43e4SBin Meng
37438ad43e4SBin Meng if (first_run) {
37538ad43e4SBin Meng tmp = is_write ? 0x01110021 : 0x01010021;
37638ad43e4SBin Meng msg_port_write(HTE, 0x00020020, tmp);
37738ad43e4SBin Meng
37838ad43e4SBin Meng msg_port_write(HTE, 0x00020021, 0x06000000);
37938ad43e4SBin Meng msg_port_write(HTE, 0x00020022, addr >> 6);
38038ad43e4SBin Meng msg_port_write(HTE, 0x00020062, 0x00800015);
381312cc39eSBin Meng msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
382312cc39eSBin Meng msg_port_write(HTE, 0x00020064, 0xcccccccc);
383312cc39eSBin Meng msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
38438ad43e4SBin Meng msg_port_write(HTE, 0x00020061, 0x00030008);
38538ad43e4SBin Meng
386312cc39eSBin Meng for (offset = 0x80; offset <= 0x8f; offset++)
387312cc39eSBin Meng msg_port_write(HTE, offset, 0xc33c0000);
38838ad43e4SBin Meng }
38938ad43e4SBin Meng
390312cc39eSBin Meng msg_port_write(HTE, 0x000200a1, 0xffff1000);
39138ad43e4SBin Meng msg_port_write(HTE, 0x00020011, 0x00011000);
39238ad43e4SBin Meng msg_port_write(HTE, 0x00020011, 0x00011100);
39338ad43e4SBin Meng
39438ad43e4SBin Meng hte_wait_for_complete();
39538ad43e4SBin Meng }
396