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/openbmc/linux/include/linux/
H A Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * enum pwm_polarity - polarity of a PWM signal
13 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
15 * period
16 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
18 * period
26 * struct pwm_args - board-dependent PWM arguments
27 * @period: reference period
30 * This structure describes board-dependent arguments attached to a PWM
31 * device. These arguments are usually retrieved from the PWM lookup table or
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/openbmc/linux/drivers/pwm/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2011-2012 Avionic Design GmbH
12 #include <linux/pwm.h>
21 #include <dt-bindings/pwm/pwm.h>
24 #include <trace/events/pwm.h>
46 return -ENOSPC; in alloc_pwms()
56 bitmap_clear(allocated_pwms, chip->base, chip->npwm); in free_pwms()
58 kfree(chip->pwms); in free_pwms()
59 chip->pwms = NULL; in free_pwms()
72 const char *chip_name = dev_name(chip->dev); in pwmchip_find_by_name()
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H A Dpwm-visconti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti pulse-width-modulation controller driver
5 * Copyright (c) 2020 - 2021 TOSHIBA CORPORATION
6 * Copyright (c) 2020 - 2021 Toshiba Electronic Devices & Storage Corporation
11 * - The fixed input clock is running at 1 MHz and is divided by either 1,
13 * - When the settings of the PWM are modified, the new values are shadowed
15 * running period is completed. This way the hardware switches atomically
17 * - Disabling the hardware completes the currently running period and keeps
26 #include <linux/pwm.h>
46 static int visconti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in visconti_pwm_apply() argument
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H A Dpwm-microchip-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11 * - If the IP block is configured without "shadow registers", all register
17 * As setting the period/duty cycle takes 4 register writes, there is a window
18 * in which this races against the start of a new period.
19 * - The IP block has no concept of a duty cycle, only rising/falling edges of
23 * period. Therefore to get a 0% waveform, the output is set the max high/low
25 * If the duty cycle is 0%, and the requested period is less than the
26 * available period resolution, this will manifest as a ~100% waveform (with
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H A Dpwm-jz4740.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
40 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
41 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2); in jz4740_pwm_can_use_chn()
43 device_property_read_u32(jz->chip.dev->parent, in jz4740_pwm_can_use_chn()
44 "ingenic,pwm-channels-mask", in jz4740_pwm_can_use_chn()
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H A Dpwm-omap-dmtimer.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
15 * reloaded with the load value and the pwm output goes up.
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
24 * a period with mixed settings. Especially when period/duty_cyle
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
27 * - period for current cycle = current_period + new period
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H A Dpwm-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pwm.h>
17 #define PWM_MODE 0x80 /* set timer in PWM mode */
21 #define PERIOD(x) (((x) * 0x10) + 0x10) macro
38 static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in bcm2835_pwm_request() argument
43 value = readl(pc->base + PWM_CONTROL); in bcm2835_pwm_request()
44 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
46 writel(value, pc->base + PWM_CONTROL); in bcm2835_pwm_request()
51 static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) in bcm2835_pwm_free() argument
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H A Dpwm-fsl-ftm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale FlexTimer Module (FTM) PWM Driver
5 * Copyright 2012-2013 Freescale Semiconductor, Inc.
17 #include <linux/pwm.h>
47 /* This value is valid iff a pwm is running */
48 struct fsl_pwm_periodcfg period; member
65 regmap_read(fpc->regmap, FTM_FMS, &val); in ftm_clear_write_protection()
67 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS); in ftm_clear_write_protection()
72 regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN); in ftm_set_write_protection()
78 if (a->clk_select != b->clk_select) in fsl_pwm_periodcfg_are_equal()
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H A Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
29 #include <linux/pwm.h>
32 /* The following is global registers for PWM controller */
40 /* The following register is PWM channel related registers */
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H A Dpwm-imx-tpm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2019 NXP.
6 * - The TPM counter and period counter are shared between
7 * multiple channels, so all channels should use same period
9 * - Changes to polarity cannot be latched at the time of the
10 * next period start.
11 * - Changing period and duty cycle together isn't atomic,
12 * with the wrong timing it might happen that a period is
13 * produced with old duty cycle but new period settings.
24 #include <linux/pwm.h>
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H A Dpwm-imx27.c1 // SPDX-License-Identifier: GPL-2.0
3 * simple driver for PWM (Pulse Width Modulator) controller
5 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
8 * - When disabled the output is driven to 0 independent of the configured
22 #include <linux/pwm.h>
25 #define MX3_PWMCR 0x00 /* PWM Control Register */
26 #define MX3_PWMSR 0x04 /* PWM Status Register */
27 #define MX3_PWMSAR 0x0C /* PWM Sample Register */
28 #define MX3_PWMPR 0x10 /* PWM Period Register */
29 #define MX3_PWMCNR 0x14 /* PWM Counter Register */
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H A Dpwm-atmel-tcb.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/pwm.h>
36 unsigned div; /* PWM clock divider */
37 unsigned duty; /* PWM duty expressed in clk cycles */
38 unsigned period; /* PWM period expressed in clk cycles */ member
70 struct pwm_device *pwm) in atmel_tcb_pwm_request() argument
73 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm]; in atmel_tcb_pwm_request()
77 ret = clk_prepare_enable(tcbpwmc->clk); in atmel_tcb_pwm_request()
81 tcbpwm->duty = 0; in atmel_tcb_pwm_request()
82 tcbpwm->period = 0; in atmel_tcb_pwm_request()
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H A Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
9 * and the currently running period is not guaranteed to be completed
21 #include <linux/pwm.h>
47 #define PWM_PRD(prd) (((prd) - 1) << 16)
101 return readl(chip->base + offset); in sun4i_pwm_readl()
107 writel(val, chip->base + offset); in sun4i_pwm_writel()
111 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
119 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
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H A Dpwm-crc.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/pwm.h>
28 * struct crystalcove_pwm - Crystal Cove PWM controller
47 /* clk_div 1 - 128, maps to register values 0-127 */ in crc_pwm_calc_clk_div()
49 clk_div--; in crc_pwm_calc_clk_div()
54 static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in crc_pwm_apply() argument
58 struct device *dev = crc_pwm->chip.dev; in crc_pwm_apply()
61 if (state->period > PWM_MAX_PERIOD_NS) { in crc_pwm_apply()
62 dev_err(dev, "un-supported period_ns\n"); in crc_pwm_apply()
63 return -EINVAL; in crc_pwm_apply()
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H A Dpwm-renesas-tpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
18 #include <linux/pwm.h>
63 TPU_PIN_PWM, /* Pin is driven by PWM */
77 u16 period; member
94 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET in tpu_pwm_write()
95 + tpd->channel * TPU_CHANNEL_SIZE; in tpu_pwm_write()
103 static const char * const states[] = { "inactive", "PWM", "active" }; in tpu_pwm_set_pin()
105 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n", in tpu_pwm_set_pin()
106 tpd->channel, states[state]); in tpu_pwm_set_pin()
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H A Dpwm-dwc.c1 // SPDX-License-Identifier: GPL-2.0
3 * DesignWare PWM Controller driver
5 * Copyright (C) 2018-2020 Intel Corporation
12 * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low
22 #include <linux/pwm.h>
62 return readl(dwc->base + offset); in dwc_pwm_readl()
67 writel(value, dwc->base + offset); in dwc_pwm_writel()
70 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) in __dwc_pwm_set_enable() argument
74 reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
81 dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
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H A Dpwm-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
15 #include <linux/pwm.h>
42 unsigned long period; member
61 struct pwm_device *pwm, in rockchip_pwm_get_state() argument
65 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
71 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
75 ret = clk_enable(pc->clk); in rockchip_pwm_get_state()
79 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
81 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
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H A Dpwm-intel-lgm.c1 // SPDX-License-Identifier: GPL-2.0
6 * - The hardware supports fixed period & configures only 2-wire mode.
7 * - Supports normal polarity. Does not support changing polarity.
8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
9 * keep track of running period.
10 * - When duty cycle is changed, PWM output may be a mix of previous setting
11 * and new setting for the first period. From second period, the output is
13 * - It is a dedicated PWM fan controller. There are no other consumers for
14 * this PWM controller.
21 #include <linux/pwm.h>
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H A Dpwm-sifive.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
19 #include <linux/pwm.h>
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/openbmc/linux/drivers/clk/
H A Dclk-pwm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * PWM (mis)used as clock output
7 #include <linux/clk-provider.h>
12 #include <linux/pwm.h>
16 struct pwm_device *pwm; member
29 return pwm_enable(clk_pwm->pwm); in clk_pwm_prepare()
36 pwm_disable(clk_pwm->pwm); in clk_pwm_unprepare()
44 return clk_pwm->fixed_rate; in clk_pwm_recalc_rate()
52 pwm_get_state(clk_pwm->pwm, &state); in clk_pwm_get_duty_cycle()
54 duty->num = state.duty_cycle; in clk_pwm_get_duty_cycle()
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/openbmc/linux/Documentation/driver-api/
H A Dpwm.rst2 Pulse Width Modulation (PWM) interface
5 This provides an overview about the Linux PWM interface
9 the Linux PWM API (although they could). However, PWMs are often
12 this kind of flexibility the generic PWM API exists.
15 ----------------
17 Users of the legacy PWM API use unique IDs to refer to PWM devices.
19 Instead of referring to a PWM device via its unique ID, board setup code
20 should instead register a static mapping that can be used to match PWM
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
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/openbmc/linux/include/trace/events/
H A Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #define TRACE_SYSTEM pwm
8 #include <linux/pwm.h>
11 DECLARE_EVENT_CLASS(pwm,
13 TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err),
15 TP_ARGS(pwm, state, err),
18 __field(struct pwm_device *, pwm)
19 __field(u64, period)
27 __entry->pwm = pwm;
28 __entry->period = state->period;
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/openbmc/linux/drivers/input/misc/
H A Dpwm-beeper.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * PWM beeper driver
14 #include <linux/pwm.h>
20 struct pwm_device *pwm; member
23 unsigned long period; member
31 static int pwm_beeper_on(struct pwm_beeper *beeper, unsigned long period) in pwm_beeper_on() argument
36 pwm_get_state(beeper->pwm, &state); in pwm_beeper_on()
39 state.period = period; in pwm_beeper_on()
42 error = pwm_apply_might_sleep(beeper->pwm, &state); in pwm_beeper_on()
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/openbmc/linux/drivers/staging/greybus/
H A Dpwm.c1 // SPDX-License-Identifier: GPL-2.0
3 * PWM Greybus driver.
12 #include <linux/pwm.h>
19 u8 pwm_max; /* max pwm number */
34 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_PWM_COUNT, in gb_pwm_count_operation()
38 pwmc->pwm_max = response.count; in gb_pwm_count_operation()
49 if (which > pwmc->pwm_max) in gb_pwm_activate_operation()
50 return -EINVAL; in gb_pwm_activate_operation()
54 gbphy_dev = to_gbphy_dev(pwmc->chip.dev); in gb_pwm_activate_operation()
59 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_ACTIVATE, in gb_pwm_activate_operation()
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/openbmc/u-boot/drivers/pwm/
H A DKconfig2 bool "Enable support for pulse-width modulation devices (PWM)"
5 A pulse-width modulator emits a pulse of varying width and provides
7 is often used to control a voltage level. The more time the PWM
8 spends in the 'high' state, the higher the voltage. The PWM's
9 frequency/period can be controlled along with the proportion of that
13 bool "Enable support for the Exynos PWM"
16 This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It
17 supports a programmable period and duty cycle. A 32-bit counter is
22 bool "Enable support for the Rockchip PWM"
25 This PWM is found on RK3288 and other Rockchip SoCs. It supports a
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