1d80f8206SUwe Kleine-König // SPDX-License-Identifier: GPL-2.0
2d80f8206SUwe Kleine-König /*
3d80f8206SUwe Kleine-König * simple driver for PWM (Pulse Width Modulator) controller
4d80f8206SUwe Kleine-König *
5d80f8206SUwe Kleine-König * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
6f6960976SUwe Kleine-König *
7f6960976SUwe Kleine-König * Limitations:
8f6960976SUwe Kleine-König * - When disabled the output is driven to 0 independent of the configured
9f6960976SUwe Kleine-König * polarity.
10d80f8206SUwe Kleine-König */
11d80f8206SUwe Kleine-König
12d80f8206SUwe Kleine-König #include <linux/bitfield.h>
13d80f8206SUwe Kleine-König #include <linux/bitops.h>
14d80f8206SUwe Kleine-König #include <linux/clk.h>
15d80f8206SUwe Kleine-König #include <linux/delay.h>
16d80f8206SUwe Kleine-König #include <linux/err.h>
17d80f8206SUwe Kleine-König #include <linux/io.h>
18d80f8206SUwe Kleine-König #include <linux/kernel.h>
19d80f8206SUwe Kleine-König #include <linux/module.h>
20d80f8206SUwe Kleine-König #include <linux/of.h>
21d80f8206SUwe Kleine-König #include <linux/platform_device.h>
22d80f8206SUwe Kleine-König #include <linux/pwm.h>
23d80f8206SUwe Kleine-König #include <linux/slab.h>
24d80f8206SUwe Kleine-König
25d80f8206SUwe Kleine-König #define MX3_PWMCR 0x00 /* PWM Control Register */
26d80f8206SUwe Kleine-König #define MX3_PWMSR 0x04 /* PWM Status Register */
27d80f8206SUwe Kleine-König #define MX3_PWMSAR 0x0C /* PWM Sample Register */
28d80f8206SUwe Kleine-König #define MX3_PWMPR 0x10 /* PWM Period Register */
29d80f8206SUwe Kleine-König
30d80f8206SUwe Kleine-König #define MX3_PWMCR_FWM GENMASK(27, 26)
31d80f8206SUwe Kleine-König #define MX3_PWMCR_STOPEN BIT(25)
32d80f8206SUwe Kleine-König #define MX3_PWMCR_DOZEN BIT(24)
33d80f8206SUwe Kleine-König #define MX3_PWMCR_WAITEN BIT(23)
34d80f8206SUwe Kleine-König #define MX3_PWMCR_DBGEN BIT(22)
35d80f8206SUwe Kleine-König #define MX3_PWMCR_BCTR BIT(21)
36d80f8206SUwe Kleine-König #define MX3_PWMCR_HCTR BIT(20)
37d80f8206SUwe Kleine-König
38d80f8206SUwe Kleine-König #define MX3_PWMCR_POUTC GENMASK(19, 18)
39d80f8206SUwe Kleine-König #define MX3_PWMCR_POUTC_NORMAL 0
40d80f8206SUwe Kleine-König #define MX3_PWMCR_POUTC_INVERTED 1
41d80f8206SUwe Kleine-König #define MX3_PWMCR_POUTC_OFF 2
42d80f8206SUwe Kleine-König
43d80f8206SUwe Kleine-König #define MX3_PWMCR_CLKSRC GENMASK(17, 16)
44d80f8206SUwe Kleine-König #define MX3_PWMCR_CLKSRC_OFF 0
45d80f8206SUwe Kleine-König #define MX3_PWMCR_CLKSRC_IPG 1
46d80f8206SUwe Kleine-König #define MX3_PWMCR_CLKSRC_IPG_HIGH 2
47d80f8206SUwe Kleine-König #define MX3_PWMCR_CLKSRC_IPG_32K 3
48d80f8206SUwe Kleine-König
49d80f8206SUwe Kleine-König #define MX3_PWMCR_PRESCALER GENMASK(15, 4)
50d80f8206SUwe Kleine-König
51d80f8206SUwe Kleine-König #define MX3_PWMCR_SWR BIT(3)
52d80f8206SUwe Kleine-König
53d80f8206SUwe Kleine-König #define MX3_PWMCR_REPEAT GENMASK(2, 1)
54d80f8206SUwe Kleine-König #define MX3_PWMCR_REPEAT_1X 0
55d80f8206SUwe Kleine-König #define MX3_PWMCR_REPEAT_2X 1
56d80f8206SUwe Kleine-König #define MX3_PWMCR_REPEAT_4X 2
57d80f8206SUwe Kleine-König #define MX3_PWMCR_REPEAT_8X 3
58d80f8206SUwe Kleine-König
59d80f8206SUwe Kleine-König #define MX3_PWMCR_EN BIT(0)
60d80f8206SUwe Kleine-König
61d80f8206SUwe Kleine-König #define MX3_PWMSR_FWE BIT(6)
62d80f8206SUwe Kleine-König #define MX3_PWMSR_CMP BIT(5)
63d80f8206SUwe Kleine-König #define MX3_PWMSR_ROV BIT(4)
64d80f8206SUwe Kleine-König #define MX3_PWMSR_FE BIT(3)
65d80f8206SUwe Kleine-König
66d80f8206SUwe Kleine-König #define MX3_PWMSR_FIFOAV GENMASK(2, 0)
67d80f8206SUwe Kleine-König #define MX3_PWMSR_FIFOAV_EMPTY 0
68d80f8206SUwe Kleine-König #define MX3_PWMSR_FIFOAV_1WORD 1
69d80f8206SUwe Kleine-König #define MX3_PWMSR_FIFOAV_2WORDS 2
70d80f8206SUwe Kleine-König #define MX3_PWMSR_FIFOAV_3WORDS 3
71d80f8206SUwe Kleine-König #define MX3_PWMSR_FIFOAV_4WORDS 4
72d80f8206SUwe Kleine-König
73d80f8206SUwe Kleine-König #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
74d80f8206SUwe Kleine-König #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
75d80f8206SUwe Kleine-König (x)) + 1)
76d80f8206SUwe Kleine-König
77d80f8206SUwe Kleine-König #define MX3_PWM_SWR_LOOP 5
78d80f8206SUwe Kleine-König
79d80f8206SUwe Kleine-König /* PWMPR register value of 0xffff has the same effect as 0xfffe */
80d80f8206SUwe Kleine-König #define MX3_PWMPR_MAX 0xfffe
81d80f8206SUwe Kleine-König
82d80f8206SUwe Kleine-König struct pwm_imx27_chip {
83d80f8206SUwe Kleine-König struct clk *clk_ipg;
84d80f8206SUwe Kleine-König struct clk *clk_per;
85d80f8206SUwe Kleine-König void __iomem *mmio_base;
86d80f8206SUwe Kleine-König struct pwm_chip chip;
87a3597d6cSThierry Reding
88a3597d6cSThierry Reding /*
89a3597d6cSThierry Reding * The driver cannot read the current duty cycle from the hardware if
90a3597d6cSThierry Reding * the hardware is disabled. Cache the last programmed duty cycle
91a3597d6cSThierry Reding * value to return in that case.
92a3597d6cSThierry Reding */
93a3597d6cSThierry Reding unsigned int duty_cycle;
94d80f8206SUwe Kleine-König };
95d80f8206SUwe Kleine-König
96d80f8206SUwe Kleine-König #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
97d80f8206SUwe Kleine-König
pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip * imx)98aad4e530SUwe Kleine-König static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
99d80f8206SUwe Kleine-König {
100d80f8206SUwe Kleine-König int ret;
101d80f8206SUwe Kleine-König
102d80f8206SUwe Kleine-König ret = clk_prepare_enable(imx->clk_ipg);
103d80f8206SUwe Kleine-König if (ret)
104d80f8206SUwe Kleine-König return ret;
105d80f8206SUwe Kleine-König
106d80f8206SUwe Kleine-König ret = clk_prepare_enable(imx->clk_per);
107d80f8206SUwe Kleine-König if (ret) {
108d80f8206SUwe Kleine-König clk_disable_unprepare(imx->clk_ipg);
109d80f8206SUwe Kleine-König return ret;
110d80f8206SUwe Kleine-König }
111d80f8206SUwe Kleine-König
112d80f8206SUwe Kleine-König return 0;
113d80f8206SUwe Kleine-König }
114d80f8206SUwe Kleine-König
pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip * imx)115aad4e530SUwe Kleine-König static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
116d80f8206SUwe Kleine-König {
117d80f8206SUwe Kleine-König clk_disable_unprepare(imx->clk_per);
118d80f8206SUwe Kleine-König clk_disable_unprepare(imx->clk_ipg);
119d80f8206SUwe Kleine-König }
120d80f8206SUwe Kleine-König
pwm_imx27_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)1216c452cffSUwe Kleine-König static int pwm_imx27_get_state(struct pwm_chip *chip,
122d80f8206SUwe Kleine-König struct pwm_device *pwm, struct pwm_state *state)
123d80f8206SUwe Kleine-König {
124d80f8206SUwe Kleine-König struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
1257ca17b20SDan Carpenter u32 period, prescaler, pwm_clk, val;
126d80f8206SUwe Kleine-König u64 tmp;
1277ca17b20SDan Carpenter int ret;
128d80f8206SUwe Kleine-König
129aad4e530SUwe Kleine-König ret = pwm_imx27_clk_prepare_enable(imx);
130d80f8206SUwe Kleine-König if (ret < 0)
131*51b9f2fbSUwe Kleine-König return ret;
132d80f8206SUwe Kleine-König
133d80f8206SUwe Kleine-König val = readl(imx->mmio_base + MX3_PWMCR);
134d80f8206SUwe Kleine-König
135519ef9b5SUwe Kleine-König if (val & MX3_PWMCR_EN)
136d80f8206SUwe Kleine-König state->enabled = true;
137519ef9b5SUwe Kleine-König else
138d80f8206SUwe Kleine-König state->enabled = false;
139d80f8206SUwe Kleine-König
140d80f8206SUwe Kleine-König switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
141d80f8206SUwe Kleine-König case MX3_PWMCR_POUTC_NORMAL:
142d80f8206SUwe Kleine-König state->polarity = PWM_POLARITY_NORMAL;
143d80f8206SUwe Kleine-König break;
144d80f8206SUwe Kleine-König case MX3_PWMCR_POUTC_INVERTED:
145d80f8206SUwe Kleine-König state->polarity = PWM_POLARITY_INVERSED;
146d80f8206SUwe Kleine-König break;
147d80f8206SUwe Kleine-König default:
148d80f8206SUwe Kleine-König dev_warn(chip->dev, "can't set polarity, output disconnected");
149d80f8206SUwe Kleine-König }
150d80f8206SUwe Kleine-König
151d80f8206SUwe Kleine-König prescaler = MX3_PWMCR_PRESCALER_GET(val);
152d80f8206SUwe Kleine-König pwm_clk = clk_get_rate(imx->clk_per);
153d80f8206SUwe Kleine-König val = readl(imx->mmio_base + MX3_PWMPR);
154d80f8206SUwe Kleine-König period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
155d80f8206SUwe Kleine-König
156d80f8206SUwe Kleine-König /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
157aef1a379SUwe Kleine-König tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
158aef1a379SUwe Kleine-König state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
159d80f8206SUwe Kleine-König
160a3597d6cSThierry Reding /*
161a3597d6cSThierry Reding * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
162a3597d6cSThierry Reding * use the cached value.
163a3597d6cSThierry Reding */
164a3597d6cSThierry Reding if (state->enabled)
165d80f8206SUwe Kleine-König val = readl(imx->mmio_base + MX3_PWMSAR);
166a3597d6cSThierry Reding else
167a3597d6cSThierry Reding val = imx->duty_cycle;
168a3597d6cSThierry Reding
169aef1a379SUwe Kleine-König tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
170aef1a379SUwe Kleine-König state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
171d80f8206SUwe Kleine-König
172aad4e530SUwe Kleine-König pwm_imx27_clk_disable_unprepare(imx);
1736c452cffSUwe Kleine-König
1746c452cffSUwe Kleine-König return 0;
175d80f8206SUwe Kleine-König }
176d80f8206SUwe Kleine-König
pwm_imx27_sw_reset(struct pwm_chip * chip)177d80f8206SUwe Kleine-König static void pwm_imx27_sw_reset(struct pwm_chip *chip)
178d80f8206SUwe Kleine-König {
179d80f8206SUwe Kleine-König struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
180d80f8206SUwe Kleine-König struct device *dev = chip->dev;
181d80f8206SUwe Kleine-König int wait_count = 0;
182d80f8206SUwe Kleine-König u32 cr;
183d80f8206SUwe Kleine-König
184d80f8206SUwe Kleine-König writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
185d80f8206SUwe Kleine-König do {
186d80f8206SUwe Kleine-König usleep_range(200, 1000);
187d80f8206SUwe Kleine-König cr = readl(imx->mmio_base + MX3_PWMCR);
188d80f8206SUwe Kleine-König } while ((cr & MX3_PWMCR_SWR) &&
189d80f8206SUwe Kleine-König (wait_count++ < MX3_PWM_SWR_LOOP));
190d80f8206SUwe Kleine-König
191d80f8206SUwe Kleine-König if (cr & MX3_PWMCR_SWR)
192d80f8206SUwe Kleine-König dev_warn(dev, "software reset timeout\n");
193d80f8206SUwe Kleine-König }
194d80f8206SUwe Kleine-König
pwm_imx27_wait_fifo_slot(struct pwm_chip * chip,struct pwm_device * pwm)195d80f8206SUwe Kleine-König static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
196d80f8206SUwe Kleine-König struct pwm_device *pwm)
197d80f8206SUwe Kleine-König {
198d80f8206SUwe Kleine-König struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
199d80f8206SUwe Kleine-König struct device *dev = chip->dev;
200d80f8206SUwe Kleine-König unsigned int period_ms;
201d80f8206SUwe Kleine-König int fifoav;
202d80f8206SUwe Kleine-König u32 sr;
203d80f8206SUwe Kleine-König
204d80f8206SUwe Kleine-König sr = readl(imx->mmio_base + MX3_PWMSR);
205d80f8206SUwe Kleine-König fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
206d80f8206SUwe Kleine-König if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
2071689dcd4SGuru Das Srinagesh period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
208d80f8206SUwe Kleine-König NSEC_PER_MSEC);
209d80f8206SUwe Kleine-König msleep(period_ms);
210d80f8206SUwe Kleine-König
211d80f8206SUwe Kleine-König sr = readl(imx->mmio_base + MX3_PWMSR);
212d80f8206SUwe Kleine-König if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
213d80f8206SUwe Kleine-König dev_warn(dev, "there is no free FIFO slot\n");
214d80f8206SUwe Kleine-König }
215d80f8206SUwe Kleine-König }
216d80f8206SUwe Kleine-König
pwm_imx27_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)217d80f8206SUwe Kleine-König static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
21871523d18SUwe Kleine-König const struct pwm_state *state)
219d80f8206SUwe Kleine-König {
220d80f8206SUwe Kleine-König unsigned long period_cycles, duty_cycles, prescale;
221d80f8206SUwe Kleine-König struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
222d80f8206SUwe Kleine-König struct pwm_state cstate;
223d80f8206SUwe Kleine-König unsigned long long c;
224aef1a379SUwe Kleine-König unsigned long long clkrate;
225d80f8206SUwe Kleine-König int ret;
226d80f8206SUwe Kleine-König u32 cr;
227d80f8206SUwe Kleine-König
228d80f8206SUwe Kleine-König pwm_get_state(pwm, &cstate);
229d80f8206SUwe Kleine-König
230aef1a379SUwe Kleine-König clkrate = clk_get_rate(imx->clk_per);
231aef1a379SUwe Kleine-König c = clkrate * state->period;
232d80f8206SUwe Kleine-König
233aef1a379SUwe Kleine-König do_div(c, NSEC_PER_SEC);
234d80f8206SUwe Kleine-König period_cycles = c;
235d80f8206SUwe Kleine-König
236d80f8206SUwe Kleine-König prescale = period_cycles / 0x10000 + 1;
237d80f8206SUwe Kleine-König
238d80f8206SUwe Kleine-König period_cycles /= prescale;
239aef1a379SUwe Kleine-König c = clkrate * state->duty_cycle;
2401ce65396SUwe Kleine-König do_div(c, NSEC_PER_SEC);
241d80f8206SUwe Kleine-König duty_cycles = c;
2421ce65396SUwe Kleine-König duty_cycles /= prescale;
243d80f8206SUwe Kleine-König
244d80f8206SUwe Kleine-König /*
245bd88d319SThierry Reding * according to imx pwm RM, the real period value should be PERIOD
246bd88d319SThierry Reding * value in PWMPR plus 2.
247d80f8206SUwe Kleine-König */
248d80f8206SUwe Kleine-König if (period_cycles > 2)
249d80f8206SUwe Kleine-König period_cycles -= 2;
250d80f8206SUwe Kleine-König else
251d80f8206SUwe Kleine-König period_cycles = 0;
252d80f8206SUwe Kleine-König
253d80f8206SUwe Kleine-König /*
254bd88d319SThierry Reding * Wait for a free FIFO slot if the PWM is already enabled, and flush
255bd88d319SThierry Reding * the FIFO if the PWM was disabled and is about to be enabled.
256d80f8206SUwe Kleine-König */
257d80f8206SUwe Kleine-König if (cstate.enabled) {
258d80f8206SUwe Kleine-König pwm_imx27_wait_fifo_slot(chip, pwm);
259d80f8206SUwe Kleine-König } else {
260aad4e530SUwe Kleine-König ret = pwm_imx27_clk_prepare_enable(imx);
261d80f8206SUwe Kleine-König if (ret)
262d80f8206SUwe Kleine-König return ret;
263d80f8206SUwe Kleine-König
264d80f8206SUwe Kleine-König pwm_imx27_sw_reset(chip);
265d80f8206SUwe Kleine-König }
266d80f8206SUwe Kleine-König
267d80f8206SUwe Kleine-König writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
268d80f8206SUwe Kleine-König writel(period_cycles, imx->mmio_base + MX3_PWMPR);
269d80f8206SUwe Kleine-König
270a3597d6cSThierry Reding /*
271bd88d319SThierry Reding * Store the duty cycle for future reference in cases where the
272bd88d319SThierry Reding * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
273a3597d6cSThierry Reding */
274a3597d6cSThierry Reding imx->duty_cycle = duty_cycles;
275a3597d6cSThierry Reding
276d80f8206SUwe Kleine-König cr = MX3_PWMCR_PRESCALER_SET(prescale) |
277d80f8206SUwe Kleine-König MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
278d80f8206SUwe Kleine-König FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
279bd88d319SThierry Reding MX3_PWMCR_DBGEN;
280d80f8206SUwe Kleine-König
281d80f8206SUwe Kleine-König if (state->polarity == PWM_POLARITY_INVERSED)
282d80f8206SUwe Kleine-König cr |= FIELD_PREP(MX3_PWMCR_POUTC,
283d80f8206SUwe Kleine-König MX3_PWMCR_POUTC_INVERTED);
284d80f8206SUwe Kleine-König
285bd88d319SThierry Reding if (state->enabled)
286bd88d319SThierry Reding cr |= MX3_PWMCR_EN;
287d80f8206SUwe Kleine-König
288bd88d319SThierry Reding writel(cr, imx->mmio_base + MX3_PWMCR);
289bd88d319SThierry Reding
29015d4dbd6SUwe Kleine-König if (!state->enabled)
291aad4e530SUwe Kleine-König pwm_imx27_clk_disable_unprepare(imx);
292d80f8206SUwe Kleine-König
293d80f8206SUwe Kleine-König return 0;
294d80f8206SUwe Kleine-König }
295d80f8206SUwe Kleine-König
296d80f8206SUwe Kleine-König static const struct pwm_ops pwm_imx27_ops = {
297d80f8206SUwe Kleine-König .apply = pwm_imx27_apply,
298d80f8206SUwe Kleine-König .get_state = pwm_imx27_get_state,
299d80f8206SUwe Kleine-König .owner = THIS_MODULE,
300d80f8206SUwe Kleine-König };
301d80f8206SUwe Kleine-König
302d80f8206SUwe Kleine-König static const struct of_device_id pwm_imx27_dt_ids[] = {
303d80f8206SUwe Kleine-König { .compatible = "fsl,imx27-pwm", },
304d80f8206SUwe Kleine-König { /* sentinel */ }
305d80f8206SUwe Kleine-König };
306d80f8206SUwe Kleine-König MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
307d80f8206SUwe Kleine-König
pwm_imx27_probe(struct platform_device * pdev)308d80f8206SUwe Kleine-König static int pwm_imx27_probe(struct platform_device *pdev)
309d80f8206SUwe Kleine-König {
310d80f8206SUwe Kleine-König struct pwm_imx27_chip *imx;
3112cb5cd90SUwe Kleine-König int ret;
3122cb5cd90SUwe Kleine-König u32 pwmcr;
313d80f8206SUwe Kleine-König
314d80f8206SUwe Kleine-König imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
315d80f8206SUwe Kleine-König if (imx == NULL)
316d80f8206SUwe Kleine-König return -ENOMEM;
317d80f8206SUwe Kleine-König
318d80f8206SUwe Kleine-König imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
319d109d74cSAnson Huang if (IS_ERR(imx->clk_ipg))
320d109d74cSAnson Huang return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg),
321d109d74cSAnson Huang "getting ipg clock failed\n");
322d80f8206SUwe Kleine-König
323d80f8206SUwe Kleine-König imx->clk_per = devm_clk_get(&pdev->dev, "per");
324d109d74cSAnson Huang if (IS_ERR(imx->clk_per))
325d109d74cSAnson Huang return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per),
326d109d74cSAnson Huang "failed to get peripheral clock\n");
327d80f8206SUwe Kleine-König
328d80f8206SUwe Kleine-König imx->chip.ops = &pwm_imx27_ops;
329d80f8206SUwe Kleine-König imx->chip.dev = &pdev->dev;
330d80f8206SUwe Kleine-König imx->chip.npwm = 1;
331d80f8206SUwe Kleine-König
3321347c94fSAnson Huang imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
333d80f8206SUwe Kleine-König if (IS_ERR(imx->mmio_base))
334d80f8206SUwe Kleine-König return PTR_ERR(imx->mmio_base);
335d80f8206SUwe Kleine-König
3362cb5cd90SUwe Kleine-König ret = pwm_imx27_clk_prepare_enable(imx);
3372cb5cd90SUwe Kleine-König if (ret)
3382cb5cd90SUwe Kleine-König return ret;
3392cb5cd90SUwe Kleine-König
3402cb5cd90SUwe Kleine-König /* keep clks on if pwm is running */
3412cb5cd90SUwe Kleine-König pwmcr = readl(imx->mmio_base + MX3_PWMCR);
3422cb5cd90SUwe Kleine-König if (!(pwmcr & MX3_PWMCR_EN))
3432cb5cd90SUwe Kleine-König pwm_imx27_clk_disable_unprepare(imx);
3442cb5cd90SUwe Kleine-König
345acfdc203SUwe Kleine-König return devm_pwmchip_add(&pdev->dev, &imx->chip);
346d80f8206SUwe Kleine-König }
347d80f8206SUwe Kleine-König
348d80f8206SUwe Kleine-König static struct platform_driver imx_pwm_driver = {
349d80f8206SUwe Kleine-König .driver = {
350d80f8206SUwe Kleine-König .name = "pwm-imx27",
351d80f8206SUwe Kleine-König .of_match_table = pwm_imx27_dt_ids,
352d80f8206SUwe Kleine-König },
353d80f8206SUwe Kleine-König .probe = pwm_imx27_probe,
354d80f8206SUwe Kleine-König };
355d80f8206SUwe Kleine-König module_platform_driver(imx_pwm_driver);
356d80f8206SUwe Kleine-König
357d80f8206SUwe Kleine-König MODULE_LICENSE("GPL v2");
358d80f8206SUwe Kleine-König MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
359