Lines Matching +full:pwm +full:- +full:period
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
29 #include <linux/pwm.h>
32 /* The following is global registers for PWM controller */
40 /* The following register is PWM channel related registers */
50 /* The following registers for PWM v1 */
55 /* The following registers for PWM v2 */
64 u8 period; member
87 * the end of the currently running period. When such an update is
88 * pending we delay disabling the PWM until the new configuration is
108 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
114 writel_relaxed(val, chip->base + offset); in atmel_pwm_writel()
137 * Each channel that has its bit in ISR set started a new period since in atmel_pwm_update_pending()
144 chip->update_pending &= ~isr; in atmel_pwm_update_pending()
149 spin_lock(&chip->lock); in atmel_pwm_set_pending()
157 chip->update_pending |= (1 << ch); in atmel_pwm_set_pending()
159 spin_unlock(&chip->lock); in atmel_pwm_set_pending()
166 spin_lock(&chip->lock); in atmel_pwm_test_pending()
168 if (chip->update_pending & (1 << ch)) { in atmel_pwm_test_pending()
171 if (chip->update_pending & (1 << ch)) in atmel_pwm_test_pending()
175 spin_unlock(&chip->lock); in atmel_pwm_test_pending()
189 return ret ? -ETIMEDOUT : 0; in atmel_pwm_wait_nonpending()
198 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres()
201 /* Calculate the period cycles and prescale value */ in atmel_pwm_calculate_cprd_and_pres()
206 * The register for the period length is cfg.period_bits bits wide. in atmel_pwm_calculate_cprd_and_pres()
210 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits; in atmel_pwm_calculate_cprd_and_pres()
213 dev_err(chip->dev, "pres exceeds the maximum value\n"); in atmel_pwm_calculate_cprd_and_pres()
214 return -EINVAL; in atmel_pwm_calculate_cprd_and_pres()
231 unsigned long long cycles = state->duty_cycle; in atmel_pwm_calculate_cdty()
236 *cdty = cprd - cycles; in atmel_pwm_calculate_cdty()
239 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_update_cdty() argument
245 if (atmel_pwm->data->regs.duty_upd == in atmel_pwm_update_cdty()
246 atmel_pwm->data->regs.period_upd) { in atmel_pwm_update_cdty()
247 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
249 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
252 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
253 atmel_pwm->data->regs.duty_upd, cdty); in atmel_pwm_update_cdty()
254 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm); in atmel_pwm_update_cdty()
258 struct pwm_device *pwm, in atmel_pwm_set_cprd_cdty() argument
263 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
264 atmel_pwm->data->regs.duty, cdty); in atmel_pwm_set_cprd_cdty()
265 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
266 atmel_pwm->data->regs.period, cprd); in atmel_pwm_set_cprd_cdty()
269 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_disable() argument
275 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); in atmel_pwm_disable()
277 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
280 * Wait for the PWM channel disable operation to be effective before in atmel_pwm_disable()
285 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
290 clk_disable(atmel_pwm->clk); in atmel_pwm_disable()
293 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_apply() argument
302 pwm_get_state(pwm, &cstate); in atmel_pwm_apply()
304 if (state->enabled) { in atmel_pwm_apply()
305 unsigned long clkrate = clk_get_rate(atmel_pwm->clk); in atmel_pwm_apply()
308 cstate.polarity == state->polarity && in atmel_pwm_apply()
309 cstate.period == state->period) { in atmel_pwm_apply()
310 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
312 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_apply()
313 atmel_pwm->data->regs.period); in atmel_pwm_apply()
317 atmel_pwm_update_cdty(chip, pwm, cdty); in atmel_pwm_apply()
324 dev_err(chip->dev, in atmel_pwm_apply()
332 atmel_pwm_disable(chip, pwm, false); in atmel_pwm_apply()
334 ret = clk_enable(atmel_pwm->clk); in atmel_pwm_apply()
336 dev_err(chip->dev, "failed to enable clock\n"); in atmel_pwm_apply()
342 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
344 if (state->polarity == PWM_POLARITY_NORMAL) in atmel_pwm_apply()
348 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_apply()
349 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty); in atmel_pwm_apply()
350 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm); in atmel_pwm_apply()
352 atmel_pwm_disable(chip, pwm, true); in atmel_pwm_apply()
358 static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_get_state() argument
365 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_get_state()
367 if (sr & (1 << pwm->hwpwm)) { in atmel_pwm_get_state()
368 unsigned long rate = clk_get_rate(atmel_pwm->clk); in atmel_pwm_get_state()
374 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_get_state()
375 atmel_pwm->data->regs.period); in atmel_pwm_get_state()
378 state->period = DIV64_U64_ROUND_UP(tmp, rate); in atmel_pwm_get_state()
381 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); in atmel_pwm_get_state()
383 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_get_state()
384 atmel_pwm->data->regs.duty); in atmel_pwm_get_state()
385 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC; in atmel_pwm_get_state()
387 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate); in atmel_pwm_get_state()
389 state->enabled = true; in atmel_pwm_get_state()
391 state->enabled = false; in atmel_pwm_get_state()
395 state->polarity = PWM_POLARITY_INVERSED; in atmel_pwm_get_state()
397 state->polarity = PWM_POLARITY_NORMAL; in atmel_pwm_get_state()
410 .period = PWMV1_CPRD,
416 /* 16 bits to keep period and duty. */
423 .period = PWMV2_CPRD,
429 /* 16 bits to keep period and duty. */
436 .period = PWMV1_CPRD,
442 /* 32 bits to keep period and duty. */
449 .compatible = "atmel,at91sam9rl-pwm",
452 .compatible = "atmel,sama5d3-pwm",
455 .compatible = "atmel,sama5d2-pwm",
458 .compatible = "microchip,sam9x60-pwm",
476 cnt = bitmap_weight(&sr, atmel_pwm->chip.npwm); in atmel_pwm_enable_clk_if_on()
482 ret = clk_enable(atmel_pwm->clk); in atmel_pwm_enable_clk_if_on()
484 dev_err(atmel_pwm->chip.dev, in atmel_pwm_enable_clk_if_on()
485 "failed to enable clock for pwm %pe\n", in atmel_pwm_enable_clk_if_on()
496 while (cnt--) in atmel_pwm_enable_clk_if_on()
497 clk_disable(atmel_pwm->clk); in atmel_pwm_enable_clk_if_on()
507 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL); in atmel_pwm_probe()
509 return -ENOMEM; in atmel_pwm_probe()
511 atmel_pwm->data = of_device_get_match_data(&pdev->dev); in atmel_pwm_probe()
513 atmel_pwm->update_pending = 0; in atmel_pwm_probe()
514 spin_lock_init(&atmel_pwm->lock); in atmel_pwm_probe()
516 atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0); in atmel_pwm_probe()
517 if (IS_ERR(atmel_pwm->base)) in atmel_pwm_probe()
518 return PTR_ERR(atmel_pwm->base); in atmel_pwm_probe()
520 atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL); in atmel_pwm_probe()
521 if (IS_ERR(atmel_pwm->clk)) in atmel_pwm_probe()
522 return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk), in atmel_pwm_probe()
523 "failed to get prepared PWM clock\n"); in atmel_pwm_probe()
525 atmel_pwm->chip.dev = &pdev->dev; in atmel_pwm_probe()
526 atmel_pwm->chip.ops = &atmel_pwm_ops; in atmel_pwm_probe()
527 atmel_pwm->chip.npwm = 4; in atmel_pwm_probe()
533 ret = devm_pwmchip_add(&pdev->dev, &atmel_pwm->chip); in atmel_pwm_probe()
535 dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); in atmel_pwm_probe()
549 .name = "atmel-pwm",
556 MODULE_ALIAS("platform:atmel-pwm");
558 MODULE_DESCRIPTION("Atmel PWM driver");