Lines Matching +full:pwm +full:- +full:period
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11 * - If the IP block is configured without "shadow registers", all register
17 * As setting the period/duty cycle takes 4 register writes, there is a window
18 * in which this races against the start of a new period.
19 * - The IP block has no concept of a duty cycle, only rising/falling edges of
23 * period. Therefore to get a 0% waveform, the output is set the max high/low
25 * If the duty cycle is 0%, and the requested period is less than the
26 * available period resolution, this will manifest as a ~100% waveform (with
28 * - The PWM period is set for the whole IP block not per channel. The driver
29 * will only change the period if no other PWM output is enabled.
42 #include <linux/pwm.h>
60 struct mutex lock; /* protects the shared period */
71 static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, in mchp_core_pwm_enable() argument
72 bool enable, u64 period) in mchp_core_pwm_enable() argument
79 * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg in mchp_core_pwm_enable()
82 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); in mchp_core_pwm_enable()
83 shift = pwm->hwpwm & 7; in mchp_core_pwm_enable()
85 channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset); in mchp_core_pwm_enable()
89 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset); in mchp_core_pwm_enable()
90 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm); in mchp_core_pwm_enable()
91 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm; in mchp_core_pwm_enable()
95 * applied to the waveform at the beginning of the next period. in mchp_core_pwm_enable()
96 * This is a NO-OP if the channel does not have shadow registers. in mchp_core_pwm_enable()
98 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) in mchp_core_pwm_enable()
99 mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period); in mchp_core_pwm_enable()
106 * If a shadow register is used for this PWM channel, and iff there is in mchp_core_pwm_wait_for_sync_update()
110 * once the current period has ended. in mchp_core_pwm_wait_for_sync_update()
113 if (mchp_core_pwm->sync_update_mask & (1 << channel)) { in mchp_core_pwm_wait_for_sync_update()
118 remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp, in mchp_core_pwm_wait_for_sync_update()
140 * Calculate the duty cycle in multiples of the prescaled period: in mchp_core_pwm_calc_duty()
146 duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp); in mchp_core_pwm_calc_duty()
151 static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm, in mchp_core_pwm_apply_duty() argument
168 if (state->polarity == PWM_POLARITY_INVERSED) { in mchp_core_pwm_apply_duty()
181 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
182 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
191 * Calculate the period cycles and prescale values. in mchp_core_pwm_calc_period()
192 * The registers are each 8 bits wide & multiplied to compute the period in mchp_core_pwm_calc_period()
195 * period = ------------------------------------- in mchp_core_pwm_calc_period()
197 * so the maximum period that can be generated is 0x10000 times the in mchp_core_pwm_calc_period()
198 * period of the input clock. in mchp_core_pwm_calc_period()
202 * of the clock period attainable is (0xff + 1) * (0xfe + 1) = 0xff00 in mchp_core_pwm_calc_period()
207 * It's therefore not possible to set a period lower than 1/clk_rate, so in mchp_core_pwm_calc_period()
208 * if tmp is 0, abort. Without aborting, we will set a period that is in mchp_core_pwm_calc_period()
210 * neg-/pos-edge issue described in the limitations. in mchp_core_pwm_calc_period()
212 tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC); in mchp_core_pwm_calc_period()
224 * is as finegrain as possible, while also keeping the period less than in mchp_core_pwm_calc_period()
231 * Integer division will ensure a round down, so the period will thereby in mchp_core_pwm_calc_period()
238 * As we must produce a period less than that requested, and for the in mchp_core_pwm_calc_period()
243 return -EINVAL; in mchp_core_pwm_calc_period()
249 * period * clk_rate in mchp_core_pwm_calc_period()
250 * prescale = ------------------------- - 1 in mchp_core_pwm_calc_period()
254 * period * clk_rate in mchp_core_pwm_calc_period()
255 * ------------------- was precomputed as `tmp` in mchp_core_pwm_calc_period()
258 *prescale = ((u16)tmp) / (MCHPCOREPWM_PERIOD_STEPS_MAX + 1) - 1; in mchp_core_pwm_calc_period()
262 * period * clk_rate in mchp_core_pwm_calc_period()
263 * period_steps = ----------------------------- - 1 in mchp_core_pwm_calc_period()
274 static int mchp_core_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, in mchp_core_pwm_apply_locked() argument
284 if (!state->enabled) { in mchp_core_pwm_apply_locked()
285 mchp_core_pwm_enable(chip, pwm, false, pwm->state.period); in mchp_core_pwm_apply_locked()
294 clk_rate = clk_get_rate(mchp_core_pwm->clk); in mchp_core_pwm_apply_locked()
296 return -EINVAL; in mchp_core_pwm_apply_locked()
306 * As all the channels share the same period, do not allow it to be in mchp_core_pwm_apply_locked()
308 * If the period is locked, it may not be possible to use a period in mchp_core_pwm_apply_locked()
311 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); in mchp_core_pwm_apply_locked()
317 hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); in mchp_core_pwm_apply_locked()
318 hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); in mchp_core_pwm_apply_locked()
322 return -EINVAL; in mchp_core_pwm_apply_locked()
329 * The period is locked and we cannot change this, so we abort. in mchp_core_pwm_apply_locked()
332 return -EINVAL; in mchp_core_pwm_apply_locked()
341 * Because the period is not per channel, it is possible that the in mchp_core_pwm_apply_locked()
342 * requested duty cycle is longer than the period, in which case cap it in mchp_core_pwm_apply_locked()
343 * to the period, IOW a 100% duty cycle. in mchp_core_pwm_apply_locked()
349 writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); in mchp_core_pwm_apply_locked()
350 writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD); in mchp_core_pwm_apply_locked()
353 mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps); in mchp_core_pwm_apply_locked()
355 mchp_core_pwm_enable(chip, pwm, true, pwm->state.period); in mchp_core_pwm_apply_locked()
360 static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in mchp_core_pwm_apply() argument
366 mutex_lock(&mchp_core_pwm->lock); in mchp_core_pwm_apply()
368 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_apply()
370 ret = mchp_core_pwm_apply_locked(chip, pwm, state); in mchp_core_pwm_apply()
372 mutex_unlock(&mchp_core_pwm->lock); in mchp_core_pwm_apply()
377 static int mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in mchp_core_pwm_get_state() argument
385 mutex_lock(&mchp_core_pwm->lock); in mchp_core_pwm_get_state()
387 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_get_state()
389 if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm)) in mchp_core_pwm_get_state()
390 state->enabled = true; in mchp_core_pwm_get_state()
392 state->enabled = false; in mchp_core_pwm_get_state()
394 rate = clk_get_rate(mchp_core_pwm->clk); in mchp_core_pwm_get_state()
397 * Calculating the period: in mchp_core_pwm_get_state()
398 * The registers are each 8 bits wide & multiplied to compute the period in mchp_core_pwm_get_state()
401 * period = ------------------------------------- in mchp_core_pwm_get_state()
409 prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); in mchp_core_pwm_get_state()
410 period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); in mchp_core_pwm_get_state()
412 state->period = (period_steps + 1) * (prescale + 1); in mchp_core_pwm_get_state()
413 state->period *= NSEC_PER_SEC; in mchp_core_pwm_get_state()
414 state->period = DIV64_U64_ROUND_UP(state->period, rate); in mchp_core_pwm_get_state()
416 posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); in mchp_core_pwm_get_state()
417 negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); in mchp_core_pwm_get_state()
419 mutex_unlock(&mchp_core_pwm->lock); in mchp_core_pwm_get_state()
422 state->duty_cycle = state->period; in mchp_core_pwm_get_state()
423 state->period *= 2; in mchp_core_pwm_get_state()
425 duty_steps = abs((s16)posedge - (s16)negedge); in mchp_core_pwm_get_state()
426 state->duty_cycle = duty_steps * (prescale + 1) * NSEC_PER_SEC; in mchp_core_pwm_get_state()
427 state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle, rate); in mchp_core_pwm_get_state()
430 state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; in mchp_core_pwm_get_state()
443 .compatible = "microchip,corepwm-rtl-v4",
455 mchp_core_pwm = devm_kzalloc(&pdev->dev, sizeof(*mchp_core_pwm), GFP_KERNEL); in mchp_core_pwm_probe()
457 return -ENOMEM; in mchp_core_pwm_probe()
459 mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); in mchp_core_pwm_probe()
460 if (IS_ERR(mchp_core_pwm->base)) in mchp_core_pwm_probe()
461 return PTR_ERR(mchp_core_pwm->base); in mchp_core_pwm_probe()
463 mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL); in mchp_core_pwm_probe()
464 if (IS_ERR(mchp_core_pwm->clk)) in mchp_core_pwm_probe()
465 return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk), in mchp_core_pwm_probe()
466 "failed to get PWM clock\n"); in mchp_core_pwm_probe()
468 if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask", in mchp_core_pwm_probe()
469 &mchp_core_pwm->sync_update_mask)) in mchp_core_pwm_probe()
470 mchp_core_pwm->sync_update_mask = 0; in mchp_core_pwm_probe()
472 mutex_init(&mchp_core_pwm->lock); in mchp_core_pwm_probe()
474 mchp_core_pwm->chip.dev = &pdev->dev; in mchp_core_pwm_probe()
475 mchp_core_pwm->chip.ops = &mchp_core_pwm_ops; in mchp_core_pwm_probe()
476 mchp_core_pwm->chip.npwm = 16; in mchp_core_pwm_probe()
478 mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0)); in mchp_core_pwm_probe()
479 mchp_core_pwm->channel_enabled |= in mchp_core_pwm_probe()
480 readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8; in mchp_core_pwm_probe()
486 writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD); in mchp_core_pwm_probe()
487 mchp_core_pwm->update_timestamp = ktime_get(); in mchp_core_pwm_probe()
489 ret = devm_pwmchip_add(&pdev->dev, &mchp_core_pwm->chip); in mchp_core_pwm_probe()
491 return dev_err_probe(&pdev->dev, ret, "Failed to add pwmchip\n"); in mchp_core_pwm_probe()
498 .name = "mchp-core-pwm",