/openbmc/linux/include/linux/soc/mediatek/ |
H A D | mtk-cmdq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 11 #include <linux/mailbox/mtk-cmdq-mailbox.h> 33 * cmdq_dev_get_client_reg() - parse cmdq client reg from the device 48 * cmdq_mbox_create() - create CMDQ mailbox client and channel 57 * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel 63 * cmdq_pkt_create() - create a CMDQ packet 72 * cmdq_pkt_destroy() - destroy the CMDQ packet 78 * cmdq_pkt_write() - append write command to the CMDQ packet 89 * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet 102 * cmdq_pkt_read_s() - append read_s command to the CMDQ packet [all …]
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/openbmc/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt8192.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/clock/mt8192-clk.h> 9 #include <dt-bindings/gce/mt8192-gce.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/memory/mt8192-larb-port.h> 13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14 #include <dt-bindings/phy/phy.h> 15 #include <dt-bindings/power/mt8192-power.h> [all …]
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H A D | mt8195.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/clock/mt8195-clk.h> 9 #include <dt-bindings/gce/mt8195-gce.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/memory/mt8195-memory-port.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15 #include <dt-bindings/power/mt8195-power.h> [all …]
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H A D | mt8183.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 #include <dt-bindings/clock/mt8183-clk.h> 9 #include <dt-bindings/gce/mt8183-gce.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/memory/mt8183-larb-port.h> 13 #include <dt-bindings/power/mt8183-power.h> 14 #include <dt-bindings/reset/mt8183-resets.h> 15 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | mt8186.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 6 /dts-v1/; 7 #include <dt-bindings/clock/mt8186-clk.h> 8 #include <dt-bindings/gce/mt8186-gce.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/memory/mt8186-memory-port.h> 12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13 #include <dt-bindings/power/mt8186-power.h> [all …]
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H A D | mt8173.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/mt8173-clk.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/memory/mt8173-larb-port.h> 11 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/power/mt8173-power.h> 13 #include <dt-bindings/reset/mt8173-resets.h> 14 #include <dt-bindings/gce/mt8173-gce.h> 15 #include <dt-bindings/thermal/thermal.h> [all …]
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/openbmc/linux/drivers/mailbox/ |
H A D | mtk-cmdq-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <linux/clk-provider.h> 8 #include <linux/dma-mapping.h> 17 #include <linux/mailbox/mtk-cmdq-mailbox.h> 21 #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) 95 WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); in cmdq_sw_ddr_enable() 98 writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); in cmdq_sw_ddr_enable() 100 writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); in cmdq_sw_ddr_enable() 102 clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); in cmdq_sw_ddr_enable() 107 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); in cmdq_get_shift_pa() [all …]
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/openbmc/linux/drivers/gpu/drm/mediatek/ |
H A D | mtk_disp_aal.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/soc/mediatek/mtk-cmdq.h> 39 return clk_prepare_enable(aal->clk); in mtk_aal_clk_enable() 46 clk_disable_unprepare(aal->clk); in mtk_aal_clk_disable() 55 mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config() 56 mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config() 63 if (aal->data && aal->data->has_gamma) in mtk_aal_gamma_set() 64 mtk_gamma_set_common(aal->regs, state, false); in mtk_aal_gamma_set() 71 writel(AAL_EN, aal->regs + DISP_AAL_EN); in mtk_aal_start() 78 writel_relaxed(0x0, aal->regs + DISP_AAL_EN); in mtk_aal_stop() [all …]
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H A D | mtk_disp_color.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/soc/mediatek/mtk-cmdq.h> 22 #define DISP_COLOR_START(comp) ((comp)->data->color_offset) 34 * struct mtk_disp_color - DISP_COLOR driver structure 50 return clk_prepare_enable(color->clk); in mtk_color_clk_enable() 57 clk_disable_unprepare(color->clk); in mtk_color_clk_disable() 66 mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color)); in mtk_color_config() 67 mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); in mtk_color_config() 75 color->regs + DISP_COLOR_CFG_MAIN); in mtk_color_start() 76 writel(0x1, color->regs + DISP_COLOR_START(color)); in mtk_color_start() [all …]
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H A D | mtk_disp_gamma.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/soc/mediatek/mtk-cmdq.h> 34 * struct mtk_disp_gamma - DISP_GAMMA driver structure 47 return clk_prepare_enable(gamma->clk); in mtk_gamma_clk_enable() 54 clk_disable_unprepare(gamma->clk); in mtk_gamma_clk_disable() 65 if (state->gamma_lut) { in mtk_gamma_set_common() 70 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_gamma_set_common() 78 diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); in mtk_gamma_set_common() 79 diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); in mtk_gamma_set_common() 80 diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); in mtk_gamma_set_common() [all …]
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H A D | mtk_disp_ccorr.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/soc/mediatek/mtk-cmdq.h> 47 return clk_prepare_enable(ccorr->clk); in mtk_ccorr_clk_enable() 54 clk_disable_unprepare(ccorr->clk); in mtk_ccorr_clk_disable() 63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config() 65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config() 73 writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); in mtk_ccorr_start() 80 writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); in mtk_ccorr_stop() 92 /* identity value 0x100000000 -> 0x400(mt8183), */ in mtk_ctm_s31_32_to_s1_n() 93 /* identity value 0x100000000 -> 0x800(mt8192), */ in mtk_ctm_s31_32_to_s1_n() [all …]
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H A D | mtk_ethdr.c | 1 // SPDX-License-Identifier: GPL-2.0-only 14 #include <linux/soc/mediatek/mtk-cmdq.h> 15 #include <linux/soc/mediatek/mtk-mmsys.h> 106 priv->vblank_cb = vblank_cb; in mtk_ethdr_register_vblank_cb() 107 priv->vblank_cb_data = vblank_cb_data; in mtk_ethdr_register_vblank_cb() 114 priv->vblank_cb = NULL; in mtk_ethdr_unregister_vblank_cb() 115 priv->vblank_cb_data = NULL; in mtk_ethdr_unregister_vblank_cb() 122 writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN); in mtk_ethdr_enable_vblank() 129 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN); in mtk_ethdr_disable_vblank() 136 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA); in mtk_ethdr_irq_handler() [all …]
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H A D | mtk_mdp_rdma.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 #include <linux/soc/mediatek/mtk-cmdq.h> 155 FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg, in mtk_mdp_rdma_fifo_config() 156 priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN | in mtk_mdp_rdma_fifo_config() 165 mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, in mtk_mdp_rdma_start() 166 priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); in mtk_mdp_rdma_start() 173 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, in mtk_mdp_rdma_stop() 174 priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE); in mtk_mdp_rdma_stop() 175 mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); in mtk_mdp_rdma_stop() 176 mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); in mtk_mdp_rdma_stop() [all …]
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H A D | mtk_disp_merge.c | 1 // SPDX-License-Identifier: GPL-2.0 11 #include <linux/soc/mediatek/mtk-cmdq.h> 87 if (priv->mute_support) in mtk_merge_start_cmdq() 88 mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs, in mtk_merge_start_cmdq() 91 mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, in mtk_merge_start_cmdq() 99 if (priv->mute_support) in mtk_merge_stop_cmdq() 100 mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs, in mtk_merge_stop_cmdq() 103 mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, in mtk_merge_stop_cmdq() 106 if (!cmdq_pkt && priv->async_clk) in mtk_merge_stop_cmdq() 107 reset_control_reset(priv->reset_ctl); in mtk_merge_stop_cmdq() [all …]
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H A D | mtk_drm_crtc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/dma-mapping.h> 11 #include <linux/soc/mediatek/mtk-cmdq.h> 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 29 * struct mtk_drm_crtc - MediaTek specific crtc structure. 95 struct drm_crtc *crtc = &mtk_crtc->base; in mtk_drm_crtc_finish_page_flip() 98 if (mtk_crtc->event) { in mtk_drm_crtc_finish_page_flip() 99 spin_lock_irqsave(&crtc->dev->event_lock, flags); in mtk_drm_crtc_finish_page_flip() 100 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); in mtk_drm_crtc_finish_page_flip() [all …]
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H A D | mtk_disp_rdma.c | 1 // SPDX-License-Identifier: GPL-2.0-only 14 #include <linux/soc/mediatek/mtk-cmdq.h> 52 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) 78 * struct mtk_disp_rdma - DISP_RDMA driver structure 96 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); in mtk_disp_rdma_irq_handler() 98 if (!priv->vblank_cb) in mtk_disp_rdma_irq_handler() 101 priv->vblank_cb(priv->vblank_cb_data); in mtk_disp_rdma_irq_handler() 110 unsigned int tmp = readl(rdma->regs + reg); in rdma_update_bits() 113 writel(tmp, rdma->regs + reg); in rdma_update_bits() 122 rdma->vblank_cb = vblank_cb; in mtk_rdma_register_vblank_cb() [all …]
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H A D | mtk_drm_ddp_comp.c | 1 // SPDX-License-Identifier: GPL-2.0-only 14 #include <linux/soc/mediatek/mtk-cmdq.h> 75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write() 76 cmdq_reg->offset + offset, value); in mtk_ddp_write() 88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_relaxed() 89 cmdq_reg->offset + offset, value); in mtk_ddp_write_relaxed() 101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_mask() 102 cmdq_reg->offset + offset, value, mask); in mtk_ddp_write_mask() 118 return clk_prepare_enable(priv->clk); in mtk_ddp_clk_enable() 125 clk_disable_unprepare(priv->clk); in mtk_ddp_clk_disable() [all …]
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H A D | mtk_disp_ovl.c | 1 // SPDX-License-Identifier: GPL-2.0-only 16 #include <linux/soc/mediatek/mtk-cmdq.h> 47 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) 48 #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) 49 #define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08) 62 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 64 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 120 * struct mtk_disp_ovl - DISP_OVL driver structure 139 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); in mtk_disp_ovl_irq_handler() 141 if (!priv->vblank_cb) in mtk_disp_ovl_irq_handler() [all …]
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/openbmc/linux/drivers/soc/mediatek/ |
H A D | mtk-cmdq-helper.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <linux/dma-mapping.h> 11 #include <linux/soc/mediatek/mtk-cmdq.h> 53 return -ENOENT; in cmdq_dev_get_client_reg() 55 err = of_parse_phandle_with_fixed_args(dev->of_node, in cmdq_dev_get_client_reg() 56 "mediatek,gce-client-reg", in cmdq_dev_get_client_reg() 60 "error %d can't parse gce-client-reg property (%d)", in cmdq_dev_get_client_reg() 66 client_reg->subsys = (u8)spec.args[0]; in cmdq_dev_get_client_reg() 67 client_reg->offset = (u16)spec.args[1]; in cmdq_dev_get_client_reg() 68 client_reg->size = (u16)spec.args[2]; in cmdq_dev_get_client_reg() [all …]
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H A D | mtk-mutex.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 14 #include <linux/soc/mediatek/mtk-cmdq.h> 598 * So that MUTEX can not only send a STREAM_DONE event to GCE 722 if (!mtx->mutex[i].claimed) { in mtk_mutex_get() 723 mtx->mutex[i].claimed = true; in mtk_mutex_get() 724 return &mtx->mutex[i]; in mtk_mutex_get() 727 return ERR_PTR(-EBUSY); in mtk_mutex_get() 734 mutex[mutex->id]); in mtk_mutex_put() [all …]
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H A D | mtk-mmsys.c | 1 // SPDX-License-Identifier: GPL-2.0-only 13 #include <linux/reset-controller.h> 14 #include <linux/soc/mediatek/mtk-mmsys.h> 16 #include "mtk-mmsys.h" 17 #include "mt8167-mmsys.h" 18 #include "mt8173-mmsys.h" 19 #include "mt8183-mmsys.h" 20 #include "mt8186-mmsys.h" 21 #include "mt8188-mmsys.h" 22 #include "mt8192-mmsys.h" [all …]
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/openbmc/linux/drivers/media/platform/mediatek/mdp3/ |
H A D | mtk-mdp3-comp.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 11 #include "mtk-mdp3-cfg.h" 12 #include "mtk-mdp3-comp.h" 13 #include "mtk-mdp3-core.h" 14 #include "mtk-mdp3-regs.h" 31 return ctx->comp->mdp_dev->mdp_data->mdp_cfg; in __get_plat_cfg() 39 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0); in get_comp_flag() 40 rsz1 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RSZ1); in get_comp_flag() 44 if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) in get_comp_flag() [all …]
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt8516.c | 1 // SPDX-License-Identifier: GPL-2.0 16 #include "clk-gate.h" 17 #include "clk-mtk.h" 19 #include <dt-bindings/clock/mt8516-clk.h> 583 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4), 664 { .compatible = "mediatek,mt8516-topckgen", .data = &topck_desc }, 665 { .compatible = "mediatek,mt8516-infracfg", .data = &infra_desc }, 674 .name = "clk-mt8516",
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H A D | clk-mt8167.c | 1 // SPDX-License-Identifier: GPL-2.0 16 #include "clk-gate.h" 17 #include "clk-mtk.h" 19 #include <dt-bindings/clock/mt8167-clk.h> 792 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4), 882 { .compatible = "mediatek,mt8167-topckgen", .data = &topck_desc }, 883 { .compatible = "mediatek,mt8167-infracfg", .data = &infra_desc }, 892 .name = "clk-mt8167",
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/openbmc/linux/ |
H A D | opengrok0.0.log | 1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz' 2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz' 3 2024-12-2 [all...] |