11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2119f5173SCK Hu /*
3119f5173SCK Hu * Copyright (c) 2015 MediaTek Inc.
4119f5173SCK Hu * Authors:
5119f5173SCK Hu * YT Shen <yt.shen@mediatek.com>
6119f5173SCK Hu * CK Hu <ck.hu@mediatek.com>
7119f5173SCK Hu */
8119f5173SCK Hu
9119f5173SCK Hu #include <linux/clk.h>
10119f5173SCK Hu #include <linux/of.h>
11119f5173SCK Hu #include <linux/of_address.h>
12119f5173SCK Hu #include <linux/of_platform.h>
13119f5173SCK Hu #include <linux/platform_device.h>
14d0afe37fSBibby Hsieh #include <linux/soc/mediatek/mtk-cmdq.h>
155aa8e764SStu Hsieh #include <drm/drm_print.h>
165aa8e764SStu Hsieh
171d33f13aSCK Hu #include "mtk_disp_drv.h"
18119f5173SCK Hu #include "mtk_drm_drv.h"
19119f5173SCK Hu #include "mtk_drm_plane.h"
20119f5173SCK Hu #include "mtk_drm_ddp_comp.h"
212f3f4ddaSBibby Hsieh #include "mtk_drm_crtc.h"
22119f5173SCK Hu
23119f5173SCK Hu
24aa0c3155Sjason-jh.lin #define DISP_REG_DITHER_EN 0x0000
25450aa87cSYongqiang Niu #define DITHER_EN BIT(0)
26aa0c3155Sjason-jh.lin #define DISP_REG_DITHER_CFG 0x0020
27450aa87cSYongqiang Niu #define DITHER_RELAY_MODE BIT(0)
2849629304SYongqiang Niu #define DITHER_ENGINE_EN BIT(1)
2972164364SBibby Hsieh #define DISP_DITHERING BIT(2)
3073d37247Sjason-jh.lin #define DISP_REG_DITHER_SIZE 0x0030
3173d37247Sjason-jh.lin #define DISP_REG_DITHER_5 0x0114
3273d37247Sjason-jh.lin #define DISP_REG_DITHER_7 0x011c
3373d37247Sjason-jh.lin #define DISP_REG_DITHER_15 0x013c
3472164364SBibby Hsieh #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
3572164364SBibby Hsieh #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
3672164364SBibby Hsieh #define DITHER_NEW_BIT_MODE BIT(0)
3773d37247Sjason-jh.lin #define DISP_REG_DITHER_16 0x0140
3872164364SBibby Hsieh #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
3972164364SBibby Hsieh #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
4072164364SBibby Hsieh #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
4172164364SBibby Hsieh #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
4272164364SBibby Hsieh
43b7fb767bSjason-jh.lin #define DISP_REG_DSC_CON 0x0000
44b7fb767bSjason-jh.lin #define DSC_EN BIT(0)
45b7fb767bSjason-jh.lin #define DSC_DUAL_INOUT BIT(2)
46b7fb767bSjason-jh.lin #define DSC_BYPASS BIT(4)
47b7fb767bSjason-jh.lin #define DSC_UFOE_SEL BIT(16)
48b7fb767bSjason-jh.lin
4973d37247Sjason-jh.lin #define DISP_REG_OD_EN 0x0000
5073d37247Sjason-jh.lin #define DISP_REG_OD_CFG 0x0020
5173d37247Sjason-jh.lin #define OD_RELAYMODE BIT(0)
5273d37247Sjason-jh.lin #define DISP_REG_OD_SIZE 0x0030
5373d37247Sjason-jh.lin
54aa0c3155Sjason-jh.lin #define DISP_REG_POSTMASK_EN 0x0000
558c9f215aSYongqiang Niu #define POSTMASK_EN BIT(0)
56aa0c3155Sjason-jh.lin #define DISP_REG_POSTMASK_CFG 0x0020
578c9f215aSYongqiang Niu #define POSTMASK_RELAY_MODE BIT(0)
58aa0c3155Sjason-jh.lin #define DISP_REG_POSTMASK_SIZE 0x0030
598c9f215aSYongqiang Niu
6073d37247Sjason-jh.lin #define DISP_REG_UFO_START 0x0000
6173d37247Sjason-jh.lin #define UFO_BYPASS BIT(2)
6273d37247Sjason-jh.lin
63c0d36de8SCK Hu struct mtk_ddp_comp_dev {
64c0d36de8SCK Hu struct clk *clk;
653c87daefSCK Hu void __iomem *regs;
66616443caSCK Hu struct cmdq_client_reg cmdq_reg;
67c0d36de8SCK Hu };
68c0d36de8SCK Hu
mtk_ddp_write(struct cmdq_pkt * cmdq_pkt,unsigned int value,struct cmdq_client_reg * cmdq_reg,void __iomem * regs,unsigned int offset)69d0afe37fSBibby Hsieh void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
70616443caSCK Hu struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
71d0afe37fSBibby Hsieh unsigned int offset)
72d0afe37fSBibby Hsieh {
73d0afe37fSBibby Hsieh #if IS_REACHABLE(CONFIG_MTK_CMDQ)
74d0afe37fSBibby Hsieh if (cmdq_pkt)
75616443caSCK Hu cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
76616443caSCK Hu cmdq_reg->offset + offset, value);
77d0afe37fSBibby Hsieh else
78d0afe37fSBibby Hsieh #endif
793c87daefSCK Hu writel(value, regs + offset);
80d0afe37fSBibby Hsieh }
81d0afe37fSBibby Hsieh
mtk_ddp_write_relaxed(struct cmdq_pkt * cmdq_pkt,unsigned int value,struct cmdq_client_reg * cmdq_reg,void __iomem * regs,unsigned int offset)823c87daefSCK Hu void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
83616443caSCK Hu struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
843c87daefSCK Hu unsigned int offset)
853c87daefSCK Hu {
863c87daefSCK Hu #if IS_REACHABLE(CONFIG_MTK_CMDQ)
873c87daefSCK Hu if (cmdq_pkt)
88616443caSCK Hu cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
89616443caSCK Hu cmdq_reg->offset + offset, value);
903c87daefSCK Hu else
913c87daefSCK Hu #endif
923c87daefSCK Hu writel_relaxed(value, regs + offset);
933c87daefSCK Hu }
943c87daefSCK Hu
mtk_ddp_write_mask(struct cmdq_pkt * cmdq_pkt,unsigned int value,struct cmdq_client_reg * cmdq_reg,void __iomem * regs,unsigned int offset,unsigned int mask)953c87daefSCK Hu void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
96616443caSCK Hu struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
973c87daefSCK Hu unsigned int offset, unsigned int mask)
98d0afe37fSBibby Hsieh {
99d0afe37fSBibby Hsieh #if IS_REACHABLE(CONFIG_MTK_CMDQ)
100d0afe37fSBibby Hsieh if (cmdq_pkt) {
101616443caSCK Hu cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
102616443caSCK Hu cmdq_reg->offset + offset, value, mask);
103d0afe37fSBibby Hsieh } else {
104d0afe37fSBibby Hsieh #endif
1053c87daefSCK Hu u32 tmp = readl(regs + offset);
106d0afe37fSBibby Hsieh
107d0afe37fSBibby Hsieh tmp = (tmp & ~mask) | (value & mask);
1083c87daefSCK Hu writel(tmp, regs + offset);
109d0afe37fSBibby Hsieh #if IS_REACHABLE(CONFIG_MTK_CMDQ)
110d0afe37fSBibby Hsieh }
111d0afe37fSBibby Hsieh #endif
112d0afe37fSBibby Hsieh }
113d0afe37fSBibby Hsieh
mtk_ddp_clk_enable(struct device * dev)114c0d36de8SCK Hu static int mtk_ddp_clk_enable(struct device *dev)
115c0d36de8SCK Hu {
116c0d36de8SCK Hu struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
117c0d36de8SCK Hu
118c0d36de8SCK Hu return clk_prepare_enable(priv->clk);
119c0d36de8SCK Hu }
120c0d36de8SCK Hu
mtk_ddp_clk_disable(struct device * dev)121c0d36de8SCK Hu static void mtk_ddp_clk_disable(struct device *dev)
122c0d36de8SCK Hu {
123c0d36de8SCK Hu struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
124c0d36de8SCK Hu
125c0d36de8SCK Hu clk_disable_unprepare(priv->clk);
126c0d36de8SCK Hu }
127c0d36de8SCK Hu
mtk_dither_set_common(void __iomem * regs,struct cmdq_client_reg * cmdq_reg,unsigned int bpc,unsigned int cfg,unsigned int dither_en,struct cmdq_pkt * cmdq_pkt)128a6b7c98aSHsin-Yi Wang void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
129a6b7c98aSHsin-Yi Wang unsigned int bpc, unsigned int cfg,
130a6b7c98aSHsin-Yi Wang unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
131a6b7c98aSHsin-Yi Wang {
13272164364SBibby Hsieh /* If bpc equal to 0, the dithering function didn't be enabled */
13372164364SBibby Hsieh if (bpc == 0)
13472164364SBibby Hsieh return;
13572164364SBibby Hsieh
13672164364SBibby Hsieh if (bpc >= MTK_MIN_BPC) {
137aa0c3155Sjason-jh.lin mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
138aa0c3155Sjason-jh.lin mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
139d0afe37fSBibby Hsieh mtk_ddp_write(cmdq_pkt,
140d0afe37fSBibby Hsieh DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
14172164364SBibby Hsieh DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
14272164364SBibby Hsieh DITHER_NEW_BIT_MODE,
143aa0c3155Sjason-jh.lin cmdq_reg, regs, DISP_REG_DITHER_15);
144d0afe37fSBibby Hsieh mtk_ddp_write(cmdq_pkt,
145d0afe37fSBibby Hsieh DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
14672164364SBibby Hsieh DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
14772164364SBibby Hsieh DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
14872164364SBibby Hsieh DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
149aa0c3155Sjason-jh.lin cmdq_reg, regs, DISP_REG_DITHER_16);
150a6b7c98aSHsin-Yi Wang mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
15172164364SBibby Hsieh }
15272164364SBibby Hsieh }
15372164364SBibby Hsieh
mtk_dither_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)15473d37247Sjason-jh.lin static void mtk_dither_config(struct device *dev, unsigned int w,
15573d37247Sjason-jh.lin unsigned int h, unsigned int vrefresh,
15673d37247Sjason-jh.lin unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
15773d37247Sjason-jh.lin {
15873d37247Sjason-jh.lin struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
15973d37247Sjason-jh.lin
16087fd9294SAllen-KH Cheng mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
16173d37247Sjason-jh.lin mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
16273d37247Sjason-jh.lin DISP_REG_DITHER_CFG);
16373d37247Sjason-jh.lin mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
16473d37247Sjason-jh.lin DITHER_ENGINE_EN, cmdq_pkt);
16573d37247Sjason-jh.lin }
16673d37247Sjason-jh.lin
mtk_dither_start(struct device * dev)16773d37247Sjason-jh.lin static void mtk_dither_start(struct device *dev)
16873d37247Sjason-jh.lin {
16973d37247Sjason-jh.lin struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
17073d37247Sjason-jh.lin
17173d37247Sjason-jh.lin writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
17273d37247Sjason-jh.lin }
17373d37247Sjason-jh.lin
mtk_dither_stop(struct device * dev)17473d37247Sjason-jh.lin static void mtk_dither_stop(struct device *dev)
17573d37247Sjason-jh.lin {
17673d37247Sjason-jh.lin struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
17773d37247Sjason-jh.lin
17873d37247Sjason-jh.lin writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
17973d37247Sjason-jh.lin }
18073d37247Sjason-jh.lin
mtk_dither_set(struct device * dev,unsigned int bpc,unsigned int cfg,struct cmdq_pkt * cmdq_pkt)181a6b7c98aSHsin-Yi Wang static void mtk_dither_set(struct device *dev, unsigned int bpc,
182a6b7c98aSHsin-Yi Wang unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
183a6b7c98aSHsin-Yi Wang {
184a6b7c98aSHsin-Yi Wang struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
185a6b7c98aSHsin-Yi Wang
186a6b7c98aSHsin-Yi Wang mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
187a6b7c98aSHsin-Yi Wang DISP_DITHERING, cmdq_pkt);
188a6b7c98aSHsin-Yi Wang }
189a6b7c98aSHsin-Yi Wang
mtk_dsc_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)190b7fb767bSjason-jh.lin static void mtk_dsc_config(struct device *dev, unsigned int w,
191b7fb767bSjason-jh.lin unsigned int h, unsigned int vrefresh,
192b7fb767bSjason-jh.lin unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
193b7fb767bSjason-jh.lin {
194b7fb767bSjason-jh.lin struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
195b7fb767bSjason-jh.lin
196b7fb767bSjason-jh.lin /* dsc bypass mode */
197b7fb767bSjason-jh.lin mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
198b7fb767bSjason-jh.lin DISP_REG_DSC_CON, DSC_BYPASS);
199b7fb767bSjason-jh.lin mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
200b7fb767bSjason-jh.lin DISP_REG_DSC_CON, DSC_UFOE_SEL);
201b7fb767bSjason-jh.lin mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
202b7fb767bSjason-jh.lin DISP_REG_DSC_CON, DSC_DUAL_INOUT);
203b7fb767bSjason-jh.lin }
204b7fb767bSjason-jh.lin
mtk_dsc_start(struct device * dev)205b7fb767bSjason-jh.lin static void mtk_dsc_start(struct device *dev)
206b7fb767bSjason-jh.lin {
207b7fb767bSjason-jh.lin struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
208b7fb767bSjason-jh.lin
209b7fb767bSjason-jh.lin /* write with mask to reserve the value set in mtk_dsc_config */
210b7fb767bSjason-jh.lin mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
211b7fb767bSjason-jh.lin }
212b7fb767bSjason-jh.lin
mtk_dsc_stop(struct device * dev)213b7fb767bSjason-jh.lin static void mtk_dsc_stop(struct device *dev)
214b7fb767bSjason-jh.lin {
215b7fb767bSjason-jh.lin struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
216b7fb767bSjason-jh.lin
217b7fb767bSjason-jh.lin writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
218b7fb767bSjason-jh.lin }
219b7fb767bSjason-jh.lin
mtk_od_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)2204d510659SCK Hu static void mtk_od_config(struct device *dev, unsigned int w,
22172164364SBibby Hsieh unsigned int h, unsigned int vrefresh,
222d0afe37fSBibby Hsieh unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
223119f5173SCK Hu {
2244d510659SCK Hu struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
2253c87daefSCK Hu
226aa0c3155Sjason-jh.lin mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
227aa0c3155Sjason-jh.lin mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
228aa0c3155Sjason-jh.lin mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
229119f5173SCK Hu }
230119f5173SCK Hu
mtk_od_start(struct device * dev)2314d510659SCK Hu static void mtk_od_start(struct device *dev)
232119f5173SCK Hu {
2334d510659SCK Hu struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
2343c87daefSCK Hu
235aa0c3155Sjason-jh.lin writel(1, priv->regs + DISP_REG_OD_EN);
236119f5173SCK Hu }
237119f5173SCK Hu
mtk_postmask_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)2388c9f215aSYongqiang Niu static void mtk_postmask_config(struct device *dev, unsigned int w,
2398c9f215aSYongqiang Niu unsigned int h, unsigned int vrefresh,
2408c9f215aSYongqiang Niu unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
2418c9f215aSYongqiang Niu {
2428c9f215aSYongqiang Niu struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
2438c9f215aSYongqiang Niu
2448c9f215aSYongqiang Niu mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
245aa0c3155Sjason-jh.lin DISP_REG_POSTMASK_SIZE);
2468c9f215aSYongqiang Niu mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
247aa0c3155Sjason-jh.lin priv->regs, DISP_REG_POSTMASK_CFG);
2488c9f215aSYongqiang Niu }
2498c9f215aSYongqiang Niu
mtk_postmask_start(struct device * dev)2508c9f215aSYongqiang Niu static void mtk_postmask_start(struct device *dev)
2518c9f215aSYongqiang Niu {
2528c9f215aSYongqiang Niu struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
2538c9f215aSYongqiang Niu
254aa0c3155Sjason-jh.lin writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
2558c9f215aSYongqiang Niu }
2568c9f215aSYongqiang Niu
mtk_postmask_stop(struct device * dev)2578c9f215aSYongqiang Niu static void mtk_postmask_stop(struct device *dev)
2588c9f215aSYongqiang Niu {
2598c9f215aSYongqiang Niu struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
2608c9f215aSYongqiang Niu
261aa0c3155Sjason-jh.lin writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
2628c9f215aSYongqiang Niu }
2638c9f215aSYongqiang Niu
mtk_ufoe_start(struct device * dev)26473d37247Sjason-jh.lin static void mtk_ufoe_start(struct device *dev)
26573d37247Sjason-jh.lin {
26673d37247Sjason-jh.lin struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
26773d37247Sjason-jh.lin
26873d37247Sjason-jh.lin writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
26973d37247Sjason-jh.lin }
27073d37247Sjason-jh.lin
2710664d139SBibby Hsieh static const struct mtk_ddp_comp_funcs ddp_aal = {
27278d1783cSYongqiang Niu .clk_enable = mtk_aal_clk_enable,
27378d1783cSYongqiang Niu .clk_disable = mtk_aal_clk_disable,
27469a4237aSYongqiang Niu .gamma_set = mtk_aal_gamma_set,
2750664d139SBibby Hsieh .config = mtk_aal_config,
2760664d139SBibby Hsieh .start = mtk_aal_start,
2770664d139SBibby Hsieh .stop = mtk_aal_stop,
2780664d139SBibby Hsieh };
2790664d139SBibby Hsieh
280cefb6abfSYongqiang Niu static const struct mtk_ddp_comp_funcs ddp_ccorr = {
281072a4cb5SYongqiang Niu .clk_enable = mtk_ccorr_clk_enable,
282072a4cb5SYongqiang Niu .clk_disable = mtk_ccorr_clk_disable,
283cefb6abfSYongqiang Niu .config = mtk_ccorr_config,
284cefb6abfSYongqiang Niu .start = mtk_ccorr_start,
285cefb6abfSYongqiang Niu .stop = mtk_ccorr_stop,
28684abcf12SYongqiang Niu .ctm_set = mtk_ccorr_ctm_set,
287cefb6abfSYongqiang Niu };
288cefb6abfSYongqiang Niu
2891d33f13aSCK Hu static const struct mtk_ddp_comp_funcs ddp_color = {
2901d33f13aSCK Hu .clk_enable = mtk_color_clk_enable,
2911d33f13aSCK Hu .clk_disable = mtk_color_clk_disable,
2921d33f13aSCK Hu .config = mtk_color_config,
2931d33f13aSCK Hu .start = mtk_color_start,
2941d33f13aSCK Hu };
2951d33f13aSCK Hu
296450aa87cSYongqiang Niu static const struct mtk_ddp_comp_funcs ddp_dither = {
297c0d36de8SCK Hu .clk_enable = mtk_ddp_clk_enable,
298c0d36de8SCK Hu .clk_disable = mtk_ddp_clk_disable,
299450aa87cSYongqiang Niu .config = mtk_dither_config,
300450aa87cSYongqiang Niu .start = mtk_dither_start,
301450aa87cSYongqiang Niu .stop = mtk_dither_stop,
302450aa87cSYongqiang Niu };
303450aa87cSYongqiang Niu
3041d33f13aSCK Hu static const struct mtk_ddp_comp_funcs ddp_dpi = {
3051d33f13aSCK Hu .start = mtk_dpi_start,
3061d33f13aSCK Hu .stop = mtk_dpi_stop,
3071d33f13aSCK Hu };
3081d33f13aSCK Hu
309b7fb767bSjason-jh.lin static const struct mtk_ddp_comp_funcs ddp_dsc = {
310b7fb767bSjason-jh.lin .clk_enable = mtk_ddp_clk_enable,
311b7fb767bSjason-jh.lin .clk_disable = mtk_ddp_clk_disable,
312b7fb767bSjason-jh.lin .config = mtk_dsc_config,
313b7fb767bSjason-jh.lin .start = mtk_dsc_start,
314b7fb767bSjason-jh.lin .stop = mtk_dsc_stop,
315b7fb767bSjason-jh.lin };
316b7fb767bSjason-jh.lin
3171d33f13aSCK Hu static const struct mtk_ddp_comp_funcs ddp_dsi = {
3181d33f13aSCK Hu .start = mtk_dsi_ddp_start,
3191d33f13aSCK Hu .stop = mtk_dsi_ddp_stop,
3201d33f13aSCK Hu };
3211d33f13aSCK Hu
322e0a5d337SBibby Hsieh static const struct mtk_ddp_comp_funcs ddp_gamma = {
32369a4237aSYongqiang Niu .clk_enable = mtk_gamma_clk_enable,
32469a4237aSYongqiang Niu .clk_disable = mtk_gamma_clk_disable,
3252f3f4ddaSBibby Hsieh .gamma_set = mtk_gamma_set,
326e0a5d337SBibby Hsieh .config = mtk_gamma_config,
327e0a5d337SBibby Hsieh .start = mtk_gamma_start,
328e0a5d337SBibby Hsieh .stop = mtk_gamma_stop,
329e0a5d337SBibby Hsieh };
330e0a5d337SBibby Hsieh
331bd448b88Sjason-jh.lin static const struct mtk_ddp_comp_funcs ddp_merge = {
332bd448b88Sjason-jh.lin .clk_enable = mtk_merge_clk_enable,
333bd448b88Sjason-jh.lin .clk_disable = mtk_merge_clk_disable,
334bd448b88Sjason-jh.lin .start = mtk_merge_start,
335bd448b88Sjason-jh.lin .stop = mtk_merge_stop,
336bd448b88Sjason-jh.lin .config = mtk_merge_config,
337bd448b88Sjason-jh.lin };
338bd448b88Sjason-jh.lin
339119f5173SCK Hu static const struct mtk_ddp_comp_funcs ddp_od = {
340c0d36de8SCK Hu .clk_enable = mtk_ddp_clk_enable,
341c0d36de8SCK Hu .clk_disable = mtk_ddp_clk_disable,
342119f5173SCK Hu .config = mtk_od_config,
343119f5173SCK Hu .start = mtk_od_start,
344119f5173SCK Hu };
345119f5173SCK Hu
3461d33f13aSCK Hu static const struct mtk_ddp_comp_funcs ddp_ovl = {
3471d33f13aSCK Hu .clk_enable = mtk_ovl_clk_enable,
3481d33f13aSCK Hu .clk_disable = mtk_ovl_clk_disable,
3491d33f13aSCK Hu .config = mtk_ovl_config,
3501d33f13aSCK Hu .start = mtk_ovl_start,
3511d33f13aSCK Hu .stop = mtk_ovl_stop,
352b74d921bSRex-BC Chen .register_vblank_cb = mtk_ovl_register_vblank_cb,
353b74d921bSRex-BC Chen .unregister_vblank_cb = mtk_ovl_unregister_vblank_cb,
3541d33f13aSCK Hu .enable_vblank = mtk_ovl_enable_vblank,
3551d33f13aSCK Hu .disable_vblank = mtk_ovl_disable_vblank,
3561d33f13aSCK Hu .supported_rotations = mtk_ovl_supported_rotations,
3571d33f13aSCK Hu .layer_nr = mtk_ovl_layer_nr,
3581d33f13aSCK Hu .layer_check = mtk_ovl_layer_check,
3591d33f13aSCK Hu .layer_config = mtk_ovl_layer_config,
3601d33f13aSCK Hu .bgclr_in_on = mtk_ovl_bgclr_in_on,
3611d33f13aSCK Hu .bgclr_in_off = mtk_ovl_bgclr_in_off,
362f287c66aSJustin Green .get_formats = mtk_ovl_get_formats,
363f287c66aSJustin Green .get_num_formats = mtk_ovl_get_num_formats,
3641d33f13aSCK Hu };
3651d33f13aSCK Hu
3668c9f215aSYongqiang Niu static const struct mtk_ddp_comp_funcs ddp_postmask = {
3678c9f215aSYongqiang Niu .clk_enable = mtk_ddp_clk_enable,
3688c9f215aSYongqiang Niu .clk_disable = mtk_ddp_clk_disable,
3698c9f215aSYongqiang Niu .config = mtk_postmask_config,
3708c9f215aSYongqiang Niu .start = mtk_postmask_start,
3718c9f215aSYongqiang Niu .stop = mtk_postmask_stop,
3728c9f215aSYongqiang Niu };
3738c9f215aSYongqiang Niu
3741d33f13aSCK Hu static const struct mtk_ddp_comp_funcs ddp_rdma = {
3751d33f13aSCK Hu .clk_enable = mtk_rdma_clk_enable,
3761d33f13aSCK Hu .clk_disable = mtk_rdma_clk_disable,
3771d33f13aSCK Hu .config = mtk_rdma_config,
3781d33f13aSCK Hu .start = mtk_rdma_start,
3791d33f13aSCK Hu .stop = mtk_rdma_stop,
380b74d921bSRex-BC Chen .register_vblank_cb = mtk_rdma_register_vblank_cb,
381b74d921bSRex-BC Chen .unregister_vblank_cb = mtk_rdma_unregister_vblank_cb,
3821d33f13aSCK Hu .enable_vblank = mtk_rdma_enable_vblank,
3831d33f13aSCK Hu .disable_vblank = mtk_rdma_disable_vblank,
3841d33f13aSCK Hu .layer_nr = mtk_rdma_layer_nr,
3851d33f13aSCK Hu .layer_config = mtk_rdma_layer_config,
386f287c66aSJustin Green .get_formats = mtk_rdma_get_formats,
387f287c66aSJustin Green .get_num_formats = mtk_rdma_get_num_formats,
3881d33f13aSCK Hu };
3891d33f13aSCK Hu
390119f5173SCK Hu static const struct mtk_ddp_comp_funcs ddp_ufoe = {
391c0d36de8SCK Hu .clk_enable = mtk_ddp_clk_enable,
392c0d36de8SCK Hu .clk_disable = mtk_ddp_clk_disable,
393119f5173SCK Hu .start = mtk_ufoe_start,
394119f5173SCK Hu };
395119f5173SCK Hu
3960d9eee91SNancy.Lin static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
3970d9eee91SNancy.Lin .clk_enable = mtk_ovl_adaptor_clk_enable,
3980d9eee91SNancy.Lin .clk_disable = mtk_ovl_adaptor_clk_disable,
3990d9eee91SNancy.Lin .config = mtk_ovl_adaptor_config,
4000d9eee91SNancy.Lin .start = mtk_ovl_adaptor_start,
4010d9eee91SNancy.Lin .stop = mtk_ovl_adaptor_stop,
4020d9eee91SNancy.Lin .layer_nr = mtk_ovl_adaptor_layer_nr,
4030d9eee91SNancy.Lin .layer_config = mtk_ovl_adaptor_layer_config,
4040d9eee91SNancy.Lin .register_vblank_cb = mtk_ovl_adaptor_register_vblank_cb,
4050d9eee91SNancy.Lin .unregister_vblank_cb = mtk_ovl_adaptor_unregister_vblank_cb,
4060d9eee91SNancy.Lin .enable_vblank = mtk_ovl_adaptor_enable_vblank,
4070d9eee91SNancy.Lin .disable_vblank = mtk_ovl_adaptor_disable_vblank,
4080d9eee91SNancy.Lin .dma_dev_get = mtk_ovl_adaptor_dma_dev_get,
4090d9eee91SNancy.Lin .connect = mtk_ovl_adaptor_connect,
4100d9eee91SNancy.Lin .disconnect = mtk_ovl_adaptor_disconnect,
4110d9eee91SNancy.Lin .add = mtk_ovl_adaptor_add_comp,
4120d9eee91SNancy.Lin .remove = mtk_ovl_adaptor_remove_comp,
413d6dc3cdcSNancy.Lin .get_formats = mtk_ovl_adaptor_get_formats,
414d6dc3cdcSNancy.Lin .get_num_formats = mtk_ovl_adaptor_get_num_formats,
4150d9eee91SNancy.Lin };
4160d9eee91SNancy.Lin
417119f5173SCK Hu static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
418119f5173SCK Hu [MTK_DISP_AAL] = "aal",
41973d37247Sjason-jh.lin [MTK_DISP_BLS] = "bls",
42073d37247Sjason-jh.lin [MTK_DISP_CCORR] = "ccorr",
42173d37247Sjason-jh.lin [MTK_DISP_COLOR] = "color",
422450aa87cSYongqiang Niu [MTK_DISP_DITHER] = "dither",
423b7fb767bSjason-jh.lin [MTK_DISP_DSC] = "dsc",
42473d37247Sjason-jh.lin [MTK_DISP_GAMMA] = "gamma",
425bd448b88Sjason-jh.lin [MTK_DISP_MERGE] = "merge",
426119f5173SCK Hu [MTK_DISP_MUTEX] = "mutex",
427119f5173SCK Hu [MTK_DISP_OD] = "od",
42873d37247Sjason-jh.lin [MTK_DISP_OVL] = "ovl",
42973d37247Sjason-jh.lin [MTK_DISP_OVL_2L] = "ovl-2l",
4300d9eee91SNancy.Lin [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
4318c9f215aSYongqiang Niu [MTK_DISP_POSTMASK] = "postmask",
43273d37247Sjason-jh.lin [MTK_DISP_PWM] = "pwm",
43373d37247Sjason-jh.lin [MTK_DISP_RDMA] = "rdma",
43473d37247Sjason-jh.lin [MTK_DISP_UFOE] = "ufoe",
43573d37247Sjason-jh.lin [MTK_DISP_WDMA] = "wdma",
436d86c1568SGuillaume Ranquet [MTK_DP_INTF] = "dp-intf",
43773d37247Sjason-jh.lin [MTK_DPI] = "dpi",
43873d37247Sjason-jh.lin [MTK_DSI] = "dsi",
439119f5173SCK Hu };
440119f5173SCK Hu
441119f5173SCK Hu struct mtk_ddp_comp_match {
442119f5173SCK Hu enum mtk_ddp_comp_type type;
443119f5173SCK Hu int alias_id;
444119f5173SCK Hu const struct mtk_ddp_comp_funcs *funcs;
445119f5173SCK Hu };
446119f5173SCK Hu
4470d9eee91SNancy.Lin static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] = {
448d480bbc4Sstu.hsieh@mediatek.com [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
449d480bbc4Sstu.hsieh@mediatek.com [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
450c37813deSyt.shen@mediatek.com [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
451cefb6abfSYongqiang Niu [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
4521d33f13aSCK Hu [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
4531d33f13aSCK Hu [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
4549c1b06a5Sjason-jh.lin [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
455d86c1568SGuillaume Ranquet [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi },
456d86c1568SGuillaume Ranquet [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi },
4571d33f13aSCK Hu [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
4581d33f13aSCK Hu [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
4590d9eee91SNancy.Lin [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
460b7fb767bSjason-jh.lin [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
461b7fb767bSjason-jh.lin [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
4621d33f13aSCK Hu [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
4631d33f13aSCK Hu [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
4641d33f13aSCK Hu [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
4651d33f13aSCK Hu [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
466e0a5d337SBibby Hsieh [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
467bd448b88Sjason-jh.lin [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
468bd448b88Sjason-jh.lin [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
469bd448b88Sjason-jh.lin [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
470bd448b88Sjason-jh.lin [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
471bd448b88Sjason-jh.lin [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
472bd448b88Sjason-jh.lin [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
473df2dce4eSstu.hsieh@mediatek.com [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
474df2dce4eSstu.hsieh@mediatek.com [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
4751d33f13aSCK Hu [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
4761d33f13aSCK Hu [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
4771d33f13aSCK Hu [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
4781d33f13aSCK Hu [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
479787a7a87SYongqiang Niu [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
4808c9f215aSYongqiang Niu [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
481119f5173SCK Hu [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
4829ec3818eSstu.hsieh@mediatek.com [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
4832e244778Sstu.hsieh@mediatek.com [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
4841d33f13aSCK Hu [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
4851d33f13aSCK Hu [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
4861d33f13aSCK Hu [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
487f4cca88eSYongqiang Niu [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
488119f5173SCK Hu [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
489119f5173SCK Hu [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
490119f5173SCK Hu [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
491119f5173SCK Hu };
492119f5173SCK Hu
mtk_drm_find_comp_in_ddp(struct device * dev,const unsigned int * path,unsigned int path_len,struct mtk_ddp_comp * ddp_comp)493ff139560SCK Hu static bool mtk_drm_find_comp_in_ddp(struct device *dev,
4940d9eee91SNancy.Lin const unsigned int *path,
495ff139560SCK Hu unsigned int path_len,
496ff139560SCK Hu struct mtk_ddp_comp *ddp_comp)
4975aa8e764SStu Hsieh {
4985aa8e764SStu Hsieh unsigned int i;
4995aa8e764SStu Hsieh
5005aa8e764SStu Hsieh if (path == NULL)
5015aa8e764SStu Hsieh return false;
5025aa8e764SStu Hsieh
5035aa8e764SStu Hsieh for (i = 0U; i < path_len; i++)
504ff139560SCK Hu if (dev == ddp_comp[path[i]].dev)
5055aa8e764SStu Hsieh return true;
5065aa8e764SStu Hsieh
5075aa8e764SStu Hsieh return false;
5085aa8e764SStu Hsieh }
5095aa8e764SStu Hsieh
mtk_ddp_comp_get_id(struct device_node * node,enum mtk_ddp_comp_type comp_type)510119f5173SCK Hu int mtk_ddp_comp_get_id(struct device_node *node,
511119f5173SCK Hu enum mtk_ddp_comp_type comp_type)
512119f5173SCK Hu {
513119f5173SCK Hu int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
514119f5173SCK Hu int i;
515119f5173SCK Hu
516119f5173SCK Hu for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
517119f5173SCK Hu if (comp_type == mtk_ddp_matches[i].type &&
518119f5173SCK Hu (id < 0 || id == mtk_ddp_matches[i].alias_id))
519119f5173SCK Hu return i;
520119f5173SCK Hu }
521119f5173SCK Hu
522119f5173SCK Hu return -EINVAL;
523119f5173SCK Hu }
524119f5173SCK Hu
mtk_drm_find_possible_crtc_by_comp(struct drm_device * drm,struct device * dev)5255aa8e764SStu Hsieh unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
526ff139560SCK Hu struct device *dev)
5275aa8e764SStu Hsieh {
5285aa8e764SStu Hsieh struct mtk_drm_private *private = drm->dev_private;
5295aa8e764SStu Hsieh unsigned int ret = 0;
5305aa8e764SStu Hsieh
531ff139560SCK Hu if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len,
532ff139560SCK Hu private->ddp_comp))
5335aa8e764SStu Hsieh ret = BIT(0);
534ff139560SCK Hu else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
535ff139560SCK Hu private->data->ext_len, private->ddp_comp))
5365aa8e764SStu Hsieh ret = BIT(1);
537ff139560SCK Hu else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
538ff139560SCK Hu private->data->third_len, private->ddp_comp))
5395aa8e764SStu Hsieh ret = BIT(2);
5405aa8e764SStu Hsieh else
5415aa8e764SStu Hsieh DRM_INFO("Failed to find comp in ddp table\n");
5425aa8e764SStu Hsieh
5435aa8e764SStu Hsieh return ret;
5445aa8e764SStu Hsieh }
5455aa8e764SStu Hsieh
mtk_ddp_comp_init(struct device_node * node,struct mtk_ddp_comp * comp,unsigned int comp_id)5466ea6f827SChun-Kuang Hu int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
5470d9eee91SNancy.Lin unsigned int comp_id)
548119f5173SCK Hu {
5496ea6f827SChun-Kuang Hu struct platform_device *comp_pdev;
550119f5173SCK Hu enum mtk_ddp_comp_type type;
551c0d36de8SCK Hu struct mtk_ddp_comp_dev *priv;
552ce6c24baSYong Wu #if IS_REACHABLE(CONFIG_MTK_CMDQ)
553926df14eSCK Hu int ret;
554ce6c24baSYong Wu #endif
555119f5173SCK Hu
5560d9eee91SNancy.Lin if (comp_id < 0 || comp_id >= DDP_COMPONENT_DRM_ID_MAX)
557119f5173SCK Hu return -EINVAL;
558119f5173SCK Hu
559c5f228efSyt.shen@mediatek.com type = mtk_ddp_matches[comp_id].type;
560c5f228efSyt.shen@mediatek.com
561119f5173SCK Hu comp->id = comp_id;
5621d33f13aSCK Hu comp->funcs = mtk_ddp_matches[comp_id].funcs;
5630d9eee91SNancy.Lin /* Not all drm components have a DTS device node, such as ovl_adaptor,
5640d9eee91SNancy.Lin * which is the drm bring up sub driver
5650d9eee91SNancy.Lin */
566*63ee9438SNancy.Lin if (!node)
567*63ee9438SNancy.Lin return 0;
568*63ee9438SNancy.Lin
5696ea6f827SChun-Kuang Hu comp_pdev = of_find_device_by_node(node);
5706ea6f827SChun-Kuang Hu if (!comp_pdev) {
5716ea6f827SChun-Kuang Hu DRM_INFO("Waiting for device %s\n", node->full_name);
5726ea6f827SChun-Kuang Hu return -EPROBE_DEFER;
5736ea6f827SChun-Kuang Hu }
574c0d36de8SCK Hu comp->dev = &comp_pdev->dev;
5756ea6f827SChun-Kuang Hu
57678d1783cSYongqiang Niu if (type == MTK_DISP_AAL ||
57778d1783cSYongqiang Niu type == MTK_DISP_BLS ||
578072a4cb5SYongqiang Niu type == MTK_DISP_CCORR ||
5794d510659SCK Hu type == MTK_DISP_COLOR ||
58069a4237aSYongqiang Niu type == MTK_DISP_GAMMA ||
581bd448b88Sjason-jh.lin type == MTK_DISP_MERGE ||
582c0d36de8SCK Hu type == MTK_DISP_OVL ||
583c0d36de8SCK Hu type == MTK_DISP_OVL_2L ||
5844d510659SCK Hu type == MTK_DISP_PWM ||
58573d37247Sjason-jh.lin type == MTK_DISP_RDMA ||
58673d37247Sjason-jh.lin type == MTK_DPI ||
587d86c1568SGuillaume Ranquet type == MTK_DP_INTF ||
58873d37247Sjason-jh.lin type == MTK_DSI)
589c0d36de8SCK Hu return 0;
590c0d36de8SCK Hu
591c0d36de8SCK Hu priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
592c0d36de8SCK Hu if (!priv)
593c0d36de8SCK Hu return -ENOMEM;
594c0d36de8SCK Hu
5953c87daefSCK Hu priv->regs = of_iomap(node, 0);
596c0d36de8SCK Hu priv->clk = of_clk_get(node, 0);
597c0d36de8SCK Hu if (IS_ERR(priv->clk))
598c0d36de8SCK Hu return PTR_ERR(priv->clk);
599c0d36de8SCK Hu
600616443caSCK Hu #if IS_REACHABLE(CONFIG_MTK_CMDQ)
601616443caSCK Hu ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
602616443caSCK Hu if (ret)
603616443caSCK Hu dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
604616443caSCK Hu #endif
605616443caSCK Hu
606c0d36de8SCK Hu platform_set_drvdata(comp_pdev, priv);
607c0d36de8SCK Hu
608119f5173SCK Hu return 0;
609119f5173SCK Hu }
610