12e78620bSAllen-KH Cheng// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 22e78620bSAllen-KH Cheng/* 32e78620bSAllen-KH Cheng * Copyright (C) 2022 MediaTek Inc. 42e78620bSAllen-KH Cheng * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 52e78620bSAllen-KH Cheng */ 62e78620bSAllen-KH Cheng/dts-v1/; 72e78620bSAllen-KH Cheng#include <dt-bindings/clock/mt8186-clk.h> 841218847SAllen-KH Cheng#include <dt-bindings/gce/mt8186-gce.h> 92e78620bSAllen-KH Cheng#include <dt-bindings/interrupt-controller/arm-gic.h> 102e78620bSAllen-KH Cheng#include <dt-bindings/interrupt-controller/irq.h> 11d4a65162SAllen-KH Cheng#include <dt-bindings/memory/mt8186-memory-port.h> 122e78620bSAllen-KH Cheng#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 132e78620bSAllen-KH Cheng#include <dt-bindings/power/mt8186-power.h> 142e78620bSAllen-KH Cheng#include <dt-bindings/phy/phy.h> 152e78620bSAllen-KH Cheng#include <dt-bindings/reset/mt8186-resets.h> 162e78620bSAllen-KH Cheng 172e78620bSAllen-KH Cheng/ { 182e78620bSAllen-KH Cheng compatible = "mediatek,mt8186"; 192e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 202e78620bSAllen-KH Cheng #address-cells = <2>; 212e78620bSAllen-KH Cheng #size-cells = <2>; 222e78620bSAllen-KH Cheng 237e07d332SAllen-KH Cheng aliases { 247e07d332SAllen-KH Cheng ovl0 = &ovl0; 259bd3a188SChen-Yu Tsai ovl-2l0 = &ovl_2l0; 267e07d332SAllen-KH Cheng rdma0 = &rdma0; 277e07d332SAllen-KH Cheng rdma1 = &rdma1; 287e07d332SAllen-KH Cheng }; 297e07d332SAllen-KH Cheng 3032dfbc03SChen-Yu Tsai cci: cci { 3132dfbc03SChen-Yu Tsai compatible = "mediatek,mt8186-cci"; 3232dfbc03SChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, 3332dfbc03SChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 3432dfbc03SChen-Yu Tsai clock-names = "cci", "intermediate"; 3532dfbc03SChen-Yu Tsai operating-points-v2 = <&cci_opp>; 3632dfbc03SChen-Yu Tsai }; 3732dfbc03SChen-Yu Tsai 3832dfbc03SChen-Yu Tsai cci_opp: opp-table-cci { 3932dfbc03SChen-Yu Tsai compatible = "operating-points-v2"; 4032dfbc03SChen-Yu Tsai opp-shared; 4132dfbc03SChen-Yu Tsai 4232dfbc03SChen-Yu Tsai cci_opp_0: opp-500000000 { 4332dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <500000000>; 4432dfbc03SChen-Yu Tsai opp-microvolt = <600000>; 4532dfbc03SChen-Yu Tsai }; 4632dfbc03SChen-Yu Tsai 4732dfbc03SChen-Yu Tsai cci_opp_1: opp-560000000 { 4832dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <560000000>; 4932dfbc03SChen-Yu Tsai opp-microvolt = <675000>; 5032dfbc03SChen-Yu Tsai }; 5132dfbc03SChen-Yu Tsai 5232dfbc03SChen-Yu Tsai cci_opp_2: opp-612000000 { 5332dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <612000000>; 5432dfbc03SChen-Yu Tsai opp-microvolt = <693750>; 5532dfbc03SChen-Yu Tsai }; 5632dfbc03SChen-Yu Tsai 5732dfbc03SChen-Yu Tsai cci_opp_3: opp-682000000 { 5832dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <682000000>; 5932dfbc03SChen-Yu Tsai opp-microvolt = <718750>; 6032dfbc03SChen-Yu Tsai }; 6132dfbc03SChen-Yu Tsai 6232dfbc03SChen-Yu Tsai cci_opp_4: opp-752000000 { 6332dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <752000000>; 6432dfbc03SChen-Yu Tsai opp-microvolt = <743750>; 6532dfbc03SChen-Yu Tsai }; 6632dfbc03SChen-Yu Tsai 6732dfbc03SChen-Yu Tsai cci_opp_5: opp-822000000 { 6832dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <822000000>; 6932dfbc03SChen-Yu Tsai opp-microvolt = <768750>; 7032dfbc03SChen-Yu Tsai }; 7132dfbc03SChen-Yu Tsai 7232dfbc03SChen-Yu Tsai cci_opp_6: opp-875000000 { 7332dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <875000000>; 7432dfbc03SChen-Yu Tsai opp-microvolt = <781250>; 7532dfbc03SChen-Yu Tsai }; 7632dfbc03SChen-Yu Tsai 7732dfbc03SChen-Yu Tsai cci_opp_7: opp-927000000 { 7832dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <927000000>; 7932dfbc03SChen-Yu Tsai opp-microvolt = <800000>; 8032dfbc03SChen-Yu Tsai }; 8132dfbc03SChen-Yu Tsai 8232dfbc03SChen-Yu Tsai cci_opp_8: opp-980000000 { 8332dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <980000000>; 8432dfbc03SChen-Yu Tsai opp-microvolt = <818750>; 8532dfbc03SChen-Yu Tsai }; 8632dfbc03SChen-Yu Tsai 8732dfbc03SChen-Yu Tsai cci_opp_9: opp-1050000000 { 8832dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <1050000000>; 8932dfbc03SChen-Yu Tsai opp-microvolt = <843750>; 9032dfbc03SChen-Yu Tsai }; 9132dfbc03SChen-Yu Tsai 9232dfbc03SChen-Yu Tsai cci_opp_10: opp-1120000000 { 9332dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <1120000000>; 9432dfbc03SChen-Yu Tsai opp-microvolt = <862500>; 9532dfbc03SChen-Yu Tsai }; 9632dfbc03SChen-Yu Tsai 9732dfbc03SChen-Yu Tsai cci_opp_11: opp-1155000000 { 9832dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <1155000000>; 9932dfbc03SChen-Yu Tsai opp-microvolt = <887500>; 10032dfbc03SChen-Yu Tsai }; 10132dfbc03SChen-Yu Tsai 10232dfbc03SChen-Yu Tsai cci_opp_12: opp-1190000000 { 10332dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <1190000000>; 10432dfbc03SChen-Yu Tsai opp-microvolt = <906250>; 10532dfbc03SChen-Yu Tsai }; 10632dfbc03SChen-Yu Tsai 10732dfbc03SChen-Yu Tsai cci_opp_13: opp-1260000000 { 10832dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <1260000000>; 10932dfbc03SChen-Yu Tsai opp-microvolt = <950000>; 11032dfbc03SChen-Yu Tsai }; 11132dfbc03SChen-Yu Tsai 11232dfbc03SChen-Yu Tsai cci_opp_14: opp-1330000000 { 11332dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <1330000000>; 11432dfbc03SChen-Yu Tsai opp-microvolt = <993750>; 11532dfbc03SChen-Yu Tsai }; 11632dfbc03SChen-Yu Tsai 11732dfbc03SChen-Yu Tsai cci_opp_15: opp-1400000000 { 11832dfbc03SChen-Yu Tsai opp-hz = /bits/ 64 <1400000000>; 11932dfbc03SChen-Yu Tsai opp-microvolt = <1031250>; 12032dfbc03SChen-Yu Tsai }; 12132dfbc03SChen-Yu Tsai }; 12232dfbc03SChen-Yu Tsai 1238f4ed8fcSChen-Yu Tsai cluster0_opp: opp-table-cluster0 { 1248f4ed8fcSChen-Yu Tsai compatible = "operating-points-v2"; 1258f4ed8fcSChen-Yu Tsai opp-shared; 1268f4ed8fcSChen-Yu Tsai 1278f4ed8fcSChen-Yu Tsai opp-500000000 { 1288f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <500000000>; 1298f4ed8fcSChen-Yu Tsai opp-microvolt = <600000>; 1308f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_0>; 1318f4ed8fcSChen-Yu Tsai }; 1328f4ed8fcSChen-Yu Tsai 1338f4ed8fcSChen-Yu Tsai opp-774000000 { 1348f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <774000000>; 1358f4ed8fcSChen-Yu Tsai opp-microvolt = <675000>; 1368f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_1>; 1378f4ed8fcSChen-Yu Tsai }; 1388f4ed8fcSChen-Yu Tsai 1398f4ed8fcSChen-Yu Tsai opp-875000000 { 1408f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <875000000>; 1418f4ed8fcSChen-Yu Tsai opp-microvolt = <700000>; 1428f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_2>; 1438f4ed8fcSChen-Yu Tsai }; 1448f4ed8fcSChen-Yu Tsai 1458f4ed8fcSChen-Yu Tsai opp-975000000 { 1468f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <975000000>; 1478f4ed8fcSChen-Yu Tsai opp-microvolt = <725000>; 1488f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_3>; 1498f4ed8fcSChen-Yu Tsai }; 1508f4ed8fcSChen-Yu Tsai 1518f4ed8fcSChen-Yu Tsai opp-1075000000 { 1528f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1075000000>; 1538f4ed8fcSChen-Yu Tsai opp-microvolt = <750000>; 1548f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_4>; 1558f4ed8fcSChen-Yu Tsai }; 1568f4ed8fcSChen-Yu Tsai 1578f4ed8fcSChen-Yu Tsai opp-1175000000 { 1588f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1175000000>; 1598f4ed8fcSChen-Yu Tsai opp-microvolt = <775000>; 1608f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_5>; 1618f4ed8fcSChen-Yu Tsai }; 1628f4ed8fcSChen-Yu Tsai 1638f4ed8fcSChen-Yu Tsai opp-1275000000 { 1648f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1275000000>; 1658f4ed8fcSChen-Yu Tsai opp-microvolt = <800000>; 1668f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_6>; 1678f4ed8fcSChen-Yu Tsai }; 1688f4ed8fcSChen-Yu Tsai 1698f4ed8fcSChen-Yu Tsai opp-1375000000 { 1708f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1375000000>; 1718f4ed8fcSChen-Yu Tsai opp-microvolt = <825000>; 1728f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_7>; 1738f4ed8fcSChen-Yu Tsai }; 1748f4ed8fcSChen-Yu Tsai 1758f4ed8fcSChen-Yu Tsai opp-1500000000 { 1768f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1500000000>; 1778f4ed8fcSChen-Yu Tsai opp-microvolt = <856250>; 1788f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_8>; 1798f4ed8fcSChen-Yu Tsai }; 1808f4ed8fcSChen-Yu Tsai 1818f4ed8fcSChen-Yu Tsai opp-1618000000 { 1828f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1618000000>; 1838f4ed8fcSChen-Yu Tsai opp-microvolt = <875000>; 1848f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_9>; 1858f4ed8fcSChen-Yu Tsai }; 1868f4ed8fcSChen-Yu Tsai 1878f4ed8fcSChen-Yu Tsai opp-1666000000 { 1888f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1666000000>; 1898f4ed8fcSChen-Yu Tsai opp-microvolt = <900000>; 1908f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_10>; 1918f4ed8fcSChen-Yu Tsai }; 1928f4ed8fcSChen-Yu Tsai 1938f4ed8fcSChen-Yu Tsai opp-1733000000 { 1948f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1733000000>; 1958f4ed8fcSChen-Yu Tsai opp-microvolt = <925000>; 1968f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_11>; 1978f4ed8fcSChen-Yu Tsai }; 1988f4ed8fcSChen-Yu Tsai 1998f4ed8fcSChen-Yu Tsai opp-1800000000 { 2008f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1800000000>; 2018f4ed8fcSChen-Yu Tsai opp-microvolt = <950000>; 2028f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_12>; 2038f4ed8fcSChen-Yu Tsai }; 2048f4ed8fcSChen-Yu Tsai 2058f4ed8fcSChen-Yu Tsai opp-1866000000 { 2068f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1866000000>; 2078f4ed8fcSChen-Yu Tsai opp-microvolt = <981250>; 2088f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_13>; 2098f4ed8fcSChen-Yu Tsai }; 2108f4ed8fcSChen-Yu Tsai 2118f4ed8fcSChen-Yu Tsai opp-1933000000 { 2128f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1933000000>; 2138f4ed8fcSChen-Yu Tsai opp-microvolt = <1006250>; 2148f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_14>; 2158f4ed8fcSChen-Yu Tsai }; 2168f4ed8fcSChen-Yu Tsai 2178f4ed8fcSChen-Yu Tsai opp-2000000000 { 2188f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <2000000000>; 2198f4ed8fcSChen-Yu Tsai opp-microvolt = <1031250>; 2208f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_15>; 2218f4ed8fcSChen-Yu Tsai }; 2228f4ed8fcSChen-Yu Tsai }; 2238f4ed8fcSChen-Yu Tsai 2248f4ed8fcSChen-Yu Tsai cluster1_opp: opp-table-cluster1 { 2258f4ed8fcSChen-Yu Tsai compatible = "operating-points-v2"; 2268f4ed8fcSChen-Yu Tsai opp-shared; 2278f4ed8fcSChen-Yu Tsai 2288f4ed8fcSChen-Yu Tsai opp-774000000 { 2298f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <774000000>; 2308f4ed8fcSChen-Yu Tsai opp-microvolt = <675000>; 2318f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_0>; 2328f4ed8fcSChen-Yu Tsai }; 2338f4ed8fcSChen-Yu Tsai 2348f4ed8fcSChen-Yu Tsai opp-835000000 { 2358f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <835000000>; 2368f4ed8fcSChen-Yu Tsai opp-microvolt = <693750>; 2378f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_1>; 2388f4ed8fcSChen-Yu Tsai }; 2398f4ed8fcSChen-Yu Tsai 2408f4ed8fcSChen-Yu Tsai opp-919000000 { 2418f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <919000000>; 2428f4ed8fcSChen-Yu Tsai opp-microvolt = <718750>; 2438f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_2>; 2448f4ed8fcSChen-Yu Tsai }; 2458f4ed8fcSChen-Yu Tsai 2468f4ed8fcSChen-Yu Tsai opp-1002000000 { 2478f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1002000000>; 2488f4ed8fcSChen-Yu Tsai opp-microvolt = <743750>; 2498f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_3>; 2508f4ed8fcSChen-Yu Tsai }; 2518f4ed8fcSChen-Yu Tsai 2528f4ed8fcSChen-Yu Tsai opp-1085000000 { 2538f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1085000000>; 2548f4ed8fcSChen-Yu Tsai opp-microvolt = <775000>; 2558f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_4>; 2568f4ed8fcSChen-Yu Tsai }; 2578f4ed8fcSChen-Yu Tsai 2588f4ed8fcSChen-Yu Tsai opp-1169000000 { 2598f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1169000000>; 2608f4ed8fcSChen-Yu Tsai opp-microvolt = <800000>; 2618f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_5>; 2628f4ed8fcSChen-Yu Tsai }; 2638f4ed8fcSChen-Yu Tsai 2648f4ed8fcSChen-Yu Tsai opp-1308000000 { 2658f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1308000000>; 2668f4ed8fcSChen-Yu Tsai opp-microvolt = <843750>; 2678f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_6>; 2688f4ed8fcSChen-Yu Tsai }; 2698f4ed8fcSChen-Yu Tsai 2708f4ed8fcSChen-Yu Tsai opp-1419000000 { 2718f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1419000000>; 2728f4ed8fcSChen-Yu Tsai opp-microvolt = <875000>; 2738f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_7>; 2748f4ed8fcSChen-Yu Tsai }; 2758f4ed8fcSChen-Yu Tsai 2768f4ed8fcSChen-Yu Tsai opp-1530000000 { 2778f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1530000000>; 2788f4ed8fcSChen-Yu Tsai opp-microvolt = <912500>; 2798f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_8>; 2808f4ed8fcSChen-Yu Tsai }; 2818f4ed8fcSChen-Yu Tsai 2828f4ed8fcSChen-Yu Tsai opp-1670000000 { 2838f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1670000000>; 2848f4ed8fcSChen-Yu Tsai opp-microvolt = <956250>; 2858f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_9>; 2868f4ed8fcSChen-Yu Tsai }; 2878f4ed8fcSChen-Yu Tsai 2888f4ed8fcSChen-Yu Tsai opp-1733000000 { 2898f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1733000000>; 2908f4ed8fcSChen-Yu Tsai opp-microvolt = <981250>; 2918f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_10>; 2928f4ed8fcSChen-Yu Tsai }; 2938f4ed8fcSChen-Yu Tsai 2948f4ed8fcSChen-Yu Tsai opp-1796000000 { 2958f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1796000000>; 2968f4ed8fcSChen-Yu Tsai opp-microvolt = <1012500>; 2978f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_11>; 2988f4ed8fcSChen-Yu Tsai }; 2998f4ed8fcSChen-Yu Tsai 3008f4ed8fcSChen-Yu Tsai opp-1860000000 { 3018f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1860000000>; 3028f4ed8fcSChen-Yu Tsai opp-microvolt = <1037500>; 3038f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_12>; 3048f4ed8fcSChen-Yu Tsai }; 3058f4ed8fcSChen-Yu Tsai 3068f4ed8fcSChen-Yu Tsai opp-1923000000 { 3078f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1923000000>; 3088f4ed8fcSChen-Yu Tsai opp-microvolt = <1062500>; 3098f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_13>; 3108f4ed8fcSChen-Yu Tsai }; 3118f4ed8fcSChen-Yu Tsai 3128f4ed8fcSChen-Yu Tsai cluster1_opp_14: opp-1986000000 { 3138f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <1986000000>; 3148f4ed8fcSChen-Yu Tsai opp-microvolt = <1093750>; 3158f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_14>; 3168f4ed8fcSChen-Yu Tsai }; 3178f4ed8fcSChen-Yu Tsai 3188f4ed8fcSChen-Yu Tsai cluster1_opp_15: opp-2050000000 { 3198f4ed8fcSChen-Yu Tsai opp-hz = /bits/ 64 <2050000000>; 3208f4ed8fcSChen-Yu Tsai opp-microvolt = <1118750>; 3218f4ed8fcSChen-Yu Tsai required-opps = <&cci_opp_15>; 3228f4ed8fcSChen-Yu Tsai }; 3238f4ed8fcSChen-Yu Tsai }; 3248f4ed8fcSChen-Yu Tsai 3252e78620bSAllen-KH Cheng cpus { 3262e78620bSAllen-KH Cheng #address-cells = <1>; 3272e78620bSAllen-KH Cheng #size-cells = <0>; 3282e78620bSAllen-KH Cheng 3292e78620bSAllen-KH Cheng cpu-map { 3302e78620bSAllen-KH Cheng cluster0 { 3312e78620bSAllen-KH Cheng core0 { 3322e78620bSAllen-KH Cheng cpu = <&cpu0>; 3332e78620bSAllen-KH Cheng }; 3342e78620bSAllen-KH Cheng 3352e78620bSAllen-KH Cheng core1 { 3362e78620bSAllen-KH Cheng cpu = <&cpu1>; 3372e78620bSAllen-KH Cheng }; 3382e78620bSAllen-KH Cheng 3392e78620bSAllen-KH Cheng core2 { 3402e78620bSAllen-KH Cheng cpu = <&cpu2>; 3412e78620bSAllen-KH Cheng }; 3422e78620bSAllen-KH Cheng 3432e78620bSAllen-KH Cheng core3 { 3442e78620bSAllen-KH Cheng cpu = <&cpu3>; 3452e78620bSAllen-KH Cheng }; 3462e78620bSAllen-KH Cheng 3472e78620bSAllen-KH Cheng core4 { 3482e78620bSAllen-KH Cheng cpu = <&cpu4>; 3492e78620bSAllen-KH Cheng }; 3502e78620bSAllen-KH Cheng 3512e78620bSAllen-KH Cheng core5 { 3522e78620bSAllen-KH Cheng cpu = <&cpu5>; 3532e78620bSAllen-KH Cheng }; 3542e78620bSAllen-KH Cheng 3551c473804SAngeloGioacchino Del Regno core6 { 3562e78620bSAllen-KH Cheng cpu = <&cpu6>; 3572e78620bSAllen-KH Cheng }; 3582e78620bSAllen-KH Cheng 3591c473804SAngeloGioacchino Del Regno core7 { 3602e78620bSAllen-KH Cheng cpu = <&cpu7>; 3612e78620bSAllen-KH Cheng }; 3622e78620bSAllen-KH Cheng }; 3632e78620bSAllen-KH Cheng }; 3642e78620bSAllen-KH Cheng 3652e78620bSAllen-KH Cheng cpu0: cpu@0 { 3662e78620bSAllen-KH Cheng device_type = "cpu"; 3672e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 3682e78620bSAllen-KH Cheng reg = <0x000>; 3692e78620bSAllen-KH Cheng enable-method = "psci"; 3702e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 3718f4ed8fcSChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 3728f4ed8fcSChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 3738f4ed8fcSChen-Yu Tsai clock-names = "cpu", "intermediate"; 3748f4ed8fcSChen-Yu Tsai operating-points-v2 = <&cluster0_opp>; 3758f4ed8fcSChen-Yu Tsai dynamic-power-coefficient = <84>; 3762e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 377f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 37870282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 37970282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 38070282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 38170282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 38270282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 38370282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 3842e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 3852e78620bSAllen-KH Cheng #cooling-cells = <2>; 38632dfbc03SChen-Yu Tsai mediatek,cci = <&cci>; 3872e78620bSAllen-KH Cheng }; 3882e78620bSAllen-KH Cheng 3892e78620bSAllen-KH Cheng cpu1: cpu@100 { 3902e78620bSAllen-KH Cheng device_type = "cpu"; 3912e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 3922e78620bSAllen-KH Cheng reg = <0x100>; 3932e78620bSAllen-KH Cheng enable-method = "psci"; 3942e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 3958f4ed8fcSChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 3968f4ed8fcSChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 3978f4ed8fcSChen-Yu Tsai clock-names = "cpu", "intermediate"; 3988f4ed8fcSChen-Yu Tsai operating-points-v2 = <&cluster0_opp>; 3998f4ed8fcSChen-Yu Tsai dynamic-power-coefficient = <84>; 4002e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 401f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 40270282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 40370282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 40470282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 40570282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 40670282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 40770282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 4082e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 4092e78620bSAllen-KH Cheng #cooling-cells = <2>; 41032dfbc03SChen-Yu Tsai mediatek,cci = <&cci>; 4112e78620bSAllen-KH Cheng }; 4122e78620bSAllen-KH Cheng 4132e78620bSAllen-KH Cheng cpu2: cpu@200 { 4142e78620bSAllen-KH Cheng device_type = "cpu"; 4152e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 4162e78620bSAllen-KH Cheng reg = <0x200>; 4172e78620bSAllen-KH Cheng enable-method = "psci"; 4182e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 4198f4ed8fcSChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 4208f4ed8fcSChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 4218f4ed8fcSChen-Yu Tsai clock-names = "cpu", "intermediate"; 4228f4ed8fcSChen-Yu Tsai operating-points-v2 = <&cluster0_opp>; 4238f4ed8fcSChen-Yu Tsai dynamic-power-coefficient = <84>; 4242e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 425f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 42670282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 42770282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 42870282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 42970282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 43070282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 43170282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 4322e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 4332e78620bSAllen-KH Cheng #cooling-cells = <2>; 43432dfbc03SChen-Yu Tsai mediatek,cci = <&cci>; 4352e78620bSAllen-KH Cheng }; 4362e78620bSAllen-KH Cheng 4372e78620bSAllen-KH Cheng cpu3: cpu@300 { 4382e78620bSAllen-KH Cheng device_type = "cpu"; 4392e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 4402e78620bSAllen-KH Cheng reg = <0x300>; 4412e78620bSAllen-KH Cheng enable-method = "psci"; 4422e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 4438f4ed8fcSChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 4448f4ed8fcSChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 4458f4ed8fcSChen-Yu Tsai clock-names = "cpu", "intermediate"; 4468f4ed8fcSChen-Yu Tsai operating-points-v2 = <&cluster0_opp>; 4478f4ed8fcSChen-Yu Tsai dynamic-power-coefficient = <84>; 4482e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 449f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 45070282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 45170282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 45270282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 45370282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 45470282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 45570282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 4562e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 4572e78620bSAllen-KH Cheng #cooling-cells = <2>; 45832dfbc03SChen-Yu Tsai mediatek,cci = <&cci>; 4592e78620bSAllen-KH Cheng }; 4602e78620bSAllen-KH Cheng 4612e78620bSAllen-KH Cheng cpu4: cpu@400 { 4622e78620bSAllen-KH Cheng device_type = "cpu"; 4632e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 4642e78620bSAllen-KH Cheng reg = <0x400>; 4652e78620bSAllen-KH Cheng enable-method = "psci"; 4662e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 4678f4ed8fcSChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 4688f4ed8fcSChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 4698f4ed8fcSChen-Yu Tsai clock-names = "cpu", "intermediate"; 4708f4ed8fcSChen-Yu Tsai operating-points-v2 = <&cluster0_opp>; 4718f4ed8fcSChen-Yu Tsai dynamic-power-coefficient = <84>; 4722e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 473f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 47470282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 47570282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 47670282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 47770282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 47870282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 47970282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 4802e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 4812e78620bSAllen-KH Cheng #cooling-cells = <2>; 48232dfbc03SChen-Yu Tsai mediatek,cci = <&cci>; 4832e78620bSAllen-KH Cheng }; 4842e78620bSAllen-KH Cheng 4852e78620bSAllen-KH Cheng cpu5: cpu@500 { 4862e78620bSAllen-KH Cheng device_type = "cpu"; 4872e78620bSAllen-KH Cheng compatible = "arm,cortex-a55"; 4882e78620bSAllen-KH Cheng reg = <0x500>; 4892e78620bSAllen-KH Cheng enable-method = "psci"; 4902e78620bSAllen-KH Cheng clock-frequency = <2000000000>; 4918f4ed8fcSChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 4928f4ed8fcSChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 4938f4ed8fcSChen-Yu Tsai clock-names = "cpu", "intermediate"; 4948f4ed8fcSChen-Yu Tsai operating-points-v2 = <&cluster0_opp>; 4958f4ed8fcSChen-Yu Tsai dynamic-power-coefficient = <84>; 4962e78620bSAllen-KH Cheng capacity-dmips-mhz = <382>; 497f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 49870282f31SAngeloGioacchino Del Regno i-cache-size = <32768>; 49970282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 50070282f31SAngeloGioacchino Del Regno i-cache-sets = <128>; 50170282f31SAngeloGioacchino Del Regno d-cache-size = <32768>; 50270282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 50370282f31SAngeloGioacchino Del Regno d-cache-sets = <128>; 5042e78620bSAllen-KH Cheng next-level-cache = <&l2_0>; 5052e78620bSAllen-KH Cheng #cooling-cells = <2>; 50632dfbc03SChen-Yu Tsai mediatek,cci = <&cci>; 5072e78620bSAllen-KH Cheng }; 5082e78620bSAllen-KH Cheng 5092e78620bSAllen-KH Cheng cpu6: cpu@600 { 5102e78620bSAllen-KH Cheng device_type = "cpu"; 5112e78620bSAllen-KH Cheng compatible = "arm,cortex-a76"; 5122e78620bSAllen-KH Cheng reg = <0x600>; 5132e78620bSAllen-KH Cheng enable-method = "psci"; 5142e78620bSAllen-KH Cheng clock-frequency = <2050000000>; 5158f4ed8fcSChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 5168f4ed8fcSChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 5178f4ed8fcSChen-Yu Tsai clock-names = "cpu", "intermediate"; 5188f4ed8fcSChen-Yu Tsai operating-points-v2 = <&cluster1_opp>; 5198f4ed8fcSChen-Yu Tsai dynamic-power-coefficient = <335>; 5202e78620bSAllen-KH Cheng capacity-dmips-mhz = <1024>; 521f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 52270282f31SAngeloGioacchino Del Regno i-cache-size = <65536>; 52370282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 52470282f31SAngeloGioacchino Del Regno i-cache-sets = <256>; 52570282f31SAngeloGioacchino Del Regno d-cache-size = <65536>; 52670282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 52770282f31SAngeloGioacchino Del Regno d-cache-sets = <256>; 5282e78620bSAllen-KH Cheng next-level-cache = <&l2_1>; 5292e78620bSAllen-KH Cheng #cooling-cells = <2>; 53032dfbc03SChen-Yu Tsai mediatek,cci = <&cci>; 5312e78620bSAllen-KH Cheng }; 5322e78620bSAllen-KH Cheng 5332e78620bSAllen-KH Cheng cpu7: cpu@700 { 5342e78620bSAllen-KH Cheng device_type = "cpu"; 5352e78620bSAllen-KH Cheng compatible = "arm,cortex-a76"; 5362e78620bSAllen-KH Cheng reg = <0x700>; 5372e78620bSAllen-KH Cheng enable-method = "psci"; 5382e78620bSAllen-KH Cheng clock-frequency = <2050000000>; 5398f4ed8fcSChen-Yu Tsai clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 5408f4ed8fcSChen-Yu Tsai <&apmixedsys CLK_APMIXED_MAINPLL>; 5418f4ed8fcSChen-Yu Tsai clock-names = "cpu", "intermediate"; 5428f4ed8fcSChen-Yu Tsai operating-points-v2 = <&cluster1_opp>; 5438f4ed8fcSChen-Yu Tsai dynamic-power-coefficient = <335>; 5442e78620bSAllen-KH Cheng capacity-dmips-mhz = <1024>; 545f3ca1580SAngeloGioacchino Del Regno cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 54670282f31SAngeloGioacchino Del Regno i-cache-size = <65536>; 54770282f31SAngeloGioacchino Del Regno i-cache-line-size = <64>; 54870282f31SAngeloGioacchino Del Regno i-cache-sets = <256>; 54970282f31SAngeloGioacchino Del Regno d-cache-size = <65536>; 55070282f31SAngeloGioacchino Del Regno d-cache-line-size = <64>; 55170282f31SAngeloGioacchino Del Regno d-cache-sets = <256>; 5522e78620bSAllen-KH Cheng next-level-cache = <&l2_1>; 5532e78620bSAllen-KH Cheng #cooling-cells = <2>; 55432dfbc03SChen-Yu Tsai mediatek,cci = <&cci>; 5552e78620bSAllen-KH Cheng }; 5562e78620bSAllen-KH Cheng 5572e78620bSAllen-KH Cheng idle-states { 5582e78620bSAllen-KH Cheng entry-method = "psci"; 5592e78620bSAllen-KH Cheng 560f3ca1580SAngeloGioacchino Del Regno cpu_ret_l: cpu-retention-l { 5612e78620bSAllen-KH Cheng compatible = "arm,idle-state"; 5622e78620bSAllen-KH Cheng arm,psci-suspend-param = <0x00010001>; 5632e78620bSAllen-KH Cheng local-timer-stop; 5642e78620bSAllen-KH Cheng entry-latency-us = <50>; 5652e78620bSAllen-KH Cheng exit-latency-us = <100>; 5662e78620bSAllen-KH Cheng min-residency-us = <1600>; 5672e78620bSAllen-KH Cheng }; 5682e78620bSAllen-KH Cheng 569f3ca1580SAngeloGioacchino Del Regno cpu_ret_b: cpu-retention-b { 5702e78620bSAllen-KH Cheng compatible = "arm,idle-state"; 5712e78620bSAllen-KH Cheng arm,psci-suspend-param = <0x00010001>; 5722e78620bSAllen-KH Cheng local-timer-stop; 5732e78620bSAllen-KH Cheng entry-latency-us = <50>; 5742e78620bSAllen-KH Cheng exit-latency-us = <100>; 5752e78620bSAllen-KH Cheng min-residency-us = <1400>; 5762e78620bSAllen-KH Cheng }; 5772e78620bSAllen-KH Cheng 578f3ca1580SAngeloGioacchino Del Regno cpu_off_l: cpu-off-l { 5792e78620bSAllen-KH Cheng compatible = "arm,idle-state"; 5802e78620bSAllen-KH Cheng arm,psci-suspend-param = <0x01010001>; 5812e78620bSAllen-KH Cheng local-timer-stop; 5822e78620bSAllen-KH Cheng entry-latency-us = <100>; 5832e78620bSAllen-KH Cheng exit-latency-us = <250>; 5842e78620bSAllen-KH Cheng min-residency-us = <2100>; 5852e78620bSAllen-KH Cheng }; 5862e78620bSAllen-KH Cheng 587f3ca1580SAngeloGioacchino Del Regno cpu_off_b: cpu-off-b { 5882e78620bSAllen-KH Cheng compatible = "arm,idle-state"; 5892e78620bSAllen-KH Cheng arm,psci-suspend-param = <0x01010001>; 5902e78620bSAllen-KH Cheng local-timer-stop; 5912e78620bSAllen-KH Cheng entry-latency-us = <100>; 5922e78620bSAllen-KH Cheng exit-latency-us = <250>; 5932e78620bSAllen-KH Cheng min-residency-us = <1900>; 5942e78620bSAllen-KH Cheng }; 5952e78620bSAllen-KH Cheng }; 5962e78620bSAllen-KH Cheng 5972e78620bSAllen-KH Cheng l2_0: l2-cache0 { 5982e78620bSAllen-KH Cheng compatible = "cache"; 599ce459b1dSPierre Gondois cache-level = <2>; 60070282f31SAngeloGioacchino Del Regno cache-size = <131072>; 60170282f31SAngeloGioacchino Del Regno cache-line-size = <64>; 60270282f31SAngeloGioacchino Del Regno cache-sets = <512>; 6032e78620bSAllen-KH Cheng next-level-cache = <&l3_0>; 604492061bfSKrzysztof Kozlowski cache-unified; 6052e78620bSAllen-KH Cheng }; 6062e78620bSAllen-KH Cheng 6072e78620bSAllen-KH Cheng l2_1: l2-cache1 { 6082e78620bSAllen-KH Cheng compatible = "cache"; 609ce459b1dSPierre Gondois cache-level = <2>; 61070282f31SAngeloGioacchino Del Regno cache-size = <262144>; 61170282f31SAngeloGioacchino Del Regno cache-line-size = <64>; 61270282f31SAngeloGioacchino Del Regno cache-sets = <512>; 6132e78620bSAllen-KH Cheng next-level-cache = <&l3_0>; 614492061bfSKrzysztof Kozlowski cache-unified; 6152e78620bSAllen-KH Cheng }; 6162e78620bSAllen-KH Cheng 6172e78620bSAllen-KH Cheng l3_0: l3-cache { 6182e78620bSAllen-KH Cheng compatible = "cache"; 619ce459b1dSPierre Gondois cache-level = <3>; 62070282f31SAngeloGioacchino Del Regno cache-size = <1048576>; 62170282f31SAngeloGioacchino Del Regno cache-line-size = <64>; 62270282f31SAngeloGioacchino Del Regno cache-sets = <1024>; 62370282f31SAngeloGioacchino Del Regno cache-unified; 6242e78620bSAllen-KH Cheng }; 6252e78620bSAllen-KH Cheng }; 6262e78620bSAllen-KH Cheng 627b391efbaSChen-Yu Tsai clk13m: fixed-factor-clock-13m { 628b391efbaSChen-Yu Tsai compatible = "fixed-factor-clock"; 6292e78620bSAllen-KH Cheng #clock-cells = <0>; 630b391efbaSChen-Yu Tsai clocks = <&clk26m>; 631b391efbaSChen-Yu Tsai clock-div = <2>; 632b391efbaSChen-Yu Tsai clock-mult = <1>; 6332e78620bSAllen-KH Cheng clock-output-names = "clk13m"; 6342e78620bSAllen-KH Cheng }; 6352e78620bSAllen-KH Cheng 6362e78620bSAllen-KH Cheng clk26m: oscillator-26m { 6372e78620bSAllen-KH Cheng compatible = "fixed-clock"; 6382e78620bSAllen-KH Cheng #clock-cells = <0>; 6392e78620bSAllen-KH Cheng clock-frequency = <26000000>; 6402e78620bSAllen-KH Cheng clock-output-names = "clk26m"; 6412e78620bSAllen-KH Cheng }; 6422e78620bSAllen-KH Cheng 6432e78620bSAllen-KH Cheng clk32k: oscillator-32k { 6442e78620bSAllen-KH Cheng compatible = "fixed-clock"; 6452e78620bSAllen-KH Cheng #clock-cells = <0>; 6462e78620bSAllen-KH Cheng clock-frequency = <32768>; 6472e78620bSAllen-KH Cheng clock-output-names = "clk32k"; 6482e78620bSAllen-KH Cheng }; 6492e78620bSAllen-KH Cheng 650f38ea593SChen-Yu Tsai gpu_opp_table: opp-table-gpu { 651f38ea593SChen-Yu Tsai compatible = "operating-points-v2"; 652f38ea593SChen-Yu Tsai 653f38ea593SChen-Yu Tsai opp-299000000 { 654f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <299000000>; 655f38ea593SChen-Yu Tsai opp-microvolt = <612500>; 656f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 657f38ea593SChen-Yu Tsai }; 658f38ea593SChen-Yu Tsai 659f38ea593SChen-Yu Tsai opp-332000000 { 660f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <332000000>; 661f38ea593SChen-Yu Tsai opp-microvolt = <625000>; 662f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 663f38ea593SChen-Yu Tsai }; 664f38ea593SChen-Yu Tsai 665f38ea593SChen-Yu Tsai opp-366000000 { 666f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <366000000>; 667f38ea593SChen-Yu Tsai opp-microvolt = <637500>; 668f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 669f38ea593SChen-Yu Tsai }; 670f38ea593SChen-Yu Tsai 671f38ea593SChen-Yu Tsai opp-400000000 { 672f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <400000000>; 673f38ea593SChen-Yu Tsai opp-microvolt = <643750>; 674f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 675f38ea593SChen-Yu Tsai }; 676f38ea593SChen-Yu Tsai 677f38ea593SChen-Yu Tsai opp-434000000 { 678f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <434000000>; 679f38ea593SChen-Yu Tsai opp-microvolt = <656250>; 680f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 681f38ea593SChen-Yu Tsai }; 682f38ea593SChen-Yu Tsai 683f38ea593SChen-Yu Tsai opp-484000000 { 684f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <484000000>; 685f38ea593SChen-Yu Tsai opp-microvolt = <668750>; 686f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 687f38ea593SChen-Yu Tsai }; 688f38ea593SChen-Yu Tsai 689f38ea593SChen-Yu Tsai opp-535000000 { 690f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <535000000>; 691f38ea593SChen-Yu Tsai opp-microvolt = <687500>; 692f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 693f38ea593SChen-Yu Tsai }; 694f38ea593SChen-Yu Tsai 695f38ea593SChen-Yu Tsai opp-586000000 { 696f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <586000000>; 697f38ea593SChen-Yu Tsai opp-microvolt = <700000>; 698f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 699f38ea593SChen-Yu Tsai }; 700f38ea593SChen-Yu Tsai 701f38ea593SChen-Yu Tsai opp-637000000 { 702f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <637000000>; 703f38ea593SChen-Yu Tsai opp-microvolt = <712500>; 704f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 705f38ea593SChen-Yu Tsai }; 706f38ea593SChen-Yu Tsai 707f38ea593SChen-Yu Tsai opp-690000000 { 708f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <690000000>; 709f38ea593SChen-Yu Tsai opp-microvolt = <737500>; 710f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 711f38ea593SChen-Yu Tsai }; 712f38ea593SChen-Yu Tsai 713f38ea593SChen-Yu Tsai opp-743000000 { 714f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <743000000>; 715f38ea593SChen-Yu Tsai opp-microvolt = <756250>; 716f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 717f38ea593SChen-Yu Tsai }; 718f38ea593SChen-Yu Tsai 719f38ea593SChen-Yu Tsai opp-796000000 { 720f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <796000000>; 721f38ea593SChen-Yu Tsai opp-microvolt = <781250>; 722f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 723f38ea593SChen-Yu Tsai }; 724f38ea593SChen-Yu Tsai 725f38ea593SChen-Yu Tsai opp-850000000 { 726f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <850000000>; 727f38ea593SChen-Yu Tsai opp-microvolt = <800000>; 728f38ea593SChen-Yu Tsai opp-supported-hw = <0xff>; 729f38ea593SChen-Yu Tsai }; 730f38ea593SChen-Yu Tsai 731f38ea593SChen-Yu Tsai opp-900000000-3 { 732f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <900000000>; 733f38ea593SChen-Yu Tsai opp-microvolt = <850000>; 734f38ea593SChen-Yu Tsai opp-supported-hw = <0x8>; 735f38ea593SChen-Yu Tsai }; 736f38ea593SChen-Yu Tsai 737f38ea593SChen-Yu Tsai opp-900000000-4 { 738f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <900000000>; 739f38ea593SChen-Yu Tsai opp-microvolt = <837500>; 740f38ea593SChen-Yu Tsai opp-supported-hw = <0x10>; 741f38ea593SChen-Yu Tsai }; 742f38ea593SChen-Yu Tsai 743f38ea593SChen-Yu Tsai opp-900000000-5 { 744f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <900000000>; 745f38ea593SChen-Yu Tsai opp-microvolt = <825000>; 746f38ea593SChen-Yu Tsai opp-supported-hw = <0x30>; 747f38ea593SChen-Yu Tsai }; 748f38ea593SChen-Yu Tsai 749f38ea593SChen-Yu Tsai opp-950000000-3 { 750f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <950000000>; 751f38ea593SChen-Yu Tsai opp-microvolt = <900000>; 752f38ea593SChen-Yu Tsai opp-supported-hw = <0x8>; 753f38ea593SChen-Yu Tsai }; 754f38ea593SChen-Yu Tsai 755f38ea593SChen-Yu Tsai opp-950000000-4 { 756f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <950000000>; 757f38ea593SChen-Yu Tsai opp-microvolt = <875000>; 758f38ea593SChen-Yu Tsai opp-supported-hw = <0x10>; 759f38ea593SChen-Yu Tsai }; 760f38ea593SChen-Yu Tsai 761f38ea593SChen-Yu Tsai opp-950000000-5 { 762f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <950000000>; 763f38ea593SChen-Yu Tsai opp-microvolt = <850000>; 764f38ea593SChen-Yu Tsai opp-supported-hw = <0x30>; 765f38ea593SChen-Yu Tsai }; 766f38ea593SChen-Yu Tsai 767f38ea593SChen-Yu Tsai opp-1000000000-3 { 768f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <1000000000>; 769f38ea593SChen-Yu Tsai opp-microvolt = <950000>; 770f38ea593SChen-Yu Tsai opp-supported-hw = <0x8>; 771f38ea593SChen-Yu Tsai }; 772f38ea593SChen-Yu Tsai 773f38ea593SChen-Yu Tsai opp-1000000000-4 { 774f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <1000000000>; 775f38ea593SChen-Yu Tsai opp-microvolt = <912500>; 776f38ea593SChen-Yu Tsai opp-supported-hw = <0x10>; 777f38ea593SChen-Yu Tsai }; 778f38ea593SChen-Yu Tsai 779f38ea593SChen-Yu Tsai opp-1000000000-5 { 780f38ea593SChen-Yu Tsai opp-hz = /bits/ 64 <1000000000>; 781f38ea593SChen-Yu Tsai opp-microvolt = <875000>; 782f38ea593SChen-Yu Tsai opp-supported-hw = <0x30>; 783f38ea593SChen-Yu Tsai }; 784f38ea593SChen-Yu Tsai }; 785f38ea593SChen-Yu Tsai 7862e78620bSAllen-KH Cheng pmu-a55 { 7872e78620bSAllen-KH Cheng compatible = "arm,cortex-a55-pmu"; 7882e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 7892e78620bSAllen-KH Cheng interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 7902e78620bSAllen-KH Cheng }; 7912e78620bSAllen-KH Cheng 7922e78620bSAllen-KH Cheng pmu-a76 { 7932e78620bSAllen-KH Cheng compatible = "arm,cortex-a76-pmu"; 7942e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 7952e78620bSAllen-KH Cheng interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 7962e78620bSAllen-KH Cheng }; 7972e78620bSAllen-KH Cheng 7982e78620bSAllen-KH Cheng psci { 7992e78620bSAllen-KH Cheng compatible = "arm,psci-1.0"; 8002e78620bSAllen-KH Cheng method = "smc"; 8012e78620bSAllen-KH Cheng }; 8022e78620bSAllen-KH Cheng 8032e78620bSAllen-KH Cheng timer { 8042e78620bSAllen-KH Cheng compatible = "arm,armv8-timer"; 8052e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 8062e78620bSAllen-KH Cheng interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 8072e78620bSAllen-KH Cheng <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 8082e78620bSAllen-KH Cheng <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 8092e78620bSAllen-KH Cheng <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 8102e78620bSAllen-KH Cheng }; 8112e78620bSAllen-KH Cheng 8122e78620bSAllen-KH Cheng soc { 8132e78620bSAllen-KH Cheng #address-cells = <2>; 8142e78620bSAllen-KH Cheng #size-cells = <2>; 8152e78620bSAllen-KH Cheng compatible = "simple-bus"; 816f5430284SYong Wu dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 8172e78620bSAllen-KH Cheng ranges; 8182e78620bSAllen-KH Cheng 8192e78620bSAllen-KH Cheng gic: interrupt-controller@c000000 { 8202e78620bSAllen-KH Cheng compatible = "arm,gic-v3"; 8212e78620bSAllen-KH Cheng #interrupt-cells = <4>; 8222e78620bSAllen-KH Cheng #redistributor-regions = <1>; 8232e78620bSAllen-KH Cheng interrupt-parent = <&gic>; 8242e78620bSAllen-KH Cheng interrupt-controller; 8252e78620bSAllen-KH Cheng reg = <0 0x0c000000 0 0x40000>, 8262e78620bSAllen-KH Cheng <0 0x0c040000 0 0x200000>; 8272e78620bSAllen-KH Cheng interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 8282e78620bSAllen-KH Cheng 8292e78620bSAllen-KH Cheng ppi-partitions { 8302e78620bSAllen-KH Cheng ppi_cluster0: interrupt-partition-0 { 8312e78620bSAllen-KH Cheng affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 8322e78620bSAllen-KH Cheng }; 8332e78620bSAllen-KH Cheng 8342e78620bSAllen-KH Cheng ppi_cluster1: interrupt-partition-1 { 8352e78620bSAllen-KH Cheng affinity = <&cpu6 &cpu7>; 8362e78620bSAllen-KH Cheng }; 8372e78620bSAllen-KH Cheng }; 8382e78620bSAllen-KH Cheng }; 8392e78620bSAllen-KH Cheng 8402e78620bSAllen-KH Cheng mcusys: syscon@c53a000 { 8412e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mcusys", "syscon"; 8422e78620bSAllen-KH Cheng reg = <0 0xc53a000 0 0x1000>; 8432e78620bSAllen-KH Cheng #clock-cells = <1>; 8442e78620bSAllen-KH Cheng }; 8452e78620bSAllen-KH Cheng 8462e78620bSAllen-KH Cheng topckgen: syscon@10000000 { 8472e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-topckgen", "syscon"; 8482e78620bSAllen-KH Cheng reg = <0 0x10000000 0 0x1000>; 8492e78620bSAllen-KH Cheng #clock-cells = <1>; 8502e78620bSAllen-KH Cheng }; 8512e78620bSAllen-KH Cheng 8522e78620bSAllen-KH Cheng infracfg_ao: syscon@10001000 { 8532e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 8542e78620bSAllen-KH Cheng reg = <0 0x10001000 0 0x1000>; 8552e78620bSAllen-KH Cheng #clock-cells = <1>; 8562e78620bSAllen-KH Cheng #reset-cells = <1>; 8572e78620bSAllen-KH Cheng }; 8582e78620bSAllen-KH Cheng 8592e78620bSAllen-KH Cheng pericfg: syscon@10003000 { 8602e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-pericfg", "syscon"; 8612e78620bSAllen-KH Cheng reg = <0 0x10003000 0 0x1000>; 8622e78620bSAllen-KH Cheng }; 8632e78620bSAllen-KH Cheng 8642e78620bSAllen-KH Cheng pio: pinctrl@10005000 { 8652e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-pinctrl"; 8662e78620bSAllen-KH Cheng reg = <0 0x10005000 0 0x1000>, 8672e78620bSAllen-KH Cheng <0 0x10002000 0 0x0200>, 8682e78620bSAllen-KH Cheng <0 0x10002200 0 0x0200>, 8692e78620bSAllen-KH Cheng <0 0x10002400 0 0x0200>, 8702e78620bSAllen-KH Cheng <0 0x10002600 0 0x0200>, 8712e78620bSAllen-KH Cheng <0 0x10002a00 0 0x0200>, 8722e78620bSAllen-KH Cheng <0 0x10002c00 0 0x0200>, 8732e78620bSAllen-KH Cheng <0 0x1000b000 0 0x1000>; 8742e78620bSAllen-KH Cheng reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 8752e78620bSAllen-KH Cheng "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 8762e78620bSAllen-KH Cheng gpio-controller; 8772e78620bSAllen-KH Cheng #gpio-cells = <2>; 8782e78620bSAllen-KH Cheng gpio-ranges = <&pio 0 0 185>; 8792e78620bSAllen-KH Cheng interrupt-controller; 8802e78620bSAllen-KH Cheng interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 8812e78620bSAllen-KH Cheng #interrupt-cells = <2>; 8822e78620bSAllen-KH Cheng }; 8832e78620bSAllen-KH Cheng 884d9e43c1eSAllen-KH Cheng scpsys: syscon@10006000 { 885d9e43c1eSAllen-KH Cheng compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 886d9e43c1eSAllen-KH Cheng reg = <0 0x10006000 0 0x1000>; 887d9e43c1eSAllen-KH Cheng 888d9e43c1eSAllen-KH Cheng /* System Power Manager */ 889d9e43c1eSAllen-KH Cheng spm: power-controller { 890d9e43c1eSAllen-KH Cheng compatible = "mediatek,mt8186-power-controller"; 891d9e43c1eSAllen-KH Cheng #address-cells = <1>; 892d9e43c1eSAllen-KH Cheng #size-cells = <0>; 893d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 894d9e43c1eSAllen-KH Cheng 895d9e43c1eSAllen-KH Cheng /* power domain of the SoC */ 896d9e43c1eSAllen-KH Cheng mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 897d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_MFG0>; 898d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MFG>; 899d9e43c1eSAllen-KH Cheng clock-names = "mfg00"; 900d9e43c1eSAllen-KH Cheng #address-cells = <1>; 901d9e43c1eSAllen-KH Cheng #size-cells = <0>; 902d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 903d9e43c1eSAllen-KH Cheng 904f38ea593SChen-Yu Tsai mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { 905d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_MFG1>; 906d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 907d9e43c1eSAllen-KH Cheng #address-cells = <1>; 908d9e43c1eSAllen-KH Cheng #size-cells = <0>; 909d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 910d9e43c1eSAllen-KH Cheng 911d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_MFG2 { 912d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_MFG2>; 913d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 914d9e43c1eSAllen-KH Cheng }; 915d9e43c1eSAllen-KH Cheng 916d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_MFG3 { 917d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_MFG3>; 918d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 919d9e43c1eSAllen-KH Cheng }; 920d9e43c1eSAllen-KH Cheng }; 921d9e43c1eSAllen-KH Cheng }; 922d9e43c1eSAllen-KH Cheng 923d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 924d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 925d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_SENINF>, 926d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF1>; 927b6eccbcbSEugen Hristev clock-names = "subsys-csirx-top0", 928b6eccbcbSEugen Hristev "subsys-csirx-top1"; 929d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 930d9e43c1eSAllen-KH Cheng }; 931d9e43c1eSAllen-KH Cheng 932d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_SSUSB { 933d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_SSUSB>; 9348781c3f4SNícolas F. R. A. Prado clocks = <&topckgen CLK_TOP_USB_TOP>, 9358781c3f4SNícolas F. R. A. Prado <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>; 9368781c3f4SNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck"; 937d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 938d9e43c1eSAllen-KH Cheng }; 939d9e43c1eSAllen-KH Cheng 940d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 941d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 9428781c3f4SNícolas F. R. A. Prado clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 9438781c3f4SNícolas F. R. A. Prado <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>; 9448781c3f4SNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck"; 945d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 946d9e43c1eSAllen-KH Cheng }; 947d9e43c1eSAllen-KH Cheng 948d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 949d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 950d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_AUDIODSP>, 951d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_ADSP_BUS>; 952b6eccbcbSEugen Hristev clock-names = "audioadsp", 953b6eccbcbSEugen Hristev "subsys-adsp-bus"; 954d9e43c1eSAllen-KH Cheng #address-cells = <1>; 955d9e43c1eSAllen-KH Cheng #size-cells = <0>; 956d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 957d9e43c1eSAllen-KH Cheng 958d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 959d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 960d9e43c1eSAllen-KH Cheng #address-cells = <1>; 961d9e43c1eSAllen-KH Cheng #size-cells = <0>; 962d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 963d9e43c1eSAllen-KH Cheng 964d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 965d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 966d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 967d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 968d9e43c1eSAllen-KH Cheng }; 969d9e43c1eSAllen-KH Cheng }; 970d9e43c1eSAllen-KH Cheng }; 971d9e43c1eSAllen-KH Cheng 972d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CONN_ON { 973d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CONN_ON>; 974d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 975d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 976d9e43c1eSAllen-KH Cheng }; 977d9e43c1eSAllen-KH Cheng 978d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_DIS { 979d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_DIS>; 980d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP>, 981d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_MDP>, 982d9e43c1eSAllen-KH Cheng <&mmsys CLK_MM_SMI_INFRA>, 983d9e43c1eSAllen-KH Cheng <&mmsys CLK_MM_SMI_COMMON>, 984d9e43c1eSAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, 985d9e43c1eSAllen-KH Cheng <&mmsys CLK_MM_SMI_IOMMU>; 986b6eccbcbSEugen Hristev clock-names = "disp", "mdp", 987b6eccbcbSEugen Hristev "subsys-smi-infra", 988b6eccbcbSEugen Hristev "subsys-smi-common", 989b6eccbcbSEugen Hristev "subsys-smi-gals", 990b6eccbcbSEugen Hristev "subsys-smi-iommu"; 991d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 992d9e43c1eSAllen-KH Cheng #address-cells = <1>; 993d9e43c1eSAllen-KH Cheng #size-cells = <0>; 994d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 995d9e43c1eSAllen-KH Cheng 996d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_VDEC { 997d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_VDEC>; 998d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_VDEC>, 999d9e43c1eSAllen-KH Cheng <&vdecsys CLK_VDEC_LARB1_CKEN>; 1000d9e43c1eSAllen-KH Cheng clock-names = "vdec0", "larb"; 1001d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 1002d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 1003d9e43c1eSAllen-KH Cheng }; 1004d9e43c1eSAllen-KH Cheng 1005d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CAM { 1006d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CAM>; 1007b6eccbcbSEugen Hristev clocks = <&topckgen CLK_TOP_SENINF>, 1008d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF1>, 1009d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF2>, 1010d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_SENINF3>, 1011b6eccbcbSEugen Hristev <&camsys CLK_CAM2MM_GALS>, 1012d9e43c1eSAllen-KH Cheng <&topckgen CLK_TOP_CAMTM>, 1013b6eccbcbSEugen Hristev <&topckgen CLK_TOP_CAM>; 1014b6eccbcbSEugen Hristev clock-names = "cam0", "cam1", "cam2", 1015b6eccbcbSEugen Hristev "cam3", "gals", 1016b6eccbcbSEugen Hristev "subsys-cam-tm", 1017b6eccbcbSEugen Hristev "subsys-cam-top"; 1018d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 1019d9e43c1eSAllen-KH Cheng #address-cells = <1>; 1020d9e43c1eSAllen-KH Cheng #size-cells = <0>; 1021d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 1022d9e43c1eSAllen-KH Cheng 1023d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 1024d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 1025d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 1026d9e43c1eSAllen-KH Cheng }; 1027d9e43c1eSAllen-KH Cheng 1028d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 1029d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 1030d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 1031d9e43c1eSAllen-KH Cheng }; 1032d9e43c1eSAllen-KH Cheng }; 1033d9e43c1eSAllen-KH Cheng 1034d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_IMG { 1035d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_IMG>; 1036b6eccbcbSEugen Hristev clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1037b6eccbcbSEugen Hristev <&topckgen CLK_TOP_IMG1>; 1038b6eccbcbSEugen Hristev clock-names = "gals", "subsys-img-top"; 1039d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 1040d9e43c1eSAllen-KH Cheng #address-cells = <1>; 1041d9e43c1eSAllen-KH Cheng #size-cells = <0>; 1042d9e43c1eSAllen-KH Cheng #power-domain-cells = <1>; 1043d9e43c1eSAllen-KH Cheng 1044d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_IMG2 { 1045d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_IMG2>; 1046d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 1047d9e43c1eSAllen-KH Cheng }; 1048d9e43c1eSAllen-KH Cheng }; 1049d9e43c1eSAllen-KH Cheng 1050d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_IPE { 1051d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_IPE>; 1052d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_IPE>, 1053d9e43c1eSAllen-KH Cheng <&ipesys CLK_IPE_LARB19>, 1054d9e43c1eSAllen-KH Cheng <&ipesys CLK_IPE_LARB20>, 1055d9e43c1eSAllen-KH Cheng <&ipesys CLK_IPE_SMI_SUBCOM>, 1056d9e43c1eSAllen-KH Cheng <&ipesys CLK_IPE_GALS_IPE>; 1057b6eccbcbSEugen Hristev clock-names = "subsys-ipe-top", 1058b6eccbcbSEugen Hristev "subsys-ipe-larb0", 1059b6eccbcbSEugen Hristev "subsys-ipe-larb1", 1060b6eccbcbSEugen Hristev "subsys-ipe-smi", 1061b6eccbcbSEugen Hristev "subsys-ipe-gals"; 1062d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 1063d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 1064d9e43c1eSAllen-KH Cheng }; 1065d9e43c1eSAllen-KH Cheng 1066d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_VENC { 1067d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_VENC>; 1068d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_VENC>, 1069d9e43c1eSAllen-KH Cheng <&vencsys CLK_VENC_CKE1_VENC>; 1070b5d11a01SEugen Hristev clock-names = "venc0", "subsys-larb"; 1071d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 1072d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 1073d9e43c1eSAllen-KH Cheng }; 1074d9e43c1eSAllen-KH Cheng 1075d9e43c1eSAllen-KH Cheng power-domain@MT8186_POWER_DOMAIN_WPE { 1076d9e43c1eSAllen-KH Cheng reg = <MT8186_POWER_DOMAIN_WPE>; 1077d9e43c1eSAllen-KH Cheng clocks = <&topckgen CLK_TOP_WPE>, 1078d9e43c1eSAllen-KH Cheng <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1079d9e43c1eSAllen-KH Cheng <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 1080b6eccbcbSEugen Hristev clock-names = "wpe0", 1081b6eccbcbSEugen Hristev "subsys-larb-ck", 1082b6eccbcbSEugen Hristev "subsys-larb-pclk"; 1083d9e43c1eSAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 1084d9e43c1eSAllen-KH Cheng #power-domain-cells = <0>; 1085d9e43c1eSAllen-KH Cheng }; 1086d9e43c1eSAllen-KH Cheng }; 1087d9e43c1eSAllen-KH Cheng }; 1088d9e43c1eSAllen-KH Cheng }; 1089d9e43c1eSAllen-KH Cheng 10902e78620bSAllen-KH Cheng watchdog: watchdog@10007000 { 1091e5e96162SAngeloGioacchino Del Regno compatible = "mediatek,mt8186-wdt"; 10922e78620bSAllen-KH Cheng mediatek,disable-extrst; 10932e78620bSAllen-KH Cheng reg = <0 0x10007000 0 0x1000>; 10942e78620bSAllen-KH Cheng #reset-cells = <1>; 10952e78620bSAllen-KH Cheng }; 10962e78620bSAllen-KH Cheng 10972e78620bSAllen-KH Cheng apmixedsys: syscon@1000c000 { 10982e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-apmixedsys", "syscon"; 10992e78620bSAllen-KH Cheng reg = <0 0x1000c000 0 0x1000>; 11002e78620bSAllen-KH Cheng #clock-cells = <1>; 11012e78620bSAllen-KH Cheng }; 11022e78620bSAllen-KH Cheng 11032e78620bSAllen-KH Cheng pwrap: pwrap@1000d000 { 11042e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-pwrap", "syscon"; 11052e78620bSAllen-KH Cheng reg = <0 0x1000d000 0 0x1000>; 11062e78620bSAllen-KH Cheng reg-names = "pwrap"; 11072e78620bSAllen-KH Cheng interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 11082e78620bSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 11092e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 11102e78620bSAllen-KH Cheng clock-names = "spi", "wrap"; 11112e78620bSAllen-KH Cheng }; 11122e78620bSAllen-KH Cheng 111336cfc08fSAllen-KH Cheng spmi: spmi@10015000 { 111436cfc08fSAllen-KH Cheng compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 111536cfc08fSAllen-KH Cheng reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 111636cfc08fSAllen-KH Cheng reg-names = "pmif", "spmimst"; 111736cfc08fSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 111836cfc08fSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 111936cfc08fSAllen-KH Cheng <&topckgen CLK_TOP_SPMI_MST>; 112036cfc08fSAllen-KH Cheng clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 112136cfc08fSAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 112236cfc08fSAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 112336cfc08fSAllen-KH Cheng interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 112436cfc08fSAllen-KH Cheng <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 112536cfc08fSAllen-KH Cheng status = "disabled"; 112636cfc08fSAllen-KH Cheng }; 112736cfc08fSAllen-KH Cheng 11282e78620bSAllen-KH Cheng systimer: timer@10017000 { 11292e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-timer", 11302e78620bSAllen-KH Cheng "mediatek,mt6765-timer"; 11312e78620bSAllen-KH Cheng reg = <0 0x10017000 0 0x1000>; 11322e78620bSAllen-KH Cheng interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 11332e78620bSAllen-KH Cheng clocks = <&clk13m>; 11342e78620bSAllen-KH Cheng }; 11352e78620bSAllen-KH Cheng 113641218847SAllen-KH Cheng gce: mailbox@1022c000 { 113741218847SAllen-KH Cheng compatible = "mediatek,mt8186-gce"; 113841218847SAllen-KH Cheng reg = <0 0X1022c000 0 0x4000>; 113941218847SAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 114041218847SAllen-KH Cheng clock-names = "gce"; 114141218847SAllen-KH Cheng interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 114241218847SAllen-KH Cheng #mbox-cells = <2>; 114341218847SAllen-KH Cheng }; 114441218847SAllen-KH Cheng 11452e78620bSAllen-KH Cheng scp: scp@10500000 { 11462e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-scp"; 11472e78620bSAllen-KH Cheng reg = <0 0x10500000 0 0x40000>, 11482e78620bSAllen-KH Cheng <0 0x105c0000 0 0x19080>; 11492e78620bSAllen-KH Cheng reg-names = "sram", "cfg"; 11502e78620bSAllen-KH Cheng interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 11512e78620bSAllen-KH Cheng }; 11522e78620bSAllen-KH Cheng 11534dad4f32SAllen-KH Cheng adsp: adsp@10680000 { 11544dad4f32SAllen-KH Cheng compatible = "mediatek,mt8186-dsp"; 11554dad4f32SAllen-KH Cheng reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 11564dad4f32SAllen-KH Cheng <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 11574dad4f32SAllen-KH Cheng reg-names = "cfg", "sram", "sec", "bus"; 11584dad4f32SAllen-KH Cheng clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 11594dad4f32SAllen-KH Cheng clock-names = "audiodsp", "adsp_bus"; 11604dad4f32SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 11614dad4f32SAllen-KH Cheng <&topckgen CLK_TOP_ADSP_BUS>; 11624dad4f32SAllen-KH Cheng assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 11634dad4f32SAllen-KH Cheng mbox-names = "rx", "tx"; 11644dad4f32SAllen-KH Cheng mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 11654dad4f32SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 11664dad4f32SAllen-KH Cheng status = "disabled"; 11674dad4f32SAllen-KH Cheng }; 11684dad4f32SAllen-KH Cheng 1169f8fa25bfSEugen Hristev adsp_mailbox0: mailbox@10686100 { 1170379cf0e6SAllen-KH Cheng compatible = "mediatek,mt8186-adsp-mbox"; 1171379cf0e6SAllen-KH Cheng #mbox-cells = <0>; 1172379cf0e6SAllen-KH Cheng reg = <0 0x10686100 0 0x1000>; 1173379cf0e6SAllen-KH Cheng interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 1174379cf0e6SAllen-KH Cheng }; 1175379cf0e6SAllen-KH Cheng 1176f8fa25bfSEugen Hristev adsp_mailbox1: mailbox@10687100 { 1177379cf0e6SAllen-KH Cheng compatible = "mediatek,mt8186-adsp-mbox"; 1178379cf0e6SAllen-KH Cheng #mbox-cells = <0>; 1179379cf0e6SAllen-KH Cheng reg = <0 0x10687100 0 0x1000>; 1180379cf0e6SAllen-KH Cheng interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 1181379cf0e6SAllen-KH Cheng }; 1182379cf0e6SAllen-KH Cheng 11832e78620bSAllen-KH Cheng nor_flash: spi@11000000 { 11842e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-nor"; 11852e78620bSAllen-KH Cheng reg = <0 0x11000000 0 0x1000>; 11862e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_SPINOR>, 11872e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPINOR>, 11882e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 11892e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 11902e78620bSAllen-KH Cheng clock-names = "spi", "sf", "axi", "axi_s"; 11912e78620bSAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 11922e78620bSAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 11932e78620bSAllen-KH Cheng interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 11942e78620bSAllen-KH Cheng status = "disabled"; 11952e78620bSAllen-KH Cheng }; 11962e78620bSAllen-KH Cheng 11972e78620bSAllen-KH Cheng auxadc: adc@11001000 { 11982e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 11992e78620bSAllen-KH Cheng reg = <0 0x11001000 0 0x1000>; 12002e78620bSAllen-KH Cheng #io-channel-cells = <1>; 12012e78620bSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 12022e78620bSAllen-KH Cheng clock-names = "main"; 12032e78620bSAllen-KH Cheng }; 12042e78620bSAllen-KH Cheng 12052e78620bSAllen-KH Cheng uart0: serial@11002000 { 12062e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-uart", 12072e78620bSAllen-KH Cheng "mediatek,mt6577-uart"; 12082e78620bSAllen-KH Cheng reg = <0 0x11002000 0 0x1000>; 12092e78620bSAllen-KH Cheng interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 12102e78620bSAllen-KH Cheng clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 12112e78620bSAllen-KH Cheng clock-names = "baud", "bus"; 12122e78620bSAllen-KH Cheng status = "disabled"; 12132e78620bSAllen-KH Cheng }; 12142e78620bSAllen-KH Cheng 12152e78620bSAllen-KH Cheng uart1: serial@11003000 { 12162e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-uart", 12172e78620bSAllen-KH Cheng "mediatek,mt6577-uart"; 12182e78620bSAllen-KH Cheng reg = <0 0x11003000 0 0x1000>; 12192e78620bSAllen-KH Cheng interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 12202e78620bSAllen-KH Cheng clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 12212e78620bSAllen-KH Cheng clock-names = "baud", "bus"; 12222e78620bSAllen-KH Cheng status = "disabled"; 12232e78620bSAllen-KH Cheng }; 12242e78620bSAllen-KH Cheng 12252e78620bSAllen-KH Cheng i2c0: i2c@11007000 { 12262e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 12272e78620bSAllen-KH Cheng reg = <0 0x11007000 0 0x1000>, 12282e78620bSAllen-KH Cheng <0 0x10200100 0 0x100>; 12292e78620bSAllen-KH Cheng interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 12302e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 12312e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 12322e78620bSAllen-KH Cheng clock-names = "main", "dma"; 12332e78620bSAllen-KH Cheng clock-div = <1>; 12342e78620bSAllen-KH Cheng #address-cells = <1>; 12352e78620bSAllen-KH Cheng #size-cells = <0>; 12362e78620bSAllen-KH Cheng status = "disabled"; 12372e78620bSAllen-KH Cheng }; 12382e78620bSAllen-KH Cheng 12392e78620bSAllen-KH Cheng i2c1: i2c@11008000 { 12402e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 12412e78620bSAllen-KH Cheng reg = <0 0x11008000 0 0x1000>, 12422e78620bSAllen-KH Cheng <0 0x10200200 0 0x100>; 12432e78620bSAllen-KH Cheng interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 12442e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 12452e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 12462e78620bSAllen-KH Cheng clock-names = "main", "dma"; 12472e78620bSAllen-KH Cheng clock-div = <1>; 12482e78620bSAllen-KH Cheng #address-cells = <1>; 12492e78620bSAllen-KH Cheng #size-cells = <0>; 12502e78620bSAllen-KH Cheng status = "disabled"; 12512e78620bSAllen-KH Cheng }; 12522e78620bSAllen-KH Cheng 12532e78620bSAllen-KH Cheng i2c2: i2c@11009000 { 12542e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 12552e78620bSAllen-KH Cheng reg = <0 0x11009000 0 0x1000>, 12562e78620bSAllen-KH Cheng <0 0x10200300 0 0x180>; 12572e78620bSAllen-KH Cheng interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 12582e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 12592e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 12602e78620bSAllen-KH Cheng clock-names = "main", "dma"; 12612e78620bSAllen-KH Cheng clock-div = <1>; 12622e78620bSAllen-KH Cheng #address-cells = <1>; 12632e78620bSAllen-KH Cheng #size-cells = <0>; 12642e78620bSAllen-KH Cheng status = "disabled"; 12652e78620bSAllen-KH Cheng }; 12662e78620bSAllen-KH Cheng 12672e78620bSAllen-KH Cheng i2c3: i2c@1100f000 { 12682e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 12692e78620bSAllen-KH Cheng reg = <0 0x1100f000 0 0x1000>, 12702e78620bSAllen-KH Cheng <0 0x10200480 0 0x100>; 12712e78620bSAllen-KH Cheng interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 12722e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 12732e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 12742e78620bSAllen-KH Cheng clock-names = "main", "dma"; 12752e78620bSAllen-KH Cheng clock-div = <1>; 12762e78620bSAllen-KH Cheng #address-cells = <1>; 12772e78620bSAllen-KH Cheng #size-cells = <0>; 12782e78620bSAllen-KH Cheng status = "disabled"; 12792e78620bSAllen-KH Cheng }; 12802e78620bSAllen-KH Cheng 12812e78620bSAllen-KH Cheng i2c4: i2c@11011000 { 12822e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 12832e78620bSAllen-KH Cheng reg = <0 0x11011000 0 0x1000>, 12842e78620bSAllen-KH Cheng <0 0x10200580 0 0x180>; 12852e78620bSAllen-KH Cheng interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 12862e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 12872e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 12882e78620bSAllen-KH Cheng clock-names = "main", "dma"; 12892e78620bSAllen-KH Cheng clock-div = <1>; 12902e78620bSAllen-KH Cheng #address-cells = <1>; 12912e78620bSAllen-KH Cheng #size-cells = <0>; 12922e78620bSAllen-KH Cheng status = "disabled"; 12932e78620bSAllen-KH Cheng }; 12942e78620bSAllen-KH Cheng 12952e78620bSAllen-KH Cheng i2c5: i2c@11016000 { 12962e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 12972e78620bSAllen-KH Cheng reg = <0 0x11016000 0 0x1000>, 12982e78620bSAllen-KH Cheng <0 0x10200700 0 0x100>; 12992e78620bSAllen-KH Cheng interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 13002e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 13012e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 13022e78620bSAllen-KH Cheng clock-names = "main", "dma"; 13032e78620bSAllen-KH Cheng clock-div = <1>; 13042e78620bSAllen-KH Cheng #address-cells = <1>; 13052e78620bSAllen-KH Cheng #size-cells = <0>; 13062e78620bSAllen-KH Cheng status = "disabled"; 13072e78620bSAllen-KH Cheng }; 13082e78620bSAllen-KH Cheng 13092e78620bSAllen-KH Cheng i2c6: i2c@1100d000 { 13102e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 13112e78620bSAllen-KH Cheng reg = <0 0x1100d000 0 0x1000>, 13122e78620bSAllen-KH Cheng <0 0x10200800 0 0x100>; 13132e78620bSAllen-KH Cheng interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 13142e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 13152e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 13162e78620bSAllen-KH Cheng clock-names = "main", "dma"; 13172e78620bSAllen-KH Cheng clock-div = <1>; 13182e78620bSAllen-KH Cheng #address-cells = <1>; 13192e78620bSAllen-KH Cheng #size-cells = <0>; 13202e78620bSAllen-KH Cheng status = "disabled"; 13212e78620bSAllen-KH Cheng }; 13222e78620bSAllen-KH Cheng 13232e78620bSAllen-KH Cheng i2c7: i2c@11004000 { 13242e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 13252e78620bSAllen-KH Cheng reg = <0 0x11004000 0 0x1000>, 13262e78620bSAllen-KH Cheng <0 0x10200900 0 0x180>; 13272e78620bSAllen-KH Cheng interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 13282e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 13292e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 13302e78620bSAllen-KH Cheng clock-names = "main", "dma"; 13312e78620bSAllen-KH Cheng clock-div = <1>; 13322e78620bSAllen-KH Cheng #address-cells = <1>; 13332e78620bSAllen-KH Cheng #size-cells = <0>; 13342e78620bSAllen-KH Cheng status = "disabled"; 13352e78620bSAllen-KH Cheng }; 13362e78620bSAllen-KH Cheng 13372e78620bSAllen-KH Cheng i2c8: i2c@11005000 { 13382e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 13392e78620bSAllen-KH Cheng reg = <0 0x11005000 0 0x1000>, 13402e78620bSAllen-KH Cheng <0 0x10200A80 0 0x180>; 13412e78620bSAllen-KH Cheng interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 13422e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 13432e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 13442e78620bSAllen-KH Cheng clock-names = "main", "dma"; 13452e78620bSAllen-KH Cheng clock-div = <1>; 13462e78620bSAllen-KH Cheng #address-cells = <1>; 13472e78620bSAllen-KH Cheng #size-cells = <0>; 13482e78620bSAllen-KH Cheng status = "disabled"; 13492e78620bSAllen-KH Cheng }; 13502e78620bSAllen-KH Cheng 13512e78620bSAllen-KH Cheng spi0: spi@1100a000 { 13522e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 13532e78620bSAllen-KH Cheng #address-cells = <1>; 13542e78620bSAllen-KH Cheng #size-cells = <0>; 13552e78620bSAllen-KH Cheng reg = <0 0x1100a000 0 0x1000>; 13562e78620bSAllen-KH Cheng interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 13572e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 13582e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 13592e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI0>; 13602e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 13612e78620bSAllen-KH Cheng status = "disabled"; 13622e78620bSAllen-KH Cheng }; 13632e78620bSAllen-KH Cheng 13642e78620bSAllen-KH Cheng pwm0: pwm@1100e000 { 13652e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 13662e78620bSAllen-KH Cheng reg = <0 0x1100e000 0 0x1000>; 13672e78620bSAllen-KH Cheng interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 13682e78620bSAllen-KH Cheng #pwm-cells = <2>; 13692e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_DISP_PWM>, 13702e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 13712e78620bSAllen-KH Cheng clock-names = "main", "mm"; 13722e78620bSAllen-KH Cheng status = "disabled"; 13732e78620bSAllen-KH Cheng }; 13742e78620bSAllen-KH Cheng 13752e78620bSAllen-KH Cheng spi1: spi@11010000 { 13762e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 13772e78620bSAllen-KH Cheng #address-cells = <1>; 13782e78620bSAllen-KH Cheng #size-cells = <0>; 13792e78620bSAllen-KH Cheng reg = <0 0x11010000 0 0x1000>; 13802e78620bSAllen-KH Cheng interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 13812e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 13822e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 13832e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI1>; 13842e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 13852e78620bSAllen-KH Cheng status = "disabled"; 13862e78620bSAllen-KH Cheng }; 13872e78620bSAllen-KH Cheng 13882e78620bSAllen-KH Cheng spi2: spi@11012000 { 13892e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 13902e78620bSAllen-KH Cheng #address-cells = <1>; 13912e78620bSAllen-KH Cheng #size-cells = <0>; 13922e78620bSAllen-KH Cheng reg = <0 0x11012000 0 0x1000>; 13932e78620bSAllen-KH Cheng interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 13942e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 13952e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 13962e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI2>; 13972e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 13982e78620bSAllen-KH Cheng status = "disabled"; 13992e78620bSAllen-KH Cheng }; 14002e78620bSAllen-KH Cheng 14012e78620bSAllen-KH Cheng spi3: spi@11013000 { 14022e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 14032e78620bSAllen-KH Cheng #address-cells = <1>; 14042e78620bSAllen-KH Cheng #size-cells = <0>; 14052e78620bSAllen-KH Cheng reg = <0 0x11013000 0 0x1000>; 14062e78620bSAllen-KH Cheng interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 14072e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 14082e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 14092e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI3>; 14102e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 14112e78620bSAllen-KH Cheng status = "disabled"; 14122e78620bSAllen-KH Cheng }; 14132e78620bSAllen-KH Cheng 14142e78620bSAllen-KH Cheng spi4: spi@11014000 { 14152e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 14162e78620bSAllen-KH Cheng #address-cells = <1>; 14172e78620bSAllen-KH Cheng #size-cells = <0>; 14182e78620bSAllen-KH Cheng reg = <0 0x11014000 0 0x1000>; 14192e78620bSAllen-KH Cheng interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 14202e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 14212e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 14222e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI4>; 14232e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 14242e78620bSAllen-KH Cheng status = "disabled"; 14252e78620bSAllen-KH Cheng }; 14262e78620bSAllen-KH Cheng 14272e78620bSAllen-KH Cheng spi5: spi@11015000 { 14282e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 14292e78620bSAllen-KH Cheng #address-cells = <1>; 14302e78620bSAllen-KH Cheng #size-cells = <0>; 14312e78620bSAllen-KH Cheng reg = <0 0x11015000 0 0x1000>; 14322e78620bSAllen-KH Cheng interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 14332e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 14342e78620bSAllen-KH Cheng <&topckgen CLK_TOP_SPI>, 14352e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SPI5>; 14362e78620bSAllen-KH Cheng clock-names = "parent-clk", "sel-clk", "spi-clk"; 14372e78620bSAllen-KH Cheng status = "disabled"; 14382e78620bSAllen-KH Cheng }; 14392e78620bSAllen-KH Cheng 14402e78620bSAllen-KH Cheng imp_iic_wrap: clock-controller@11017000 { 14412e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-imp_iic_wrap"; 14422e78620bSAllen-KH Cheng reg = <0 0x11017000 0 0x1000>; 14432e78620bSAllen-KH Cheng #clock-cells = <1>; 14442e78620bSAllen-KH Cheng }; 14452e78620bSAllen-KH Cheng 14462e78620bSAllen-KH Cheng uart2: serial@11018000 { 14472e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-uart", 14482e78620bSAllen-KH Cheng "mediatek,mt6577-uart"; 14492e78620bSAllen-KH Cheng reg = <0 0x11018000 0 0x1000>; 14502e78620bSAllen-KH Cheng interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 14512e78620bSAllen-KH Cheng clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 14522e78620bSAllen-KH Cheng clock-names = "baud", "bus"; 14532e78620bSAllen-KH Cheng status = "disabled"; 14542e78620bSAllen-KH Cheng }; 14552e78620bSAllen-KH Cheng 14562e78620bSAllen-KH Cheng i2c9: i2c@11019000 { 14572e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-i2c"; 14582e78620bSAllen-KH Cheng reg = <0 0x11019000 0 0x1000>, 14592e78620bSAllen-KH Cheng <0 0x10200c00 0 0x180>; 14602e78620bSAllen-KH Cheng interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 14612e78620bSAllen-KH Cheng clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 14622e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 14632e78620bSAllen-KH Cheng clock-names = "main", "dma"; 14642e78620bSAllen-KH Cheng clock-div = <1>; 14652e78620bSAllen-KH Cheng #address-cells = <1>; 14662e78620bSAllen-KH Cheng #size-cells = <0>; 14672e78620bSAllen-KH Cheng status = "disabled"; 14682e78620bSAllen-KH Cheng }; 14692e78620bSAllen-KH Cheng 147018942d29SAllen-KH Cheng afe: audio-controller@11210000 { 147118942d29SAllen-KH Cheng compatible = "mediatek,mt8186-sound"; 147218942d29SAllen-KH Cheng reg = <0 0x11210000 0 0x2000>; 147318942d29SAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 147418942d29SAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 147518942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO>, 147618942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_INTBUS>, 147718942d29SAllen-KH Cheng <&topckgen CLK_TOP_MAINPLL_D2_D4>, 147818942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_1>, 147918942d29SAllen-KH Cheng <&apmixedsys CLK_APMIXED_APLL1>, 148018942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_2>, 148118942d29SAllen-KH Cheng <&apmixedsys CLK_APMIXED_APLL2>, 148218942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN1>, 148318942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL1_D8>, 148418942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUD_ENGEN2>, 148518942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL2_D8>, 148618942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 148718942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 148818942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 148918942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 149018942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 149118942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV0>, 149218942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV1>, 149318942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV2>, 149418942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV4>, 149518942d29SAllen-KH Cheng <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 149618942d29SAllen-KH Cheng <&topckgen CLK_TOP_AUDIO_H>, 149718942d29SAllen-KH Cheng <&clk26m>; 149818942d29SAllen-KH Cheng clock-names = "aud_infra_clk", 149918942d29SAllen-KH Cheng "mtkaif_26m_clk", 150018942d29SAllen-KH Cheng "top_mux_audio", 150118942d29SAllen-KH Cheng "top_mux_audio_int", 150218942d29SAllen-KH Cheng "top_mainpll_d2_d4", 150318942d29SAllen-KH Cheng "top_mux_aud_1", 150418942d29SAllen-KH Cheng "top_apll1_ck", 150518942d29SAllen-KH Cheng "top_mux_aud_2", 150618942d29SAllen-KH Cheng "top_apll2_ck", 150718942d29SAllen-KH Cheng "top_mux_aud_eng1", 150818942d29SAllen-KH Cheng "top_apll1_d8", 150918942d29SAllen-KH Cheng "top_mux_aud_eng2", 151018942d29SAllen-KH Cheng "top_apll2_d8", 151118942d29SAllen-KH Cheng "top_i2s0_m_sel", 151218942d29SAllen-KH Cheng "top_i2s1_m_sel", 151318942d29SAllen-KH Cheng "top_i2s2_m_sel", 151418942d29SAllen-KH Cheng "top_i2s4_m_sel", 151518942d29SAllen-KH Cheng "top_tdm_m_sel", 151618942d29SAllen-KH Cheng "top_apll12_div0", 151718942d29SAllen-KH Cheng "top_apll12_div1", 151818942d29SAllen-KH Cheng "top_apll12_div2", 151918942d29SAllen-KH Cheng "top_apll12_div4", 152018942d29SAllen-KH Cheng "top_apll12_div_tdm", 152118942d29SAllen-KH Cheng "top_mux_audio_h", 152218942d29SAllen-KH Cheng "top_clk26m_clk"; 152318942d29SAllen-KH Cheng interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 152418942d29SAllen-KH Cheng mediatek,apmixedsys = <&apmixedsys>; 152518942d29SAllen-KH Cheng mediatek,infracfg = <&infracfg_ao>; 152618942d29SAllen-KH Cheng mediatek,topckgen = <&topckgen>; 152718942d29SAllen-KH Cheng resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 152818942d29SAllen-KH Cheng reset-names = "audiosys"; 152918942d29SAllen-KH Cheng status = "disabled"; 153018942d29SAllen-KH Cheng }; 153118942d29SAllen-KH Cheng 1532f6c3e61cSAllen-KH Cheng ssusb0: usb@11201000 { 1533f6c3e61cSAllen-KH Cheng compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1534f6c3e61cSAllen-KH Cheng reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1535f6c3e61cSAllen-KH Cheng reg-names = "mac", "ippc"; 1536f6c3e61cSAllen-KH Cheng clocks = <&topckgen CLK_TOP_USB_TOP>, 1537f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1538f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1539*cfdca115SNícolas F. R. A. Prado <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1540*cfdca115SNícolas F. R. A. Prado <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1541*cfdca115SNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1542f6c3e61cSAllen-KH Cheng interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1543f6c3e61cSAllen-KH Cheng phys = <&u2port0 PHY_TYPE_USB2>; 1544f6c3e61cSAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1545f6c3e61cSAllen-KH Cheng #address-cells = <2>; 1546f6c3e61cSAllen-KH Cheng #size-cells = <2>; 1547f6c3e61cSAllen-KH Cheng ranges; 1548f6c3e61cSAllen-KH Cheng status = "disabled"; 1549f6c3e61cSAllen-KH Cheng 1550f6c3e61cSAllen-KH Cheng usb_host0: usb@11200000 { 1551f6c3e61cSAllen-KH Cheng compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1552f6c3e61cSAllen-KH Cheng reg = <0 0x11200000 0 0x1000>; 1553f6c3e61cSAllen-KH Cheng reg-names = "mac"; 1554f6c3e61cSAllen-KH Cheng clocks = <&topckgen CLK_TOP_USB_TOP>, 1555f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1556f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1557f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1558f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1559f6c3e61cSAllen-KH Cheng clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1560f6c3e61cSAllen-KH Cheng interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1561f6c3e61cSAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1562f6c3e61cSAllen-KH Cheng wakeup-source; 1563f6c3e61cSAllen-KH Cheng status = "disabled"; 1564f6c3e61cSAllen-KH Cheng }; 1565f6c3e61cSAllen-KH Cheng }; 1566f6c3e61cSAllen-KH Cheng 15672e78620bSAllen-KH Cheng mmc0: mmc@11230000 { 15682e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mmc", 15692e78620bSAllen-KH Cheng "mediatek,mt8183-mmc"; 1570558741f8SAllen-KH Cheng reg = <0 0x11230000 0 0x10000>, 15712e78620bSAllen-KH Cheng <0 0x11cd0000 0 0x1000>; 15722e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC50_0>, 15732e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1574558741f8SAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1575558741f8SAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1576558741f8SAllen-KH Cheng clock-names = "source", "hclk", "source_cg", "crypto"; 15772e78620bSAllen-KH Cheng interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 15782e78620bSAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 15792e78620bSAllen-KH Cheng assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 15802e78620bSAllen-KH Cheng status = "disabled"; 15812e78620bSAllen-KH Cheng }; 15822e78620bSAllen-KH Cheng 15832e78620bSAllen-KH Cheng mmc1: mmc@11240000 { 15842e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mmc", 15852e78620bSAllen-KH Cheng "mediatek,mt8183-mmc"; 15862e78620bSAllen-KH Cheng reg = <0 0x11240000 0 0x1000>, 15872e78620bSAllen-KH Cheng <0 0x11c90000 0 0x1000>; 15882e78620bSAllen-KH Cheng clocks = <&topckgen CLK_TOP_MSDC30_1>, 15892e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDC1>, 15902e78620bSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 15912e78620bSAllen-KH Cheng clock-names = "source", "hclk", "source_cg"; 15922e78620bSAllen-KH Cheng interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 15932e78620bSAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 15942e78620bSAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 15952e78620bSAllen-KH Cheng status = "disabled"; 15962e78620bSAllen-KH Cheng }; 15972e78620bSAllen-KH Cheng 1598f6c3e61cSAllen-KH Cheng ssusb1: usb@11281000 { 1599f6c3e61cSAllen-KH Cheng compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1600f6c3e61cSAllen-KH Cheng reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1601f6c3e61cSAllen-KH Cheng reg-names = "mac", "ippc"; 1602f6c3e61cSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1603f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1604f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1605*cfdca115SNícolas F. R. A. Prado <&clk26m>, 1606*cfdca115SNícolas F. R. A. Prado <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1607*cfdca115SNícolas F. R. A. Prado clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1608f6c3e61cSAllen-KH Cheng interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1609f6c3e61cSAllen-KH Cheng phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1610f6c3e61cSAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1611f6c3e61cSAllen-KH Cheng #address-cells = <2>; 1612f6c3e61cSAllen-KH Cheng #size-cells = <2>; 1613f6c3e61cSAllen-KH Cheng ranges; 1614f6c3e61cSAllen-KH Cheng status = "disabled"; 1615f6c3e61cSAllen-KH Cheng 1616f6c3e61cSAllen-KH Cheng usb_host1: usb@11280000 { 1617f6c3e61cSAllen-KH Cheng compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1618f6c3e61cSAllen-KH Cheng reg = <0 0x11280000 0 0x1000>; 1619f6c3e61cSAllen-KH Cheng reg-names = "mac"; 1620f6c3e61cSAllen-KH Cheng clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1621f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1622f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1623f6c3e61cSAllen-KH Cheng <&clk26m>, 1624f6c3e61cSAllen-KH Cheng <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1625f6c3e61cSAllen-KH Cheng clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1626f6c3e61cSAllen-KH Cheng interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1627f6c3e61cSAllen-KH Cheng mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1628f6c3e61cSAllen-KH Cheng wakeup-source; 1629f6c3e61cSAllen-KH Cheng status = "disabled"; 1630f6c3e61cSAllen-KH Cheng }; 1631f6c3e61cSAllen-KH Cheng }; 1632f6c3e61cSAllen-KH Cheng 16332e78620bSAllen-KH Cheng u3phy0: t-phy@11c80000 { 16342e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-tphy", 16352e78620bSAllen-KH Cheng "mediatek,generic-tphy-v2"; 16362e78620bSAllen-KH Cheng #address-cells = <1>; 16372e78620bSAllen-KH Cheng #size-cells = <1>; 16382e78620bSAllen-KH Cheng ranges = <0x0 0x0 0x11c80000 0x1000>; 16392e78620bSAllen-KH Cheng status = "disabled"; 16402e78620bSAllen-KH Cheng 16412e78620bSAllen-KH Cheng u2port1: usb-phy@0 { 16422e78620bSAllen-KH Cheng reg = <0x0 0x700>; 16432e78620bSAllen-KH Cheng clocks = <&clk26m>; 16442e78620bSAllen-KH Cheng clock-names = "ref"; 16452e78620bSAllen-KH Cheng #phy-cells = <1>; 16462e78620bSAllen-KH Cheng }; 16472e78620bSAllen-KH Cheng 16482e78620bSAllen-KH Cheng u3port1: usb-phy@700 { 16492e78620bSAllen-KH Cheng reg = <0x700 0x900>; 16502e78620bSAllen-KH Cheng clocks = <&clk26m>; 16512e78620bSAllen-KH Cheng clock-names = "ref"; 16522e78620bSAllen-KH Cheng #phy-cells = <1>; 16532e78620bSAllen-KH Cheng }; 16542e78620bSAllen-KH Cheng }; 16552e78620bSAllen-KH Cheng 16562e78620bSAllen-KH Cheng u3phy1: t-phy@11ca0000 { 16572e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-tphy", 16582e78620bSAllen-KH Cheng "mediatek,generic-tphy-v2"; 16592e78620bSAllen-KH Cheng #address-cells = <1>; 16602e78620bSAllen-KH Cheng #size-cells = <1>; 16612e78620bSAllen-KH Cheng ranges = <0x0 0x0 0x11ca0000 0x1000>; 16622e78620bSAllen-KH Cheng status = "disabled"; 16632e78620bSAllen-KH Cheng 16642e78620bSAllen-KH Cheng u2port0: usb-phy@0 { 16652e78620bSAllen-KH Cheng reg = <0x0 0x700>; 16662e78620bSAllen-KH Cheng clocks = <&clk26m>; 16672e78620bSAllen-KH Cheng clock-names = "ref"; 16682e78620bSAllen-KH Cheng #phy-cells = <1>; 16692e78620bSAllen-KH Cheng mediatek,discth = <0x8>; 16702e78620bSAllen-KH Cheng }; 16712e78620bSAllen-KH Cheng }; 16722e78620bSAllen-KH Cheng 16732e78620bSAllen-KH Cheng efuse: efuse@11cb0000 { 16742e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 16752e78620bSAllen-KH Cheng reg = <0 0x11cb0000 0 0x1000>; 16762e78620bSAllen-KH Cheng #address-cells = <1>; 16772e78620bSAllen-KH Cheng #size-cells = <1>; 1678263d2fd0SChen-Yu Tsai 1679b9cc1708SAngeloGioacchino Del Regno gpu_speedbin: gpu-speedbin@59c { 1680263d2fd0SChen-Yu Tsai reg = <0x59c 0x4>; 1681263d2fd0SChen-Yu Tsai bits = <0 3>; 1682263d2fd0SChen-Yu Tsai }; 16832e78620bSAllen-KH Cheng }; 16842e78620bSAllen-KH Cheng 16852e78620bSAllen-KH Cheng mipi_tx0: dsi-phy@11cc0000 { 16862e78620bSAllen-KH Cheng compatible = "mediatek,mt8183-mipi-tx"; 16872e78620bSAllen-KH Cheng reg = <0 0x11cc0000 0 0x1000>; 16882e78620bSAllen-KH Cheng clocks = <&clk26m>; 16892e78620bSAllen-KH Cheng #clock-cells = <0>; 16902e78620bSAllen-KH Cheng #phy-cells = <0>; 16912e78620bSAllen-KH Cheng clock-output-names = "mipi_tx0_pll"; 16922e78620bSAllen-KH Cheng status = "disabled"; 16932e78620bSAllen-KH Cheng }; 16942e78620bSAllen-KH Cheng 16952e78620bSAllen-KH Cheng mfgsys: clock-controller@13000000 { 16962e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mfgsys"; 16972e78620bSAllen-KH Cheng reg = <0 0x13000000 0 0x1000>; 16982e78620bSAllen-KH Cheng #clock-cells = <1>; 16992e78620bSAllen-KH Cheng }; 17002e78620bSAllen-KH Cheng 1701ee63f414SAngeloGioacchino Del Regno gpu: gpu@13040000 { 1702ee63f414SAngeloGioacchino Del Regno compatible = "mediatek,mt8186-mali", 1703ee63f414SAngeloGioacchino Del Regno "arm,mali-bifrost"; 1704ee63f414SAngeloGioacchino Del Regno reg = <0 0x13040000 0 0x4000>; 1705ee63f414SAngeloGioacchino Del Regno 1706ee63f414SAngeloGioacchino Del Regno clocks = <&mfgsys CLK_MFG_BG3D>; 1707ee63f414SAngeloGioacchino Del Regno interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1708ee63f414SAngeloGioacchino Del Regno <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1709ee63f414SAngeloGioacchino Del Regno <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1710ee63f414SAngeloGioacchino Del Regno interrupt-names = "job", "mmu", "gpu"; 1711ee63f414SAngeloGioacchino Del Regno power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1712ee63f414SAngeloGioacchino Del Regno <&spm MT8186_POWER_DOMAIN_MFG3>; 1713ee63f414SAngeloGioacchino Del Regno power-domain-names = "core0", "core1"; 1714ee63f414SAngeloGioacchino Del Regno #cooling-cells = <2>; 1715263d2fd0SChen-Yu Tsai nvmem-cells = <&gpu_speedbin>; 1716263d2fd0SChen-Yu Tsai nvmem-cell-names = "speed-bin"; 1717f38ea593SChen-Yu Tsai operating-points-v2 = <&gpu_opp_table>; 1718f38ea593SChen-Yu Tsai dynamic-power-coefficient = <4687>; 1719ee63f414SAngeloGioacchino Del Regno status = "disabled"; 1720ee63f414SAngeloGioacchino Del Regno }; 1721ee63f414SAngeloGioacchino Del Regno 17222e78620bSAllen-KH Cheng mmsys: syscon@14000000 { 17232e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mmsys", "syscon"; 17242e78620bSAllen-KH Cheng reg = <0 0x14000000 0 0x1000>; 17252e78620bSAllen-KH Cheng #clock-cells = <1>; 17262e78620bSAllen-KH Cheng #reset-cells = <1>; 17277e07d332SAllen-KH Cheng mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 17287e07d332SAllen-KH Cheng <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 17297e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 17307e07d332SAllen-KH Cheng }; 17317e07d332SAllen-KH Cheng 17327e07d332SAllen-KH Cheng mutex: mutex@14001000 { 17337e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-mutex"; 17347e07d332SAllen-KH Cheng reg = <0 0x14001000 0 0x1000>; 17357e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 17367e07d332SAllen-KH Cheng interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 17377e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 17387e07d332SAllen-KH Cheng mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 17397e07d332SAllen-KH Cheng <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 17407e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 17412e78620bSAllen-KH Cheng }; 17422e78620bSAllen-KH Cheng 1743d4a65162SAllen-KH Cheng smi_common: smi@14002000 { 1744d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-common"; 1745d4a65162SAllen-KH Cheng reg = <0 0x14002000 0 0x1000>; 1746d4a65162SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1747d4a65162SAllen-KH Cheng <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1748d4a65162SAllen-KH Cheng clock-names = "apb", "smi", "gals0", "gals1"; 1749d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1750d4a65162SAllen-KH Cheng }; 1751d4a65162SAllen-KH Cheng 1752d4a65162SAllen-KH Cheng larb0: smi@14003000 { 1753d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1754d4a65162SAllen-KH Cheng reg = <0 0x14003000 0 0x1000>; 1755d4a65162SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 1756d4a65162SAllen-KH Cheng <&mmsys CLK_MM_SMI_COMMON>; 1757d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1758d4a65162SAllen-KH Cheng mediatek,larb-id = <0>; 1759d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1760d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1761d4a65162SAllen-KH Cheng }; 1762d4a65162SAllen-KH Cheng 1763d4a65162SAllen-KH Cheng larb1: smi@14004000 { 1764d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1765d4a65162SAllen-KH Cheng reg = <0 0x14004000 0 0x1000>; 1766d4a65162SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_COMMON>, 1767d4a65162SAllen-KH Cheng <&mmsys CLK_MM_SMI_COMMON>; 1768d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1769d4a65162SAllen-KH Cheng mediatek,larb-id = <1>; 1770d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1771d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1772d4a65162SAllen-KH Cheng }; 1773d4a65162SAllen-KH Cheng 17747e07d332SAllen-KH Cheng ovl0: ovl@14005000 { 17757e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 17767e07d332SAllen-KH Cheng reg = <0 0x14005000 0 0x1000>; 17777e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0>; 17787e07d332SAllen-KH Cheng interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 17797e07d332SAllen-KH Cheng iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 17807e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 17817e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 17827e07d332SAllen-KH Cheng }; 17837e07d332SAllen-KH Cheng 17847e07d332SAllen-KH Cheng ovl_2l0: ovl@14006000 { 17857e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 17867e07d332SAllen-KH Cheng reg = <0 0x14006000 0 0x1000>; 17877e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 17887e07d332SAllen-KH Cheng interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 17897e07d332SAllen-KH Cheng iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 17907e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 17917e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 17927e07d332SAllen-KH Cheng }; 17937e07d332SAllen-KH Cheng 17947e07d332SAllen-KH Cheng rdma0: rdma@14007000 { 17957e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 17967e07d332SAllen-KH Cheng reg = <0 0x14007000 0 0x1000>; 17977e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA0>; 17987e07d332SAllen-KH Cheng interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 17997e07d332SAllen-KH Cheng iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 18007e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 18017e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 18027e07d332SAllen-KH Cheng }; 18037e07d332SAllen-KH Cheng 18047e07d332SAllen-KH Cheng color: color@14009000 { 18057e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 18067e07d332SAllen-KH Cheng reg = <0 0x14009000 0 0x1000>; 18077e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_COLOR0>; 18087e07d332SAllen-KH Cheng interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 18097e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 18107e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 18117e07d332SAllen-KH Cheng }; 18127e07d332SAllen-KH Cheng 181390e75e82SAllen-KH Cheng dpi: dpi@1400a000 { 181490e75e82SAllen-KH Cheng compatible = "mediatek,mt8186-dpi"; 181590e75e82SAllen-KH Cheng reg = <0 0x1400a000 0 0x1000>; 181690e75e82SAllen-KH Cheng clocks = <&topckgen CLK_TOP_DPI>, 181790e75e82SAllen-KH Cheng <&mmsys CLK_MM_DISP_DPI>, 181890e75e82SAllen-KH Cheng <&apmixedsys CLK_APMIXED_TVDPLL>; 181990e75e82SAllen-KH Cheng clock-names = "pixel", "engine", "pll"; 182090e75e82SAllen-KH Cheng assigned-clocks = <&topckgen CLK_TOP_DPI>; 182190e75e82SAllen-KH Cheng assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 182290e75e82SAllen-KH Cheng interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 182390e75e82SAllen-KH Cheng status = "disabled"; 182490e75e82SAllen-KH Cheng 182590e75e82SAllen-KH Cheng port { 182690e75e82SAllen-KH Cheng dpi_out: endpoint { }; 182790e75e82SAllen-KH Cheng }; 182890e75e82SAllen-KH Cheng }; 182990e75e82SAllen-KH Cheng 18307e07d332SAllen-KH Cheng ccorr: ccorr@1400b000 { 18317e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 18327e07d332SAllen-KH Cheng reg = <0 0x1400b000 0 0x1000>; 18337e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_CCORR0>; 18347e07d332SAllen-KH Cheng interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 18357e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 18367e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 18377e07d332SAllen-KH Cheng }; 18387e07d332SAllen-KH Cheng 18397e07d332SAllen-KH Cheng aal: aal@1400c000 { 18407e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 18417e07d332SAllen-KH Cheng reg = <0 0x1400c000 0 0x1000>; 18427e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_AAL0>; 18437e07d332SAllen-KH Cheng interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 18447e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 18457e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 18467e07d332SAllen-KH Cheng }; 18477e07d332SAllen-KH Cheng 18487e07d332SAllen-KH Cheng gamma: gamma@1400d000 { 18497e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 18507e07d332SAllen-KH Cheng reg = <0 0x1400d000 0 0x1000>; 18517e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 18527e07d332SAllen-KH Cheng interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 18537e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 18547e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 18557e07d332SAllen-KH Cheng }; 18567e07d332SAllen-KH Cheng 18577e07d332SAllen-KH Cheng postmask: postmask@1400e000 { 18587e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-postmask", 18597e07d332SAllen-KH Cheng "mediatek,mt8192-disp-postmask"; 18607e07d332SAllen-KH Cheng reg = <0 0x1400e000 0 0x1000>; 18617e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 18627e07d332SAllen-KH Cheng interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 18637e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 18647e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 18657e07d332SAllen-KH Cheng }; 18667e07d332SAllen-KH Cheng 18677e07d332SAllen-KH Cheng dither: dither@1400f000 { 18687e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 18697e07d332SAllen-KH Cheng reg = <0 0x1400f000 0 0x1000>; 18707e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_DITHER0>; 18717e07d332SAllen-KH Cheng interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 18727e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 18737e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 18747e07d332SAllen-KH Cheng }; 18757e07d332SAllen-KH Cheng 1876bd2b1b4aSAllen-KH Cheng dsi0: dsi@14013000 { 1877bd2b1b4aSAllen-KH Cheng compatible = "mediatek,mt8186-dsi"; 1878bd2b1b4aSAllen-KH Cheng reg = <0 0x14013000 0 0x1000>; 1879bd2b1b4aSAllen-KH Cheng clocks = <&mmsys CLK_MM_DSI0>, 1880bd2b1b4aSAllen-KH Cheng <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1881bd2b1b4aSAllen-KH Cheng <&mipi_tx0>; 1882bd2b1b4aSAllen-KH Cheng clock-names = "engine", "digital", "hs"; 1883bd2b1b4aSAllen-KH Cheng interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1884bd2b1b4aSAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1885bd2b1b4aSAllen-KH Cheng resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1886bd2b1b4aSAllen-KH Cheng phys = <&mipi_tx0>; 1887bd2b1b4aSAllen-KH Cheng phy-names = "dphy"; 1888bd2b1b4aSAllen-KH Cheng status = "disabled"; 1889bd2b1b4aSAllen-KH Cheng 1890bd2b1b4aSAllen-KH Cheng port { 1891bd2b1b4aSAllen-KH Cheng dsi_out: endpoint { }; 1892bd2b1b4aSAllen-KH Cheng }; 1893bd2b1b4aSAllen-KH Cheng }; 1894bd2b1b4aSAllen-KH Cheng 1895d4a65162SAllen-KH Cheng iommu_mm: iommu@14016000 { 1896d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-iommu-mm"; 1897d4a65162SAllen-KH Cheng reg = <0 0x14016000 0 0x1000>; 1898d4a65162SAllen-KH Cheng clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1899d4a65162SAllen-KH Cheng clock-names = "bclk"; 1900d4a65162SAllen-KH Cheng interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1901d4a65162SAllen-KH Cheng mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1902d4a65162SAllen-KH Cheng &larb7 &larb8 &larb9 &larb11 1903d4a65162SAllen-KH Cheng &larb13 &larb14 &larb16 &larb17 1904d4a65162SAllen-KH Cheng &larb19 &larb20>; 1905d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1906d4a65162SAllen-KH Cheng #iommu-cells = <1>; 1907d4a65162SAllen-KH Cheng }; 1908d4a65162SAllen-KH Cheng 19097e07d332SAllen-KH Cheng rdma1: rdma@1401f000 { 19107e07d332SAllen-KH Cheng compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 19117e07d332SAllen-KH Cheng reg = <0 0x1401f000 0 0x1000>; 19127e07d332SAllen-KH Cheng clocks = <&mmsys CLK_MM_DISP_RDMA1>; 19137e07d332SAllen-KH Cheng interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 19147e07d332SAllen-KH Cheng iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 19157e07d332SAllen-KH Cheng mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 19167e07d332SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 19177e07d332SAllen-KH Cheng }; 19187e07d332SAllen-KH Cheng 19192e78620bSAllen-KH Cheng wpesys: clock-controller@14020000 { 19202e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-wpesys"; 19212e78620bSAllen-KH Cheng reg = <0 0x14020000 0 0x1000>; 19222e78620bSAllen-KH Cheng #clock-cells = <1>; 19232e78620bSAllen-KH Cheng }; 19242e78620bSAllen-KH Cheng 1925d4a65162SAllen-KH Cheng larb8: smi@14023000 { 1926d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1927d4a65162SAllen-KH Cheng reg = <0 0x14023000 0 0x1000>; 1928d4a65162SAllen-KH Cheng clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1929d4a65162SAllen-KH Cheng <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1930d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1931d4a65162SAllen-KH Cheng mediatek,larb-id = <8>; 1932d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1933d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1934d4a65162SAllen-KH Cheng }; 1935d4a65162SAllen-KH Cheng 19362e78620bSAllen-KH Cheng imgsys1: clock-controller@15020000 { 19372e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-imgsys1"; 19382e78620bSAllen-KH Cheng reg = <0 0x15020000 0 0x1000>; 19392e78620bSAllen-KH Cheng #clock-cells = <1>; 19402e78620bSAllen-KH Cheng }; 19412e78620bSAllen-KH Cheng 1942d4a65162SAllen-KH Cheng larb9: smi@1502e000 { 1943d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1944d4a65162SAllen-KH Cheng reg = <0 0x1502e000 0 0x1000>; 1945d4a65162SAllen-KH Cheng clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1946d4a65162SAllen-KH Cheng <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1947d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1948d4a65162SAllen-KH Cheng mediatek,larb-id = <9>; 1949d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1950d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1951d4a65162SAllen-KH Cheng }; 1952d4a65162SAllen-KH Cheng 19532e78620bSAllen-KH Cheng imgsys2: clock-controller@15820000 { 19542e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-imgsys2"; 19552e78620bSAllen-KH Cheng reg = <0 0x15820000 0 0x1000>; 19562e78620bSAllen-KH Cheng #clock-cells = <1>; 19572e78620bSAllen-KH Cheng }; 19582e78620bSAllen-KH Cheng 1959d4a65162SAllen-KH Cheng larb11: smi@1582e000 { 1960d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1961d4a65162SAllen-KH Cheng reg = <0 0x1582e000 0 0x1000>; 1962d4a65162SAllen-KH Cheng clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1963d4a65162SAllen-KH Cheng <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1964d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1965d4a65162SAllen-KH Cheng mediatek,larb-id = <11>; 1966d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1967d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1968d4a65162SAllen-KH Cheng }; 1969d4a65162SAllen-KH Cheng 1970d4a65162SAllen-KH Cheng larb4: smi@1602e000 { 1971d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1972d4a65162SAllen-KH Cheng reg = <0 0x1602e000 0 0x1000>; 1973d4a65162SAllen-KH Cheng clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1974d4a65162SAllen-KH Cheng <&vdecsys CLK_VDEC_LARB1_CKEN>; 1975d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1976d4a65162SAllen-KH Cheng mediatek,larb-id = <4>; 1977d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 1978d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1979d4a65162SAllen-KH Cheng }; 1980d4a65162SAllen-KH Cheng 19812e78620bSAllen-KH Cheng vdecsys: clock-controller@1602f000 { 19822e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-vdecsys"; 19832e78620bSAllen-KH Cheng reg = <0 0x1602f000 0 0x1000>; 19842e78620bSAllen-KH Cheng #clock-cells = <1>; 19852e78620bSAllen-KH Cheng }; 19862e78620bSAllen-KH Cheng 19872e78620bSAllen-KH Cheng vencsys: clock-controller@17000000 { 19882e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-vencsys"; 19892e78620bSAllen-KH Cheng reg = <0 0x17000000 0 0x1000>; 19902e78620bSAllen-KH Cheng #clock-cells = <1>; 19912e78620bSAllen-KH Cheng }; 19922e78620bSAllen-KH Cheng 1993d4a65162SAllen-KH Cheng larb7: smi@17010000 { 1994d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 1995d4a65162SAllen-KH Cheng reg = <0 0x17010000 0 0x1000>; 1996d4a65162SAllen-KH Cheng clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1997d4a65162SAllen-KH Cheng <&vencsys CLK_VENC_CKE1_VENC>; 1998d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 1999d4a65162SAllen-KH Cheng mediatek,larb-id = <7>; 2000d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 2001d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 2002d4a65162SAllen-KH Cheng }; 2003d4a65162SAllen-KH Cheng 20042e78620bSAllen-KH Cheng camsys: clock-controller@1a000000 { 20052e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-camsys"; 20062e78620bSAllen-KH Cheng reg = <0 0x1a000000 0 0x1000>; 20072e78620bSAllen-KH Cheng #clock-cells = <1>; 20082e78620bSAllen-KH Cheng }; 20092e78620bSAllen-KH Cheng 2010d4a65162SAllen-KH Cheng larb13: smi@1a001000 { 2011d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 2012d4a65162SAllen-KH Cheng reg = <0 0x1a001000 0 0x1000>; 2013d4a65162SAllen-KH Cheng clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 2014d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 2015d4a65162SAllen-KH Cheng mediatek,larb-id = <13>; 2016d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 2017d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 2018d4a65162SAllen-KH Cheng }; 2019d4a65162SAllen-KH Cheng 2020d4a65162SAllen-KH Cheng larb14: smi@1a002000 { 2021d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 2022d4a65162SAllen-KH Cheng reg = <0 0x1a002000 0 0x1000>; 2023d4a65162SAllen-KH Cheng clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 2024d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 2025d4a65162SAllen-KH Cheng mediatek,larb-id = <14>; 2026d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 2027d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 2028d4a65162SAllen-KH Cheng }; 2029d4a65162SAllen-KH Cheng 2030d4a65162SAllen-KH Cheng larb16: smi@1a00f000 { 2031d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 2032d4a65162SAllen-KH Cheng reg = <0 0x1a00f000 0 0x1000>; 2033d4a65162SAllen-KH Cheng clocks = <&camsys CLK_CAM_LARB14>, 2034d4a65162SAllen-KH Cheng <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 2035d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 2036d4a65162SAllen-KH Cheng mediatek,larb-id = <16>; 2037d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 2038d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 2039d4a65162SAllen-KH Cheng }; 2040d4a65162SAllen-KH Cheng 2041d4a65162SAllen-KH Cheng larb17: smi@1a010000 { 2042d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 2043d4a65162SAllen-KH Cheng reg = <0 0x1a010000 0 0x1000>; 2044d4a65162SAllen-KH Cheng clocks = <&camsys CLK_CAM_LARB13>, 2045d4a65162SAllen-KH Cheng <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 2046d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 2047d4a65162SAllen-KH Cheng mediatek,larb-id = <17>; 2048d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 2049d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 2050d4a65162SAllen-KH Cheng }; 2051d4a65162SAllen-KH Cheng 20522e78620bSAllen-KH Cheng camsys_rawa: clock-controller@1a04f000 { 20532e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-camsys_rawa"; 20542e78620bSAllen-KH Cheng reg = <0 0x1a04f000 0 0x1000>; 20552e78620bSAllen-KH Cheng #clock-cells = <1>; 20562e78620bSAllen-KH Cheng }; 20572e78620bSAllen-KH Cheng 20582e78620bSAllen-KH Cheng camsys_rawb: clock-controller@1a06f000 { 20592e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-camsys_rawb"; 20602e78620bSAllen-KH Cheng reg = <0 0x1a06f000 0 0x1000>; 20612e78620bSAllen-KH Cheng #clock-cells = <1>; 20622e78620bSAllen-KH Cheng }; 20632e78620bSAllen-KH Cheng 20642e78620bSAllen-KH Cheng mdpsys: clock-controller@1b000000 { 20652e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-mdpsys"; 20662e78620bSAllen-KH Cheng reg = <0 0x1b000000 0 0x1000>; 20672e78620bSAllen-KH Cheng #clock-cells = <1>; 20682e78620bSAllen-KH Cheng }; 20692e78620bSAllen-KH Cheng 2070d4a65162SAllen-KH Cheng larb2: smi@1b002000 { 2071d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 2072d4a65162SAllen-KH Cheng reg = <0 0x1b002000 0 0x1000>; 2073d4a65162SAllen-KH Cheng clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 2074d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 2075d4a65162SAllen-KH Cheng mediatek,larb-id = <2>; 2076d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 2077d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 2078d4a65162SAllen-KH Cheng }; 2079d4a65162SAllen-KH Cheng 20802e78620bSAllen-KH Cheng ipesys: clock-controller@1c000000 { 20812e78620bSAllen-KH Cheng compatible = "mediatek,mt8186-ipesys"; 20822e78620bSAllen-KH Cheng reg = <0 0x1c000000 0 0x1000>; 20832e78620bSAllen-KH Cheng #clock-cells = <1>; 20842e78620bSAllen-KH Cheng }; 2085d4a65162SAllen-KH Cheng 2086d4a65162SAllen-KH Cheng larb20: smi@1c00f000 { 2087d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 2088d4a65162SAllen-KH Cheng reg = <0 0x1c00f000 0 0x1000>; 2089d4a65162SAllen-KH Cheng clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 2090d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 2091d4a65162SAllen-KH Cheng mediatek,larb-id = <20>; 2092d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 2093d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 2094d4a65162SAllen-KH Cheng }; 2095d4a65162SAllen-KH Cheng 2096d4a65162SAllen-KH Cheng larb19: smi@1c10f000 { 2097d4a65162SAllen-KH Cheng compatible = "mediatek,mt8186-smi-larb"; 2098d4a65162SAllen-KH Cheng reg = <0 0x1c10f000 0 0x1000>; 2099d4a65162SAllen-KH Cheng clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 2100d4a65162SAllen-KH Cheng clock-names = "apb", "smi"; 2101d4a65162SAllen-KH Cheng mediatek,larb-id = <19>; 2102d4a65162SAllen-KH Cheng mediatek,smi = <&smi_common>; 2103d4a65162SAllen-KH Cheng power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 2104d4a65162SAllen-KH Cheng }; 21052e78620bSAllen-KH Cheng }; 21062e78620bSAllen-KH Cheng}; 2107