1e1e4f7feSCK Hu // SPDX-License-Identifier: GPL-2.0-only
2e1e4f7feSCK Hu /*
3e1e4f7feSCK Hu * Copyright (c) 2015 MediaTek Inc.
4e1e4f7feSCK Hu */
5e1e4f7feSCK Hu
6e1e4f7feSCK Hu #include <linux/clk.h>
7e1e4f7feSCK Hu #include <linux/iopoll.h>
8e1e4f7feSCK Hu #include <linux/module.h>
9*d01e0aecSRob Herring #include <linux/of.h>
10e1e4f7feSCK Hu #include <linux/platform_device.h>
11e1e4f7feSCK Hu #include <linux/regmap.h>
12e1e4f7feSCK Hu #include <linux/soc/mediatek/mtk-mmsys.h>
13e1e4f7feSCK Hu #include <linux/soc/mediatek/mtk-mutex.h>
14e5758850SMoudy Ho #include <linux/soc/mediatek/mtk-cmdq.h>
15e1e4f7feSCK Hu
16dc36768dSAngeloGioacchino Del Regno #define MTK_MUTEX_MAX_HANDLES 10
17dc36768dSAngeloGioacchino Del Regno
18e1e4f7feSCK Hu #define MT2701_MUTEX0_MOD0 0x2c
19e1e4f7feSCK Hu #define MT2701_MUTEX0_SOF0 0x30
2004121201SYongqiang Niu #define MT8183_MUTEX0_MOD0 0x30
2104121201SYongqiang Niu #define MT8183_MUTEX0_SOF0 0x2c
22e1e4f7feSCK Hu
23e1e4f7feSCK Hu #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
24e1e4f7feSCK Hu #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
25e1e4f7feSCK Hu #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
26e1e4f7feSCK Hu #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n))
27c54d2b99SRoy-CW.Yeh #define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4)
28e1e4f7feSCK Hu #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
29e1e4f7feSCK Hu #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
30e1e4f7feSCK Hu
31e1e4f7feSCK Hu #define INT_MUTEX BIT(1)
32e1e4f7feSCK Hu
3315f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_OVL0 0
3415f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
3515f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_RDMA0 2
3615f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_COLOR0 4
3715f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_CCORR0 5
3815f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_AAL0 7
3915f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_GAMMA0 8
4015f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
4115f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_DITHER0 10
4215f17683SYongqiang Niu #define MT8186_MUTEX_MOD_DISP_RDMA1 17
4315f17683SYongqiang Niu
4415f17683SYongqiang Niu #define MT8186_MUTEX_SOF_SINGLE_MODE 0
4515f17683SYongqiang Niu #define MT8186_MUTEX_SOF_DSI0 1
4615f17683SYongqiang Niu #define MT8186_MUTEX_SOF_DPI0 2
4715f17683SYongqiang Niu #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
4815f17683SYongqiang Niu #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
4915f17683SYongqiang Niu
50e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_PWM 1
51e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_OVL0 6
52e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_OVL1 7
53e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_RDMA0 8
54e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_RDMA1 9
55e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_WDMA0 10
56e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_CCORR 11
57e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_COLOR 12
58e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_AAL 13
59e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_GAMMA 14
60e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_DITHER 15
61e1e4f7feSCK Hu #define MT8167_MUTEX_MOD_DISP_UFOE 16
62e1e4f7feSCK Hu
6313d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_OVL0 0
6413d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
6513d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_RDMA0 2
6613d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_COLOR0 4
6713d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_CCORR0 5
6813d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_AAL0 6
6913d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_GAMMA0 7
7013d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
7113d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_DITHER0 9
7213d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
7313d9624dSYongqiang Niu #define MT8192_MUTEX_MOD_DISP_RDMA4 17
7413d9624dSYongqiang Niu
7504121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_RDMA0 0
7604121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_RDMA1 1
7704121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_OVL0 9
7804121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
7904121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
8004121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_WDMA0 12
8104121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_COLOR0 13
8204121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_CCORR0 14
8304121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_AAL0 15
8404121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_GAMMA0 16
8504121201SYongqiang Niu #define MT8183_MUTEX_MOD_DISP_DITHER0 17
8604121201SYongqiang Niu
872c9f8d1eSMoudy Ho #define MT8183_MUTEX_MOD_MDP_RDMA0 2
882c9f8d1eSMoudy Ho #define MT8183_MUTEX_MOD_MDP_RSZ0 4
892c9f8d1eSMoudy Ho #define MT8183_MUTEX_MOD_MDP_RSZ1 5
902c9f8d1eSMoudy Ho #define MT8183_MUTEX_MOD_MDP_TDSHP0 6
912c9f8d1eSMoudy Ho #define MT8183_MUTEX_MOD_MDP_WROT0 7
922c9f8d1eSMoudy Ho #define MT8183_MUTEX_MOD_MDP_WDMA 8
932c9f8d1eSMoudy Ho #define MT8183_MUTEX_MOD_MDP_AAL0 23
942c9f8d1eSMoudy Ho #define MT8183_MUTEX_MOD_MDP_CCORR0 24
952c9f8d1eSMoudy Ho
9621370ecdSAllen-KH Cheng #define MT8186_MUTEX_MOD_MDP_RDMA0 0
9721370ecdSAllen-KH Cheng #define MT8186_MUTEX_MOD_MDP_AAL0 2
9821370ecdSAllen-KH Cheng #define MT8186_MUTEX_MOD_MDP_HDR0 4
9921370ecdSAllen-KH Cheng #define MT8186_MUTEX_MOD_MDP_RSZ0 5
10021370ecdSAllen-KH Cheng #define MT8186_MUTEX_MOD_MDP_RSZ1 6
10121370ecdSAllen-KH Cheng #define MT8186_MUTEX_MOD_MDP_WROT0 7
10221370ecdSAllen-KH Cheng #define MT8186_MUTEX_MOD_MDP_TDSHP0 9
10321370ecdSAllen-KH Cheng #define MT8186_MUTEX_MOD_MDP_COLOR0 14
10421370ecdSAllen-KH Cheng
105e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_OVL0 11
106e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_OVL1 12
107e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_RDMA0 13
108e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_RDMA1 14
109e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_RDMA2 15
110e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_WDMA0 16
111e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_WDMA1 17
112e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_COLOR0 18
113e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_COLOR1 19
114e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_AAL 20
115e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_GAMMA 21
116e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_UFOE 22
117e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_PWM0 23
118e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_PWM1 24
119e1e4f7feSCK Hu #define MT8173_MUTEX_MOD_DISP_OD 25
120e1e4f7feSCK Hu
12164bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_OVL0 0
12264bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_WDMA0 1
12364bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_RDMA0 2
12464bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_COLOR0 3
12564bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_CCORR0 4
12664bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_AAL0 5
12764bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_GAMMA0 6
12864bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_DITHER0 7
12964bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_DSI0 8
13064bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
13164bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20
13264bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_DP_INTF0 21
13364bc37bfSNathan Lu #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24
13464bc37bfSNathan Lu #define MT8188_MUTEX_MOD2_DISP_PWM0 33
13564bc37bfSNathan Lu
1368fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_OVL0 0
1378fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_WDMA0 1
1388fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_RDMA0 2
1398fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_COLOR0 3
1408fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_CCORR0 4
1418fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_AAL0 5
1428fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_GAMMA0 6
1438fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_DITHER0 7
1448fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_DSI0 8
1458fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
1468fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
1478fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
1488fdb61f1Sjason-jh.lin #define MT8195_MUTEX_MOD_DISP_PWM0 27
1498fdb61f1Sjason-jh.lin
1504ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0
1514ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1
1524ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2
1534ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3
1544ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4
1554ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5
1564ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6
1574ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7
1584ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8
1594ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9
1604ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10
1614ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11
1624ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12
1634ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18
1644ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_DPI0 25
1654ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_DPI1 26
1664ea6aa89SNancy.Lin #define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27
1674ea6aa89SNancy.Lin
168549053b6SRoy-CW.Yeh /* VPPSYS0 */
169549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_RDMA0 0
170549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_FG0 1
171549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_STITCH0 2
172549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_HDR0 3
173549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_AAL0 4
174549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_RSZ0 5
175549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_TDSHP0 6
176549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_COLOR0 7
177549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_OVL0 8
178549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_PAD0 9
179549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_TCC0 10
180549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_WROT0 11
181549053b6SRoy-CW.Yeh
182549053b6SRoy-CW.Yeh /* VPPSYS1 */
183549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_TCC1 3
184549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_RDMA1 4
185549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_RDMA2 5
186549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_RDMA3 6
187549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_FG1 7
188549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_FG2 8
189549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_FG3 9
190549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_HDR1 10
191549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_HDR2 11
192549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_HDR3 12
193549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_AAL1 13
194549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_AAL2 14
195549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_AAL3 15
196549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_RSZ1 16
197549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_RSZ2 17
198549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_RSZ3 18
199549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_TDSHP1 19
200549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_TDSHP2 20
201549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_TDSHP3 21
202549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_MERGE2 22
203549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_MERGE3 23
204549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_COLOR1 24
205549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_COLOR2 25
206549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_COLOR3 26
207549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_OVL1 27
208549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_PAD1 28
209549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_PAD2 29
210549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_PAD3 30
211549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_WROT1 31
212549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_WROT2 32
213549053b6SRoy-CW.Yeh #define MT8195_MUTEX_MOD_MDP_WROT3 33
214549053b6SRoy-CW.Yeh
215141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_OVL0 7
216141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
217141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_RDMA0 9
218141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_RDMA1 10
219141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_WDMA0 11
220141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_COLOR0 12
221141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_CCORR 13
222141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_AAL 14
223141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_GAMMA 15
224141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_DITHER 16
225141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_DSI0 17
226141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_PWM0 20
227141311b8SFabien Parent #define MT8365_MUTEX_MOD_DISP_DPI0 22
228141311b8SFabien Parent
229e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_PWM2 10
230e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_OVL0 11
231e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_OVL1 12
232e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_RDMA0 13
233e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_RDMA1 14
234e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_RDMA2 15
235e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_WDMA0 16
236e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_WDMA1 17
237e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_COLOR0 18
238e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_COLOR1 19
239e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_AAL0 20
240e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_UFOE 22
241e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_PWM0 23
242e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_PWM1 24
243e1e4f7feSCK Hu #define MT2712_MUTEX_MOD_DISP_OD0 25
244e1e4f7feSCK Hu #define MT2712_MUTEX_MOD2_DISP_AAL1 33
245e1e4f7feSCK Hu #define MT2712_MUTEX_MOD2_DISP_OD1 34
246e1e4f7feSCK Hu
247e1e4f7feSCK Hu #define MT2701_MUTEX_MOD_DISP_OVL 3
248e1e4f7feSCK Hu #define MT2701_MUTEX_MOD_DISP_WDMA 6
249e1e4f7feSCK Hu #define MT2701_MUTEX_MOD_DISP_COLOR 7
250e1e4f7feSCK Hu #define MT2701_MUTEX_MOD_DISP_BLS 9
251e1e4f7feSCK Hu #define MT2701_MUTEX_MOD_DISP_RDMA0 10
252e1e4f7feSCK Hu #define MT2701_MUTEX_MOD_DISP_RDMA1 12
253e1e4f7feSCK Hu
254e1e4f7feSCK Hu #define MT2712_MUTEX_SOF_SINGLE_MODE 0
255e1e4f7feSCK Hu #define MT2712_MUTEX_SOF_DSI0 1
256e1e4f7feSCK Hu #define MT2712_MUTEX_SOF_DSI1 2
257e1e4f7feSCK Hu #define MT2712_MUTEX_SOF_DPI0 3
258e1e4f7feSCK Hu #define MT2712_MUTEX_SOF_DPI1 4
259e1e4f7feSCK Hu #define MT2712_MUTEX_SOF_DSI2 5
260e1e4f7feSCK Hu #define MT2712_MUTEX_SOF_DSI3 6
261e1e4f7feSCK Hu #define MT8167_MUTEX_SOF_DPI0 2
262e1e4f7feSCK Hu #define MT8167_MUTEX_SOF_DPI1 3
26304121201SYongqiang Niu #define MT8183_MUTEX_SOF_DSI0 1
26404121201SYongqiang Niu #define MT8183_MUTEX_SOF_DPI0 2
26564bc37bfSNathan Lu #define MT8188_MUTEX_SOF_DSI0 1
26664bc37bfSNathan Lu #define MT8188_MUTEX_SOF_DP_INTF0 3
2678fdb61f1Sjason-jh.lin #define MT8195_MUTEX_SOF_DSI0 1
2688fdb61f1Sjason-jh.lin #define MT8195_MUTEX_SOF_DSI1 2
2698fdb61f1Sjason-jh.lin #define MT8195_MUTEX_SOF_DP_INTF0 3
2708fdb61f1Sjason-jh.lin #define MT8195_MUTEX_SOF_DP_INTF1 4
2718fdb61f1Sjason-jh.lin #define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
2728fdb61f1Sjason-jh.lin #define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
27304121201SYongqiang Niu
27404121201SYongqiang Niu #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
27504121201SYongqiang Niu #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
27664bc37bfSNathan Lu #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7)
27764bc37bfSNathan Lu #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7)
2788fdb61f1Sjason-jh.lin #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
2798fdb61f1Sjason-jh.lin #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
2808fdb61f1Sjason-jh.lin #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
2818fdb61f1Sjason-jh.lin #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
2828fdb61f1Sjason-jh.lin #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
2838fdb61f1Sjason-jh.lin #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
284e1e4f7feSCK Hu
285e1e4f7feSCK Hu struct mtk_mutex {
286dc36768dSAngeloGioacchino Del Regno u8 id;
287e1e4f7feSCK Hu bool claimed;
288e1e4f7feSCK Hu };
289e1e4f7feSCK Hu
290e1e4f7feSCK Hu enum mtk_mutex_sof_id {
291e1e4f7feSCK Hu MUTEX_SOF_SINGLE_MODE,
292e1e4f7feSCK Hu MUTEX_SOF_DSI0,
293e1e4f7feSCK Hu MUTEX_SOF_DSI1,
294e1e4f7feSCK Hu MUTEX_SOF_DPI0,
295e1e4f7feSCK Hu MUTEX_SOF_DPI1,
296e1e4f7feSCK Hu MUTEX_SOF_DSI2,
297e1e4f7feSCK Hu MUTEX_SOF_DSI3,
2988fdb61f1Sjason-jh.lin MUTEX_SOF_DP_INTF0,
2998fdb61f1Sjason-jh.lin MUTEX_SOF_DP_INTF1,
3008fdb61f1Sjason-jh.lin DDP_MUTEX_SOF_MAX,
301e1e4f7feSCK Hu };
302e1e4f7feSCK Hu
303e1e4f7feSCK Hu struct mtk_mutex_data {
304e1e4f7feSCK Hu const unsigned int *mutex_mod;
305e1e4f7feSCK Hu const unsigned int *mutex_sof;
306e1e4f7feSCK Hu const unsigned int mutex_mod_reg;
307e1e4f7feSCK Hu const unsigned int mutex_sof_reg;
308d0804085SMoudy Ho const unsigned int *mutex_table_mod;
309e1e4f7feSCK Hu const bool no_clk;
310e1e4f7feSCK Hu };
311e1e4f7feSCK Hu
312e1e4f7feSCK Hu struct mtk_mutex_ctx {
313e1e4f7feSCK Hu struct device *dev;
314e1e4f7feSCK Hu struct clk *clk;
315e1e4f7feSCK Hu void __iomem *regs;
316dc36768dSAngeloGioacchino Del Regno struct mtk_mutex mutex[MTK_MUTEX_MAX_HANDLES];
317e1e4f7feSCK Hu const struct mtk_mutex_data *data;
318e5758850SMoudy Ho phys_addr_t addr;
319e5758850SMoudy Ho struct cmdq_client_reg cmdq_reg;
320e1e4f7feSCK Hu };
321e1e4f7feSCK Hu
322e1e4f7feSCK Hu static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
323e1e4f7feSCK Hu [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
324e1e4f7feSCK Hu [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
325e1e4f7feSCK Hu [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
326e1e4f7feSCK Hu [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
327e1e4f7feSCK Hu [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
328e1e4f7feSCK Hu [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
329e1e4f7feSCK Hu };
330e1e4f7feSCK Hu
331e1e4f7feSCK Hu static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
332e1e4f7feSCK Hu [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
333e1e4f7feSCK Hu [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
334e1e4f7feSCK Hu [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
335e1e4f7feSCK Hu [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
336e1e4f7feSCK Hu [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
337e1e4f7feSCK Hu [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
338e1e4f7feSCK Hu [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
339e1e4f7feSCK Hu [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
340e1e4f7feSCK Hu [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
341e1e4f7feSCK Hu [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
342e1e4f7feSCK Hu [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
343e1e4f7feSCK Hu [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
344e1e4f7feSCK Hu [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
345e1e4f7feSCK Hu [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
346e1e4f7feSCK Hu [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
347e1e4f7feSCK Hu [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
348e1e4f7feSCK Hu [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
349e1e4f7feSCK Hu };
350e1e4f7feSCK Hu
351e1e4f7feSCK Hu static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
352e1e4f7feSCK Hu [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
353e1e4f7feSCK Hu [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
354e1e4f7feSCK Hu [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
3554e8988c6Sjason-jh.lin [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
356e1e4f7feSCK Hu [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
357e1e4f7feSCK Hu [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
358e1e4f7feSCK Hu [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
359e1e4f7feSCK Hu [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
360e1e4f7feSCK Hu [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
361e1e4f7feSCK Hu [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
362e1e4f7feSCK Hu [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
363e1e4f7feSCK Hu [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
364e1e4f7feSCK Hu };
365e1e4f7feSCK Hu
366e1e4f7feSCK Hu static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
367e1e4f7feSCK Hu [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
368e1e4f7feSCK Hu [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
369e1e4f7feSCK Hu [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
370e1e4f7feSCK Hu [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
371e1e4f7feSCK Hu [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
372e1e4f7feSCK Hu [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
373e1e4f7feSCK Hu [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
374e1e4f7feSCK Hu [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
375e1e4f7feSCK Hu [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
376e1e4f7feSCK Hu [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
377e1e4f7feSCK Hu [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
378e1e4f7feSCK Hu [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
379e1e4f7feSCK Hu [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
380e1e4f7feSCK Hu [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
381e1e4f7feSCK Hu [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
382e1e4f7feSCK Hu };
383e1e4f7feSCK Hu
38404121201SYongqiang Niu static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
38504121201SYongqiang Niu [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
38604121201SYongqiang Niu [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
38704121201SYongqiang Niu [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
3884e8988c6Sjason-jh.lin [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
38904121201SYongqiang Niu [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
39004121201SYongqiang Niu [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
39104121201SYongqiang Niu [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
39204121201SYongqiang Niu [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
39304121201SYongqiang Niu [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
39404121201SYongqiang Niu [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
39504121201SYongqiang Niu [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
39604121201SYongqiang Niu };
39704121201SYongqiang Niu
3982c9f8d1eSMoudy Ho static const unsigned int mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
3992c9f8d1eSMoudy Ho [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
4002c9f8d1eSMoudy Ho [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
4012c9f8d1eSMoudy Ho [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
4022c9f8d1eSMoudy Ho [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
4032c9f8d1eSMoudy Ho [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
4042c9f8d1eSMoudy Ho [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
4052c9f8d1eSMoudy Ho [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
4062c9f8d1eSMoudy Ho [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
4072c9f8d1eSMoudy Ho };
4082c9f8d1eSMoudy Ho
40915f17683SYongqiang Niu static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
41015f17683SYongqiang Niu [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
41115f17683SYongqiang Niu [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
41215f17683SYongqiang Niu [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
4134e8988c6Sjason-jh.lin [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
41415f17683SYongqiang Niu [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
41515f17683SYongqiang Niu [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
41615f17683SYongqiang Niu [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
41715f17683SYongqiang Niu [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
41815f17683SYongqiang Niu [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
41915f17683SYongqiang Niu [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
42015f17683SYongqiang Niu };
42115f17683SYongqiang Niu
42221370ecdSAllen-KH Cheng static const unsigned int mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
42321370ecdSAllen-KH Cheng [MUTEX_MOD_IDX_MDP_RDMA0] = MT8186_MUTEX_MOD_MDP_RDMA0,
42421370ecdSAllen-KH Cheng [MUTEX_MOD_IDX_MDP_RSZ0] = MT8186_MUTEX_MOD_MDP_RSZ0,
42521370ecdSAllen-KH Cheng [MUTEX_MOD_IDX_MDP_RSZ1] = MT8186_MUTEX_MOD_MDP_RSZ1,
42621370ecdSAllen-KH Cheng [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8186_MUTEX_MOD_MDP_TDSHP0,
42721370ecdSAllen-KH Cheng [MUTEX_MOD_IDX_MDP_WROT0] = MT8186_MUTEX_MOD_MDP_WROT0,
42821370ecdSAllen-KH Cheng [MUTEX_MOD_IDX_MDP_HDR0] = MT8186_MUTEX_MOD_MDP_HDR0,
42921370ecdSAllen-KH Cheng [MUTEX_MOD_IDX_MDP_AAL0] = MT8186_MUTEX_MOD_MDP_AAL0,
43021370ecdSAllen-KH Cheng [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0,
43121370ecdSAllen-KH Cheng };
43221370ecdSAllen-KH Cheng
43364bc37bfSNathan Lu static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
43464bc37bfSNathan Lu [DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0,
43564bc37bfSNathan Lu [DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0,
43664bc37bfSNathan Lu [DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0,
43764bc37bfSNathan Lu [DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0,
43864bc37bfSNathan Lu [DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0,
43964bc37bfSNathan Lu [DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0,
44064bc37bfSNathan Lu [DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0,
44164bc37bfSNathan Lu [DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0,
44264bc37bfSNathan Lu [DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0,
44364bc37bfSNathan Lu [DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE,
44464bc37bfSNathan Lu [DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
44564bc37bfSNathan Lu [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
44664bc37bfSNathan Lu [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
44764bc37bfSNathan Lu [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
44864bc37bfSNathan Lu };
44964bc37bfSNathan Lu
45013d9624dSYongqiang Niu static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
45113d9624dSYongqiang Niu [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
45213d9624dSYongqiang Niu [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
45313d9624dSYongqiang Niu [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
4544e8988c6Sjason-jh.lin [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
45513d9624dSYongqiang Niu [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
45613d9624dSYongqiang Niu [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
45713d9624dSYongqiang Niu [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
45813d9624dSYongqiang Niu [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
45913d9624dSYongqiang Niu [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
46013d9624dSYongqiang Niu [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
46113d9624dSYongqiang Niu [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
46213d9624dSYongqiang Niu };
46313d9624dSYongqiang Niu
4648fdb61f1Sjason-jh.lin static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
4658fdb61f1Sjason-jh.lin [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
4668fdb61f1Sjason-jh.lin [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
4678fdb61f1Sjason-jh.lin [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
4688fdb61f1Sjason-jh.lin [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
4698fdb61f1Sjason-jh.lin [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
4708fdb61f1Sjason-jh.lin [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
4718fdb61f1Sjason-jh.lin [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
4724e8988c6Sjason-jh.lin [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
4738fdb61f1Sjason-jh.lin [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
4748fdb61f1Sjason-jh.lin [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
4758fdb61f1Sjason-jh.lin [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
4768fdb61f1Sjason-jh.lin [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
4778fdb61f1Sjason-jh.lin [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
4784ea6aa89SNancy.Lin [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0,
4794ea6aa89SNancy.Lin [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1,
4804ea6aa89SNancy.Lin [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2,
4814ea6aa89SNancy.Lin [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3,
4824ea6aa89SNancy.Lin [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4,
4834ea6aa89SNancy.Lin [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5,
4844ea6aa89SNancy.Lin [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6,
4854ea6aa89SNancy.Lin [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7,
4864ea6aa89SNancy.Lin [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0,
4874ea6aa89SNancy.Lin [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1,
4884ea6aa89SNancy.Lin [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2,
4894ea6aa89SNancy.Lin [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
4904ea6aa89SNancy.Lin [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
4914ea6aa89SNancy.Lin [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
4924ea6aa89SNancy.Lin [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
4938fdb61f1Sjason-jh.lin };
4948fdb61f1Sjason-jh.lin
495549053b6SRoy-CW.Yeh static const unsigned int mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
496549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0,
497549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1,
498549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2,
499549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3,
500549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0,
501549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0,
502549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1,
503549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2,
504549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3,
505549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0,
506549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1,
507549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2,
508549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3,
509549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0,
510549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1,
511549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2,
512549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3,
513549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0,
514549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1,
515549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2,
516549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3,
517549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2,
518549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3,
519549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0,
520549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1,
521549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2,
522549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3,
523549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0,
524549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1,
525549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2,
526549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3,
527549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0,
528549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1,
529549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0,
530549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1,
531549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2,
532549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3,
533549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0,
534549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1,
535549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0,
536549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1,
537549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2,
538549053b6SRoy-CW.Yeh [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
539549053b6SRoy-CW.Yeh };
540549053b6SRoy-CW.Yeh
541141311b8SFabien Parent static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
542141311b8SFabien Parent [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
543141311b8SFabien Parent [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
544141311b8SFabien Parent [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0,
54544e36d75SAngeloGioacchino Del Regno [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER,
546141311b8SFabien Parent [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0,
547141311b8SFabien Parent [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0,
548141311b8SFabien Parent [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA,
549141311b8SFabien Parent [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0,
550141311b8SFabien Parent [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L,
551141311b8SFabien Parent [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0,
552141311b8SFabien Parent [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0,
553141311b8SFabien Parent [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1,
554141311b8SFabien Parent [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0,
555141311b8SFabien Parent };
556141311b8SFabien Parent
5578fdb61f1Sjason-jh.lin static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
558e1e4f7feSCK Hu [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
559e1e4f7feSCK Hu [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
560e1e4f7feSCK Hu [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
561e1e4f7feSCK Hu [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
562e1e4f7feSCK Hu [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1,
563e1e4f7feSCK Hu [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2,
564e1e4f7feSCK Hu [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
565e1e4f7feSCK Hu };
566e1e4f7feSCK Hu
5671b850150SAngeloGioacchino Del Regno static const unsigned int mt6795_mutex_sof[DDP_MUTEX_SOF_MAX] = {
5681b850150SAngeloGioacchino Del Regno [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
5691b850150SAngeloGioacchino Del Regno [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
5701b850150SAngeloGioacchino Del Regno [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
5711b850150SAngeloGioacchino Del Regno [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
5721b850150SAngeloGioacchino Del Regno };
5731b850150SAngeloGioacchino Del Regno
5748fdb61f1Sjason-jh.lin static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
575e1e4f7feSCK Hu [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
576e1e4f7feSCK Hu [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
577e1e4f7feSCK Hu [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
578e1e4f7feSCK Hu [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
579e1e4f7feSCK Hu };
580e1e4f7feSCK Hu
58104121201SYongqiang Niu /* Add EOF setting so overlay hardware can receive frame done irq */
5828fdb61f1Sjason-jh.lin static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
58304121201SYongqiang Niu [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
58404121201SYongqiang Niu [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
58504121201SYongqiang Niu [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
58604121201SYongqiang Niu };
58704121201SYongqiang Niu
58815f17683SYongqiang Niu static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
58915f17683SYongqiang Niu [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
59015f17683SYongqiang Niu [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
59115f17683SYongqiang Niu [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
59215f17683SYongqiang Niu };
59315f17683SYongqiang Niu
5948fdb61f1Sjason-jh.lin /*
5958fdb61f1Sjason-jh.lin * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
5968fdb61f1Sjason-jh.lin * select the EOF source and configure the EOF plus timing from the
5978fdb61f1Sjason-jh.lin * module that provides the timing signal.
5988fdb61f1Sjason-jh.lin * So that MUTEX can not only send a STREAM_DONE event to GCE
5998fdb61f1Sjason-jh.lin * but also detect the error at end of frame(EAEOF) when EOF signal
6008fdb61f1Sjason-jh.lin * arrives.
6018fdb61f1Sjason-jh.lin */
60264bc37bfSNathan Lu static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
60364bc37bfSNathan Lu [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
60464bc37bfSNathan Lu [MUTEX_SOF_DSI0] =
60564bc37bfSNathan Lu MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
60664bc37bfSNathan Lu [MUTEX_SOF_DP_INTF0] =
60764bc37bfSNathan Lu MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
60864bc37bfSNathan Lu };
60964bc37bfSNathan Lu
6108fdb61f1Sjason-jh.lin static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
6118fdb61f1Sjason-jh.lin [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
6128fdb61f1Sjason-jh.lin [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
6138fdb61f1Sjason-jh.lin [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
6148fdb61f1Sjason-jh.lin [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
6158fdb61f1Sjason-jh.lin [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
6168fdb61f1Sjason-jh.lin [MUTEX_SOF_DP_INTF0] =
6178fdb61f1Sjason-jh.lin MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
6188fdb61f1Sjason-jh.lin [MUTEX_SOF_DP_INTF1] =
6198fdb61f1Sjason-jh.lin MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
6208fdb61f1Sjason-jh.lin };
6218fdb61f1Sjason-jh.lin
622e1e4f7feSCK Hu static const struct mtk_mutex_data mt2701_mutex_driver_data = {
623e1e4f7feSCK Hu .mutex_mod = mt2701_mutex_mod,
624e1e4f7feSCK Hu .mutex_sof = mt2712_mutex_sof,
625e1e4f7feSCK Hu .mutex_mod_reg = MT2701_MUTEX0_MOD0,
626e1e4f7feSCK Hu .mutex_sof_reg = MT2701_MUTEX0_SOF0,
627e1e4f7feSCK Hu };
628e1e4f7feSCK Hu
629e1e4f7feSCK Hu static const struct mtk_mutex_data mt2712_mutex_driver_data = {
630e1e4f7feSCK Hu .mutex_mod = mt2712_mutex_mod,
631e1e4f7feSCK Hu .mutex_sof = mt2712_mutex_sof,
632e1e4f7feSCK Hu .mutex_mod_reg = MT2701_MUTEX0_MOD0,
633e1e4f7feSCK Hu .mutex_sof_reg = MT2701_MUTEX0_SOF0,
634e1e4f7feSCK Hu };
635e1e4f7feSCK Hu
6361b850150SAngeloGioacchino Del Regno static const struct mtk_mutex_data mt6795_mutex_driver_data = {
6371b850150SAngeloGioacchino Del Regno .mutex_mod = mt8173_mutex_mod,
6381b850150SAngeloGioacchino Del Regno .mutex_sof = mt6795_mutex_sof,
6391b850150SAngeloGioacchino Del Regno .mutex_mod_reg = MT2701_MUTEX0_MOD0,
6401b850150SAngeloGioacchino Del Regno .mutex_sof_reg = MT2701_MUTEX0_SOF0,
6411b850150SAngeloGioacchino Del Regno };
6421b850150SAngeloGioacchino Del Regno
643e1e4f7feSCK Hu static const struct mtk_mutex_data mt8167_mutex_driver_data = {
644e1e4f7feSCK Hu .mutex_mod = mt8167_mutex_mod,
645e1e4f7feSCK Hu .mutex_sof = mt8167_mutex_sof,
646e1e4f7feSCK Hu .mutex_mod_reg = MT2701_MUTEX0_MOD0,
647e1e4f7feSCK Hu .mutex_sof_reg = MT2701_MUTEX0_SOF0,
648e1e4f7feSCK Hu .no_clk = true,
649e1e4f7feSCK Hu };
650e1e4f7feSCK Hu
651e1e4f7feSCK Hu static const struct mtk_mutex_data mt8173_mutex_driver_data = {
652e1e4f7feSCK Hu .mutex_mod = mt8173_mutex_mod,
653e1e4f7feSCK Hu .mutex_sof = mt2712_mutex_sof,
654e1e4f7feSCK Hu .mutex_mod_reg = MT2701_MUTEX0_MOD0,
655e1e4f7feSCK Hu .mutex_sof_reg = MT2701_MUTEX0_SOF0,
656e1e4f7feSCK Hu };
657e1e4f7feSCK Hu
65804121201SYongqiang Niu static const struct mtk_mutex_data mt8183_mutex_driver_data = {
65904121201SYongqiang Niu .mutex_mod = mt8183_mutex_mod,
66004121201SYongqiang Niu .mutex_sof = mt8183_mutex_sof,
66104121201SYongqiang Niu .mutex_mod_reg = MT8183_MUTEX0_MOD0,
66204121201SYongqiang Niu .mutex_sof_reg = MT8183_MUTEX0_SOF0,
6632c9f8d1eSMoudy Ho .mutex_table_mod = mt8183_mutex_table_mod,
66404121201SYongqiang Niu .no_clk = true,
66504121201SYongqiang Niu };
66604121201SYongqiang Niu
66721370ecdSAllen-KH Cheng static const struct mtk_mutex_data mt8186_mdp_mutex_driver_data = {
66821370ecdSAllen-KH Cheng .mutex_mod_reg = MT8183_MUTEX0_MOD0,
66921370ecdSAllen-KH Cheng .mutex_sof_reg = MT8183_MUTEX0_SOF0,
67021370ecdSAllen-KH Cheng .mutex_table_mod = mt8186_mdp_mutex_table_mod,
67121370ecdSAllen-KH Cheng };
67221370ecdSAllen-KH Cheng
67315f17683SYongqiang Niu static const struct mtk_mutex_data mt8186_mutex_driver_data = {
67415f17683SYongqiang Niu .mutex_mod = mt8186_mutex_mod,
67515f17683SYongqiang Niu .mutex_sof = mt8186_mutex_sof,
67615f17683SYongqiang Niu .mutex_mod_reg = MT8183_MUTEX0_MOD0,
67715f17683SYongqiang Niu .mutex_sof_reg = MT8183_MUTEX0_SOF0,
67815f17683SYongqiang Niu };
67915f17683SYongqiang Niu
68064bc37bfSNathan Lu static const struct mtk_mutex_data mt8188_mutex_driver_data = {
68164bc37bfSNathan Lu .mutex_mod = mt8188_mutex_mod,
68264bc37bfSNathan Lu .mutex_sof = mt8188_mutex_sof,
68364bc37bfSNathan Lu .mutex_mod_reg = MT8183_MUTEX0_MOD0,
68464bc37bfSNathan Lu .mutex_sof_reg = MT8183_MUTEX0_SOF0,
68564bc37bfSNathan Lu };
68664bc37bfSNathan Lu
68713d9624dSYongqiang Niu static const struct mtk_mutex_data mt8192_mutex_driver_data = {
68813d9624dSYongqiang Niu .mutex_mod = mt8192_mutex_mod,
68913d9624dSYongqiang Niu .mutex_sof = mt8183_mutex_sof,
69013d9624dSYongqiang Niu .mutex_mod_reg = MT8183_MUTEX0_MOD0,
69113d9624dSYongqiang Niu .mutex_sof_reg = MT8183_MUTEX0_SOF0,
69213d9624dSYongqiang Niu };
69313d9624dSYongqiang Niu
6948fdb61f1Sjason-jh.lin static const struct mtk_mutex_data mt8195_mutex_driver_data = {
6958fdb61f1Sjason-jh.lin .mutex_mod = mt8195_mutex_mod,
6968fdb61f1Sjason-jh.lin .mutex_sof = mt8195_mutex_sof,
697537f8ffbSJason-JH.Lin .mutex_mod_reg = MT8183_MUTEX0_MOD0,
698537f8ffbSJason-JH.Lin .mutex_sof_reg = MT8183_MUTEX0_SOF0,
6998fdb61f1Sjason-jh.lin };
7008fdb61f1Sjason-jh.lin
701549053b6SRoy-CW.Yeh static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = {
702549053b6SRoy-CW.Yeh .mutex_sof = mt8195_mutex_sof,
703549053b6SRoy-CW.Yeh .mutex_mod_reg = MT8183_MUTEX0_MOD0,
704549053b6SRoy-CW.Yeh .mutex_sof_reg = MT8183_MUTEX0_SOF0,
705549053b6SRoy-CW.Yeh .mutex_table_mod = mt8195_mutex_table_mod,
706549053b6SRoy-CW.Yeh };
707549053b6SRoy-CW.Yeh
708141311b8SFabien Parent static const struct mtk_mutex_data mt8365_mutex_driver_data = {
709141311b8SFabien Parent .mutex_mod = mt8365_mutex_mod,
710141311b8SFabien Parent .mutex_sof = mt8183_mutex_sof,
711141311b8SFabien Parent .mutex_mod_reg = MT8183_MUTEX0_MOD0,
712141311b8SFabien Parent .mutex_sof_reg = MT8183_MUTEX0_SOF0,
713141311b8SFabien Parent .no_clk = true,
714141311b8SFabien Parent };
715141311b8SFabien Parent
mtk_mutex_get(struct device * dev)716e1e4f7feSCK Hu struct mtk_mutex *mtk_mutex_get(struct device *dev)
717e1e4f7feSCK Hu {
718e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
719e1e4f7feSCK Hu int i;
720e1e4f7feSCK Hu
721dc36768dSAngeloGioacchino Del Regno for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++)
722e1e4f7feSCK Hu if (!mtx->mutex[i].claimed) {
723e1e4f7feSCK Hu mtx->mutex[i].claimed = true;
724e1e4f7feSCK Hu return &mtx->mutex[i];
725e1e4f7feSCK Hu }
726e1e4f7feSCK Hu
727e1e4f7feSCK Hu return ERR_PTR(-EBUSY);
728e1e4f7feSCK Hu }
729e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_get);
730e1e4f7feSCK Hu
mtk_mutex_put(struct mtk_mutex * mutex)731e1e4f7feSCK Hu void mtk_mutex_put(struct mtk_mutex *mutex)
732e1e4f7feSCK Hu {
733e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
734e1e4f7feSCK Hu mutex[mutex->id]);
735e1e4f7feSCK Hu
736e1e4f7feSCK Hu WARN_ON(&mtx->mutex[mutex->id] != mutex);
737e1e4f7feSCK Hu
738e1e4f7feSCK Hu mutex->claimed = false;
739e1e4f7feSCK Hu }
740e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_put);
741e1e4f7feSCK Hu
mtk_mutex_prepare(struct mtk_mutex * mutex)742e1e4f7feSCK Hu int mtk_mutex_prepare(struct mtk_mutex *mutex)
743e1e4f7feSCK Hu {
744e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
745e1e4f7feSCK Hu mutex[mutex->id]);
746e1e4f7feSCK Hu return clk_prepare_enable(mtx->clk);
747e1e4f7feSCK Hu }
748e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_prepare);
749e1e4f7feSCK Hu
mtk_mutex_unprepare(struct mtk_mutex * mutex)750e1e4f7feSCK Hu void mtk_mutex_unprepare(struct mtk_mutex *mutex)
751e1e4f7feSCK Hu {
752e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
753e1e4f7feSCK Hu mutex[mutex->id]);
754e1e4f7feSCK Hu clk_disable_unprepare(mtx->clk);
755e1e4f7feSCK Hu }
756e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_unprepare);
757e1e4f7feSCK Hu
mtk_mutex_add_comp(struct mtk_mutex * mutex,enum mtk_ddp_comp_id id)758e1e4f7feSCK Hu void mtk_mutex_add_comp(struct mtk_mutex *mutex,
759e1e4f7feSCK Hu enum mtk_ddp_comp_id id)
760e1e4f7feSCK Hu {
761e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
762e1e4f7feSCK Hu mutex[mutex->id]);
763e1e4f7feSCK Hu unsigned int reg;
764e1e4f7feSCK Hu unsigned int sof_id;
765e1e4f7feSCK Hu unsigned int offset;
766e1e4f7feSCK Hu
767e1e4f7feSCK Hu WARN_ON(&mtx->mutex[mutex->id] != mutex);
768e1e4f7feSCK Hu
769e1e4f7feSCK Hu switch (id) {
770e1e4f7feSCK Hu case DDP_COMPONENT_DSI0:
771e1e4f7feSCK Hu sof_id = MUTEX_SOF_DSI0;
772e1e4f7feSCK Hu break;
773e1e4f7feSCK Hu case DDP_COMPONENT_DSI1:
774e1e4f7feSCK Hu sof_id = MUTEX_SOF_DSI0;
775e1e4f7feSCK Hu break;
776e1e4f7feSCK Hu case DDP_COMPONENT_DSI2:
777e1e4f7feSCK Hu sof_id = MUTEX_SOF_DSI2;
778e1e4f7feSCK Hu break;
779e1e4f7feSCK Hu case DDP_COMPONENT_DSI3:
780e1e4f7feSCK Hu sof_id = MUTEX_SOF_DSI3;
781e1e4f7feSCK Hu break;
782e1e4f7feSCK Hu case DDP_COMPONENT_DPI0:
783e1e4f7feSCK Hu sof_id = MUTEX_SOF_DPI0;
784e1e4f7feSCK Hu break;
785e1e4f7feSCK Hu case DDP_COMPONENT_DPI1:
786e1e4f7feSCK Hu sof_id = MUTEX_SOF_DPI1;
787e1e4f7feSCK Hu break;
7888fdb61f1Sjason-jh.lin case DDP_COMPONENT_DP_INTF0:
7898fdb61f1Sjason-jh.lin sof_id = MUTEX_SOF_DP_INTF0;
7908fdb61f1Sjason-jh.lin break;
7918150a0e3SNancy.Lin case DDP_COMPONENT_DP_INTF1:
7928150a0e3SNancy.Lin sof_id = MUTEX_SOF_DP_INTF1;
7938150a0e3SNancy.Lin break;
794e1e4f7feSCK Hu default:
795e1e4f7feSCK Hu if (mtx->data->mutex_mod[id] < 32) {
796e1e4f7feSCK Hu offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
797e1e4f7feSCK Hu mutex->id);
798e1e4f7feSCK Hu reg = readl_relaxed(mtx->regs + offset);
799e1e4f7feSCK Hu reg |= 1 << mtx->data->mutex_mod[id];
800e1e4f7feSCK Hu writel_relaxed(reg, mtx->regs + offset);
801e1e4f7feSCK Hu } else {
802e1e4f7feSCK Hu offset = DISP_REG_MUTEX_MOD2(mutex->id);
803e1e4f7feSCK Hu reg = readl_relaxed(mtx->regs + offset);
804e1e4f7feSCK Hu reg |= 1 << (mtx->data->mutex_mod[id] - 32);
805e1e4f7feSCK Hu writel_relaxed(reg, mtx->regs + offset);
806e1e4f7feSCK Hu }
807e1e4f7feSCK Hu return;
808e1e4f7feSCK Hu }
809e1e4f7feSCK Hu
810e1e4f7feSCK Hu writel_relaxed(mtx->data->mutex_sof[sof_id],
811e1e4f7feSCK Hu mtx->regs +
812e1e4f7feSCK Hu DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
813e1e4f7feSCK Hu }
814e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
815e1e4f7feSCK Hu
mtk_mutex_remove_comp(struct mtk_mutex * mutex,enum mtk_ddp_comp_id id)816e1e4f7feSCK Hu void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
817e1e4f7feSCK Hu enum mtk_ddp_comp_id id)
818e1e4f7feSCK Hu {
819e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
820e1e4f7feSCK Hu mutex[mutex->id]);
821e1e4f7feSCK Hu unsigned int reg;
822e1e4f7feSCK Hu unsigned int offset;
823e1e4f7feSCK Hu
824e1e4f7feSCK Hu WARN_ON(&mtx->mutex[mutex->id] != mutex);
825e1e4f7feSCK Hu
826e1e4f7feSCK Hu switch (id) {
827e1e4f7feSCK Hu case DDP_COMPONENT_DSI0:
828e1e4f7feSCK Hu case DDP_COMPONENT_DSI1:
829e1e4f7feSCK Hu case DDP_COMPONENT_DSI2:
830e1e4f7feSCK Hu case DDP_COMPONENT_DSI3:
831e1e4f7feSCK Hu case DDP_COMPONENT_DPI0:
832e1e4f7feSCK Hu case DDP_COMPONENT_DPI1:
8338fdb61f1Sjason-jh.lin case DDP_COMPONENT_DP_INTF0:
8348150a0e3SNancy.Lin case DDP_COMPONENT_DP_INTF1:
835e1e4f7feSCK Hu writel_relaxed(MUTEX_SOF_SINGLE_MODE,
836e1e4f7feSCK Hu mtx->regs +
837e1e4f7feSCK Hu DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
838e1e4f7feSCK Hu mutex->id));
839e1e4f7feSCK Hu break;
840e1e4f7feSCK Hu default:
841e1e4f7feSCK Hu if (mtx->data->mutex_mod[id] < 32) {
842e1e4f7feSCK Hu offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
843e1e4f7feSCK Hu mutex->id);
844e1e4f7feSCK Hu reg = readl_relaxed(mtx->regs + offset);
845e1e4f7feSCK Hu reg &= ~(1 << mtx->data->mutex_mod[id]);
846e1e4f7feSCK Hu writel_relaxed(reg, mtx->regs + offset);
847e1e4f7feSCK Hu } else {
848e1e4f7feSCK Hu offset = DISP_REG_MUTEX_MOD2(mutex->id);
849e1e4f7feSCK Hu reg = readl_relaxed(mtx->regs + offset);
850e1e4f7feSCK Hu reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
851e1e4f7feSCK Hu writel_relaxed(reg, mtx->regs + offset);
852e1e4f7feSCK Hu }
853e1e4f7feSCK Hu break;
854e1e4f7feSCK Hu }
855e1e4f7feSCK Hu }
856e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
857e1e4f7feSCK Hu
mtk_mutex_enable(struct mtk_mutex * mutex)858e1e4f7feSCK Hu void mtk_mutex_enable(struct mtk_mutex *mutex)
859e1e4f7feSCK Hu {
860e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
861e1e4f7feSCK Hu mutex[mutex->id]);
862e1e4f7feSCK Hu
863e1e4f7feSCK Hu WARN_ON(&mtx->mutex[mutex->id] != mutex);
864e1e4f7feSCK Hu
865e1e4f7feSCK Hu writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
866e1e4f7feSCK Hu }
867e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_enable);
868e1e4f7feSCK Hu
mtk_mutex_enable_by_cmdq(struct mtk_mutex * mutex,void * pkt)869e5758850SMoudy Ho int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt)
870e5758850SMoudy Ho {
871e5758850SMoudy Ho struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
872e5758850SMoudy Ho mutex[mutex->id]);
873e5758850SMoudy Ho struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt;
874e5758850SMoudy Ho
875e5758850SMoudy Ho WARN_ON(&mtx->mutex[mutex->id] != mutex);
876e5758850SMoudy Ho
877e5758850SMoudy Ho if (!mtx->cmdq_reg.size) {
878e5758850SMoudy Ho dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set");
879b34884b4SAngeloGioacchino Del Regno return -ENODEV;
880e5758850SMoudy Ho }
881e5758850SMoudy Ho
882e5758850SMoudy Ho cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys,
883e5758850SMoudy Ho mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1);
884e5758850SMoudy Ho return 0;
885e5758850SMoudy Ho }
886e5758850SMoudy Ho EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
887e5758850SMoudy Ho
mtk_mutex_disable(struct mtk_mutex * mutex)888e1e4f7feSCK Hu void mtk_mutex_disable(struct mtk_mutex *mutex)
889e1e4f7feSCK Hu {
890e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
891e1e4f7feSCK Hu mutex[mutex->id]);
892e1e4f7feSCK Hu
893e1e4f7feSCK Hu WARN_ON(&mtx->mutex[mutex->id] != mutex);
894e1e4f7feSCK Hu
895e1e4f7feSCK Hu writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
896e1e4f7feSCK Hu }
897e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_disable);
898e1e4f7feSCK Hu
mtk_mutex_acquire(struct mtk_mutex * mutex)899e1e4f7feSCK Hu void mtk_mutex_acquire(struct mtk_mutex *mutex)
900e1e4f7feSCK Hu {
901e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
902e1e4f7feSCK Hu mutex[mutex->id]);
903e1e4f7feSCK Hu u32 tmp;
904e1e4f7feSCK Hu
905e1e4f7feSCK Hu writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
906e1e4f7feSCK Hu writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id));
907e1e4f7feSCK Hu if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id),
908e1e4f7feSCK Hu tmp, tmp & INT_MUTEX, 1, 10000))
909e1e4f7feSCK Hu pr_err("could not acquire mutex %d\n", mutex->id);
910e1e4f7feSCK Hu }
911e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_acquire);
912e1e4f7feSCK Hu
mtk_mutex_release(struct mtk_mutex * mutex)913e1e4f7feSCK Hu void mtk_mutex_release(struct mtk_mutex *mutex)
914e1e4f7feSCK Hu {
915e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
916e1e4f7feSCK Hu mutex[mutex->id]);
917e1e4f7feSCK Hu
918e1e4f7feSCK Hu writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id));
919e1e4f7feSCK Hu }
920e1e4f7feSCK Hu EXPORT_SYMBOL_GPL(mtk_mutex_release);
921e1e4f7feSCK Hu
mtk_mutex_write_mod(struct mtk_mutex * mutex,enum mtk_mutex_mod_index idx,bool clear)922d0804085SMoudy Ho int mtk_mutex_write_mod(struct mtk_mutex *mutex,
923d0804085SMoudy Ho enum mtk_mutex_mod_index idx, bool clear)
924d0804085SMoudy Ho {
925d0804085SMoudy Ho struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
926d0804085SMoudy Ho mutex[mutex->id]);
927d0804085SMoudy Ho unsigned int reg;
928c54d2b99SRoy-CW.Yeh u32 reg_offset, id_offset = 0;
929d0804085SMoudy Ho
930d0804085SMoudy Ho WARN_ON(&mtx->mutex[mutex->id] != mutex);
931d0804085SMoudy Ho
932d0804085SMoudy Ho if (idx < MUTEX_MOD_IDX_MDP_RDMA0 ||
933d0804085SMoudy Ho idx >= MUTEX_MOD_IDX_MAX) {
934d0804085SMoudy Ho dev_err(mtx->dev, "Not supported MOD table index : %d", idx);
935d0804085SMoudy Ho return -EINVAL;
936d0804085SMoudy Ho }
937d0804085SMoudy Ho
938c54d2b99SRoy-CW.Yeh /*
939c54d2b99SRoy-CW.Yeh * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods
940c54d2b99SRoy-CW.Yeh * are present, hence requiring multiple 32-bits registers.
941c54d2b99SRoy-CW.Yeh *
942c54d2b99SRoy-CW.Yeh * The mutex_table_mod fully represents that by defining the number of
943c54d2b99SRoy-CW.Yeh * the mod sequentially, later used as a bit number, which can be more
944c54d2b99SRoy-CW.Yeh * than 0..31.
945c54d2b99SRoy-CW.Yeh *
946c54d2b99SRoy-CW.Yeh * In order to retain compatibility with older SoCs, we perform R/W on
947c54d2b99SRoy-CW.Yeh * the single 32 bits registers, but this requires us to translate the
948c54d2b99SRoy-CW.Yeh * mutex ID bit accordingly.
949c54d2b99SRoy-CW.Yeh */
950c54d2b99SRoy-CW.Yeh if (mtx->data->mutex_table_mod[idx] < 32) {
951c54d2b99SRoy-CW.Yeh reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
952d0804085SMoudy Ho mutex->id);
953c54d2b99SRoy-CW.Yeh } else {
954c54d2b99SRoy-CW.Yeh reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg,
955c54d2b99SRoy-CW.Yeh mutex->id);
956c54d2b99SRoy-CW.Yeh id_offset = 32;
957c54d2b99SRoy-CW.Yeh }
958d0804085SMoudy Ho
959c54d2b99SRoy-CW.Yeh reg = readl_relaxed(mtx->regs + reg_offset);
960d0804085SMoudy Ho if (clear)
961c54d2b99SRoy-CW.Yeh reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset);
962d0804085SMoudy Ho else
963c54d2b99SRoy-CW.Yeh reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset);
964d0804085SMoudy Ho
965c54d2b99SRoy-CW.Yeh writel_relaxed(reg, mtx->regs + reg_offset);
966d0804085SMoudy Ho
967d0804085SMoudy Ho return 0;
968d0804085SMoudy Ho }
969d0804085SMoudy Ho EXPORT_SYMBOL_GPL(mtk_mutex_write_mod);
970d0804085SMoudy Ho
mtk_mutex_write_sof(struct mtk_mutex * mutex,enum mtk_mutex_sof_index idx)971d0804085SMoudy Ho int mtk_mutex_write_sof(struct mtk_mutex *mutex,
972d0804085SMoudy Ho enum mtk_mutex_sof_index idx)
973d0804085SMoudy Ho {
974d0804085SMoudy Ho struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
975d0804085SMoudy Ho mutex[mutex->id]);
976d0804085SMoudy Ho
977d0804085SMoudy Ho WARN_ON(&mtx->mutex[mutex->id] != mutex);
978d0804085SMoudy Ho
979d0804085SMoudy Ho if (idx < MUTEX_SOF_IDX_SINGLE_MODE ||
980d0804085SMoudy Ho idx >= MUTEX_SOF_IDX_MAX) {
981d0804085SMoudy Ho dev_err(mtx->dev, "Not supported SOF index : %d", idx);
982d0804085SMoudy Ho return -EINVAL;
983d0804085SMoudy Ho }
984d0804085SMoudy Ho
985d0804085SMoudy Ho writel_relaxed(idx, mtx->regs +
986d0804085SMoudy Ho DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
987d0804085SMoudy Ho
988d0804085SMoudy Ho return 0;
989d0804085SMoudy Ho }
990d0804085SMoudy Ho EXPORT_SYMBOL_GPL(mtk_mutex_write_sof);
991d0804085SMoudy Ho
mtk_mutex_probe(struct platform_device * pdev)992e1e4f7feSCK Hu static int mtk_mutex_probe(struct platform_device *pdev)
993e1e4f7feSCK Hu {
994e1e4f7feSCK Hu struct device *dev = &pdev->dev;
995e1e4f7feSCK Hu struct mtk_mutex_ctx *mtx;
9964d3ddc9bSAngeloGioacchino Del Regno struct resource *regs;
997b34884b4SAngeloGioacchino Del Regno int i, ret;
998e1e4f7feSCK Hu
999e1e4f7feSCK Hu mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
1000e1e4f7feSCK Hu if (!mtx)
1001e1e4f7feSCK Hu return -ENOMEM;
1002e1e4f7feSCK Hu
1003dc36768dSAngeloGioacchino Del Regno for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++)
1004e1e4f7feSCK Hu mtx->mutex[i].id = i;
1005e1e4f7feSCK Hu
1006e1e4f7feSCK Hu mtx->data = of_device_get_match_data(dev);
1007e1e4f7feSCK Hu
1008e1e4f7feSCK Hu if (!mtx->data->no_clk) {
1009e1e4f7feSCK Hu mtx->clk = devm_clk_get(dev, NULL);
1010a73a7c41SYe Xingchen if (IS_ERR(mtx->clk))
1011a73a7c41SYe Xingchen return dev_err_probe(dev, PTR_ERR(mtx->clk), "Failed to get clock\n");
1012e1e4f7feSCK Hu }
1013e1e4f7feSCK Hu
10144d3ddc9bSAngeloGioacchino Del Regno mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
10154d3ddc9bSAngeloGioacchino Del Regno if (IS_ERR(mtx->regs)) {
10164d3ddc9bSAngeloGioacchino Del Regno dev_err(dev, "Failed to map mutex registers\n");
10174d3ddc9bSAngeloGioacchino Del Regno return PTR_ERR(mtx->regs);
1018e5758850SMoudy Ho }
10194d3ddc9bSAngeloGioacchino Del Regno mtx->addr = regs->start;
1020e5758850SMoudy Ho
1021b34884b4SAngeloGioacchino Del Regno /* CMDQ is optional */
1022e5758850SMoudy Ho ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
1023e5758850SMoudy Ho if (ret)
1024e5758850SMoudy Ho dev_dbg(dev, "No mediatek,gce-client-reg!\n");
1025e5758850SMoudy Ho
1026e1e4f7feSCK Hu platform_set_drvdata(pdev, mtx);
1027e1e4f7feSCK Hu
1028e1e4f7feSCK Hu return 0;
1029e1e4f7feSCK Hu }
1030e1e4f7feSCK Hu
1031e1e4f7feSCK Hu static const struct of_device_id mutex_driver_dt_match[] = {
103200ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data },
103300ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data },
103400ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data },
103500ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data },
103600ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data },
103700ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data },
103800ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8186-disp-mutex", .data = &mt8186_mutex_driver_data },
103900ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data },
104000ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data },
104100ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data },
104200ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data },
104300ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data },
104400ee1db7SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data },
104500ee1db7SAngeloGioacchino Del Regno { /* sentinel */ },
1046e1e4f7feSCK Hu };
1047e1e4f7feSCK Hu MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
1048e1e4f7feSCK Hu
1049b23ab27bSWei Yongjun static struct platform_driver mtk_mutex_driver = {
1050e1e4f7feSCK Hu .probe = mtk_mutex_probe,
1051e1e4f7feSCK Hu .driver = {
1052e1e4f7feSCK Hu .name = "mediatek-mutex",
1053e1e4f7feSCK Hu .of_match_table = mutex_driver_dt_match,
1054e1e4f7feSCK Hu },
1055e1e4f7feSCK Hu };
10561fccd1efSAngeloGioacchino Del Regno module_platform_driver(mtk_mutex_driver);
1057a7596e62SYongqiang Niu
1058a7596e62SYongqiang Niu MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");
1059a7596e62SYongqiang Niu MODULE_DESCRIPTION("MediaTek SoC MUTEX driver");
1060a7596e62SYongqiang Niu MODULE_LICENSE("GPL");
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