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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
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/openbmc/linux/arch/powerpc/sysdev/xics/
H A Dics-native.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/msi.h>
34 void __iomem *base; member
40 static void __iomem *ics_native_xive(struct ics_native *in, unsigned int vec) in ics_native_xive() argument
42 return in->base + 0x800 + ((vec - in->ibase) << 2); in ics_native_xive()
47 unsigned int vec = (unsigned int)irqd_to_hwirq(d); in ics_native_unmask_irq() local
52 pr_devel("ics-native: unmask virq %d [hw 0x%x]\n", d->irq, vec); in ics_native_unmask_irq()
54 if (vec < in->ibase || vec >= (in->ibase + in->icount)) in ics_native_unmask_irq()
57 server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0); in ics_native_unmask_irq()
58 out_be32(ics_native_xive(in, vec), (server << 8) | DEFAULT_PRIORITY); in ics_native_unmask_irq()
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/openbmc/linux/drivers/irqchip/
H A Dirq-loongson-pch-msi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
43 .name = "PCH PCI MSI",
54 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
56 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
59 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
60 return -ENOSPC; in pch_msi_allocate_hwirq()
63 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
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/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dls7a-pch.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2>;
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/openbmc/qemu/hw/xen/
H A Dxen_pt_msi.c5 * the COPYING file in the top-level directory.
14 #include "hw/i386/apic-msidef.h"
16 #include "hw/xen/xen-legacy-backend.h"
19 #define XEN_PT_AUTO_ASSIGN -1
69 static inline uint64_t msi_addr64(XenPTMSI *msi) in msi_addr64() argument
71 return (uint64_t)msi->addr_hi << 32 | msi->addr_lo; in msi_addr64()
83 return -1; in msi_msix_enable()
86 rc = xen_host_pci_get_word(&s->real_device, address, &val); in msi_msix_enable()
88 XEN_PT_ERR(&s->dev, "Failed to read MSI/MSI-X register (0x%x), rc:%d\n", in msi_msix_enable()
97 rc = xen_host_pci_set_word(&s->real_device, address, val); in msi_msix_enable()
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/openbmc/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_isr.c1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
19 /* base entry for packet ring/port */
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
207 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_tasklet()
210 if (ndev->mode == __NDEV_MODE_PF) { in nps_core_int_tasklet()
220 * nps_core_int_isr - interrupt handler for NITROX errors and
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
78 * msi = 1: only consider MSI interrupts
82 * the PCI-E SR-IOV standard).
88 static int msi = MSI_DEFAULT; variable
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H A Dadapter.h2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
62 * MSI-X interrupt index usage.
64 MSIX_FW = 0, /* MSI-X index for firmware Q */
65 MSIX_IQFLINT = 1, /* MSI-X index base for Ingress Qs */
90 * Per-"port" information. This is really per-Virtual Interface information
118 * absolute Queue ID base of the section of the Queue ID space allocated to
123 * SGE free-list queue state.
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/openbmc/qemu/docs/specs/
H A Dppc-spapr-xive.rst13 - *Legacy Compatibility Mode*
20 - *XIVE native exploitation mode*
34 ---------------
37 property ``ibm,arch-vec-5-platform-support`` in byte 23 and the OS
38 Selection for XIVE is indicated in the ``ibm,architecture-vec-5``
43 ``ic-mode`` which can be set on the command line. It can take the
53 ---------------
80 ic-mode kernel_irqchip
81 -------------- ----------------------------------------------
94 ic-mode kernel_irqchip
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-ismt.c65 #include <linux/dma-mapping.h>
70 #include <linux/io-64-nonatomic-lo-hi.h>
87 /* Hardware Descriptor Constants - Control Field */
96 /* Hardware Descriptor Constants - Status Field */
117 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
153 /* MSI Control Register (MSICTL) bit definitions */
154 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
174 struct ismt_desc *hw; /* descriptor virt base addr */
175 dma_addr_t io_rng_dma; /* descriptor HW base addr */
195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
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/openbmc/linux/drivers/ntb/hw/amd/
H A Dntb_hw_amd.c8 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
17 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
65 #define NTB_DESC "AMD(R) PCI-E Non-Transparent Bridge Driver"
78 if (idx < 0 || idx > ndev->mw_count) in ndev_mw_to_bar()
79 return -EINVAL; in ndev_mw_to_bar()
81 return ndev->dev_data->mw_idx << idx; in ndev_mw_to_bar()
87 return -EINVAL; in amd_ntb_mw_count()
89 return ntb_ndev(ntb)->mw_count; in amd_ntb_mw_count()
101 return -EINVAL; in amd_ntb_mw_get_align()
114 *size_max = pci_resource_len(ndev->ntb.pdev, bar); in amd_ntb_mw_get_align()
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/openbmc/linux/arch/alpha/kernel/
H A Dsys_marvel.c1 // SPDX-License-Identifier: GPL-2.0
52 * -----+-----+--------+--- in io7_device_interrupt()
57 * 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4) in io7_device_interrupt()
58 * 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4) in io7_device_interrupt()
61 irq = ((vector & 0xffff) - 0x800) >> 4; in io7_device_interrupt()
81 "%s for nonexistent io7 -- vec %x, pid %d\n", in io7_get_irq_ctl()
87 irq -= 16; /* subtract legacy bias */ in io7_get_irq_ctl()
91 "%s for invalid irq -- pid %d adjusted irq %x\n", in io7_get_irq_ctl()
96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
97 if (irq >= 0x80) /* MSI */ in io7_get_irq_ctl()
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/openbmc/linux/drivers/ntb/hw/intel/
H A Dntb_hw_gen1.c9 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
19 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
66 #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver"
74 #define bar0_off(base, bar) ((base) + ((bar) << 2)) argument
75 #define bar2_off(base, bar) bar0_off(base, (bar) - 2) argument
88 static int b2b_mw_idx = -1;
105 "XEON B2B USD BAR 2 64-bit address");
110 "XEON B2B USD BAR 4 64-bit address");
115 "XEON B2B USD split-BAR 4 32-bit address");
120 "XEON B2B USD split-BAR 5 32-bit address");
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/openbmc/linux/arch/ia64/kernel/
H A Dirq_ia64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 1998-2001 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
54 /* default base addr of IPI table */
61 * Legacy IRQ to IA-64 vector translation table.
73 [0 ... NR_IRQS - 1] = {
80 [0 ... IA64_NUM_VECTORS - 1] = -1
84 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
88 [0 ... NR_IRQS -1] = IRQ_UNUSED
98 return -ENOSPC; in find_unassigned_irq()
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dcxgb3_main.c2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
77 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
117 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
120 * msi = 2: choose from among all three options
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/openbmc/qemu/hw/loongarch/
H A Dvirt.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "hw/char/serial-mm.h"
21 #include "exec/address-spaces.h"
30 #include "hw/pci-host/ls7a.h"
31 #include "hw/pci-host/gpex.h"
36 #include "hw/acpi/aml-build.h"
37 #include "qapi/qapi-visit-common.h"
42 #include "hw/core/sysbus-fdt.h"
43 #include "hw/platform-bus.h"
45 #include "hw/mem/pc-dimm.h"
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/pcie/
H A Dinternal.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2003-2015, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-fh.h"
19 #include "iwl-csr.h"
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
22 #include "iwl-io.h"
23 #include "iwl-op-mode.h"
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
144 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
147 * msi = 2: choose from among all three options
148 * msi = 1: only consider MSI and INTx interrupts
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/openbmc/linux/arch/powerpc/kernel/
H A Dprom_init.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1996-2005 Paul Mackerras.
46 #include <asm/asm-prototypes.h>
47 #include <asm/ultravisor-api.h>
72 * On ppc32 we compile with -mrelocatable, which means that references
83 * arguments to call_prom should be 32-bit values.
125 __be64 base; member
216 * Error results ... some OF calls will return "-1" on error, some
222 #define PROM_ERROR (-1u)
236 return c1 < c2 ? -1 : 1; in prom_strcmp()
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/openbmc/qemu/hw/net/
H A Dtrace-events3 # allwinner-sun8i-emac.c
31 open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x"
32 open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x"
33 open_eth_update_irq(uint32_t v) "IRQ <- 0x%x"
39 open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x"
40 open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x"
41 open_eth_desc_read(uint32_t addr, uint32_t v) "DESC[0x%04x] -> 0x%08x"
42 open_eth_desc_write(uint32_t addr, uint32_t v) "DESC[0x%04x] <- 0x%08x"
52 # pcnet-pci.c
71 net_rx_pkt_l4_csum_calc_ph_csum(uint32_t cntr, uint16_t csl) "Pseudo-header: checksum counter %u, l…
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H A De1000e_core.c5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
41 #include "hw/pci/msi.h"
77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { in e1000e_process_ts_option()
94 e1000x_inc_reg_if_not_full(core->mac, IAC); in e1000e_raise_legacy_irq()
95 pci_set_irq(core->owner, 1); in e1000e_raise_legacy_irq()
102 pci_set_irq(core->owner, 0); in e1000e_lower_legacy_irq()
108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * in e1000e_intrmgr_rearm_timer()
109 timer->delay_resolution_ns; in e1000e_intrmgr_rearm_timer()
111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); in e1000e_intrmgr_rearm_timer()
113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); in e1000e_intrmgr_rearm_timer()
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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu.c1 // SPDX-License-Identifier: GPL-2.0
63 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_capabilities()
65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; in rvu_setup_hw_capabilities()
66 hw->cap.nix_fixed_txschq_mapping = false; in rvu_setup_hw_capabilities()
67 hw->cap.nix_shaping = true; in rvu_setup_hw_capabilities()
68 hw->cap.nix_tx_link_bp = true; in rvu_setup_hw_capabilities()
69 hw->cap.nix_rx_multicast = true; in rvu_setup_hw_capabilities()
70 hw->cap.nix_shaper_toggle_wait = false; in rvu_setup_hw_capabilities()
71 hw->cap.npc_hash_extract = false; in rvu_setup_hw_capabilities()
72 hw->cap.npc_exact_match_enabled = false; in rvu_setup_hw_capabilities()
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/openbmc/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
21 #include <linux/io-64-nonatomic-hi-lo.h>
32 if (__nn->dp.netdev) \
33 netdev_printk(lvl, __nn->dp.netdev, fmt, ## args); \
35 dev_printk(lvl, __nn->dp.dev, "ctrl: " fmt, ## args); \
48 if (__dp->netdev) \
49 netdev_warn(__dp->netdev, fmt, ## args); \
51 dev_warn(__dp->dev, fmt, ## args); \
118 #define D_IDX(ring, idx) ((idx) & ((ring)->cnt - 1))
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