18e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28e99ea8dSJohannes Berg /*
3d5050543SJohannes Berg * Copyright (C) 2003-2015, 2018-2023 Intel Corporation
48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH
68e99ea8dSJohannes Berg */
7e705c121SKalle Valo #ifndef __iwl_trans_int_pcie_h__
8e705c121SKalle Valo #define __iwl_trans_int_pcie_h__
9e705c121SKalle Valo
10e705c121SKalle Valo #include <linux/spinlock.h>
11e705c121SKalle Valo #include <linux/interrupt.h>
12e705c121SKalle Valo #include <linux/skbuff.h>
13e705c121SKalle Valo #include <linux/wait.h>
14e705c121SKalle Valo #include <linux/pci.h>
15e705c121SKalle Valo #include <linux/timer.h>
167c8d91ebSHaim Dreyfuss #include <linux/cpu.h>
17e705c121SKalle Valo
18e705c121SKalle Valo #include "iwl-fh.h"
19e705c121SKalle Valo #include "iwl-csr.h"
20e705c121SKalle Valo #include "iwl-trans.h"
21e705c121SKalle Valo #include "iwl-debug.h"
22e705c121SKalle Valo #include "iwl-io.h"
23e705c121SKalle Valo #include "iwl-op-mode.h"
24ff932f61SGolan Ben Ami #include "iwl-drv.h"
250cd1ad2dSMordechay Goodstein #include "queue/tx.h"
26f6fa5835SAlon Giladi #include "iwl-context-info.h"
27e705c121SKalle Valo
28e705c121SKalle Valo /*
29e705c121SKalle Valo * RX related structures and functions
30e705c121SKalle Valo */
31e705c121SKalle Valo #define RX_NUM_QUEUES 1
32e705c121SKalle Valo #define RX_POST_REQ_ALLOC 2
33e705c121SKalle Valo #define RX_CLAIM_REQ_ALLOC 8
3478485054SSara Sharon #define RX_PENDING_WATERMARK 16
351b493e30SGolan Ben Ami #define FIRST_RX_QUEUE 512
36e705c121SKalle Valo
37e705c121SKalle Valo struct iwl_host_cmd;
38e705c121SKalle Valo
39e705c121SKalle Valo /*This file includes the declaration that are internal to the
40e705c121SKalle Valo * trans_pcie layer */
41e705c121SKalle Valo
4296a6497bSSara Sharon /**
4396a6497bSSara Sharon * struct iwl_rx_mem_buffer
4496a6497bSSara Sharon * @page_dma: bus address of rxb page
4596a6497bSSara Sharon * @page: driver's pointer to the rxb page
4695fe8d89SJohannes Berg * @list: list entry for the membuffer
47b1753c62SSara Sharon * @invalid: rxb is in driver ownership - not owned by HW
4896a6497bSSara Sharon * @vid: index of this rxb in the global table
49cfdc20efSJohannes Berg * @offset: indicates which offset of the page (in bytes)
50cfdc20efSJohannes Berg * this buffer uses (if multiple RBs fit into one page)
5196a6497bSSara Sharon */
52e705c121SKalle Valo struct iwl_rx_mem_buffer {
53e705c121SKalle Valo dma_addr_t page_dma;
54e705c121SKalle Valo struct page *page;
55e705c121SKalle Valo struct list_head list;
56cfdc20efSJohannes Berg u32 offset;
5795fe8d89SJohannes Berg u16 vid;
5895fe8d89SJohannes Berg bool invalid;
59e705c121SKalle Valo };
60e705c121SKalle Valo
61e705c121SKalle Valo /**
62e705c121SKalle Valo * struct isr_statistics - interrupt statistics
63e705c121SKalle Valo *
64e705c121SKalle Valo */
65e705c121SKalle Valo struct isr_statistics {
66e705c121SKalle Valo u32 hw;
67e705c121SKalle Valo u32 sw;
68e705c121SKalle Valo u32 err_code;
69e705c121SKalle Valo u32 sch;
70e705c121SKalle Valo u32 alive;
71e705c121SKalle Valo u32 rfkill;
72e705c121SKalle Valo u32 ctkill;
73e705c121SKalle Valo u32 wakeup;
74e705c121SKalle Valo u32 rx;
75e705c121SKalle Valo u32 tx;
76e705c121SKalle Valo u32 unhandled;
77e705c121SKalle Valo };
78e705c121SKalle Valo
79cf495496SGolan Ben Ami /**
80cf495496SGolan Ben Ami * struct iwl_rx_transfer_desc - transfer descriptor
81cf495496SGolan Ben Ami * @addr: ptr to free buffer start address
82cf495496SGolan Ben Ami * @rbid: unique tag of the buffer
83cf495496SGolan Ben Ami * @reserved: reserved
84cf495496SGolan Ben Ami */
85cf495496SGolan Ben Ami struct iwl_rx_transfer_desc {
86cf495496SGolan Ben Ami __le16 rbid;
87f826faaaSJohannes Berg __le16 reserved[3];
88f826faaaSJohannes Berg __le64 addr;
89cf495496SGolan Ben Ami } __packed;
90cf495496SGolan Ben Ami
91f826faaaSJohannes Berg #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0)
92cf495496SGolan Ben Ami
93cf495496SGolan Ben Ami /**
94cf495496SGolan Ben Ami * struct iwl_rx_completion_desc - completion descriptor
95cf495496SGolan Ben Ami * @reserved1: reserved
96cf495496SGolan Ben Ami * @rbid: unique tag of the received buffer
97f826faaaSJohannes Berg * @flags: flags (0: fragmented, all others: reserved)
98cf495496SGolan Ben Ami * @reserved2: reserved
99cf495496SGolan Ben Ami */
100cf495496SGolan Ben Ami struct iwl_rx_completion_desc {
101f826faaaSJohannes Berg __le32 reserved1;
102cf495496SGolan Ben Ami __le16 rbid;
103f826faaaSJohannes Berg u8 flags;
104f826faaaSJohannes Berg u8 reserved2[25];
105cf495496SGolan Ben Ami } __packed;
106cf495496SGolan Ben Ami
107e705c121SKalle Valo /**
1085d19e208SJohannes Berg * struct iwl_rx_completion_desc_bz - Bz completion descriptor
1095d19e208SJohannes Berg * @rbid: unique tag of the received buffer
1105d19e208SJohannes Berg * @flags: flags (0: fragmented, all others: reserved)
1115d19e208SJohannes Berg * @reserved: reserved
1125d19e208SJohannes Berg */
1135d19e208SJohannes Berg struct iwl_rx_completion_desc_bz {
1145d19e208SJohannes Berg __le16 rbid;
1155d19e208SJohannes Berg u8 flags;
1165d19e208SJohannes Berg u8 reserved[1];
1175d19e208SJohannes Berg } __packed;
1185d19e208SJohannes Berg
1195d19e208SJohannes Berg /**
120e705c121SKalle Valo * struct iwl_rxq - Rx queue
12196a6497bSSara Sharon * @id: queue index
12296a6497bSSara Sharon * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
12396a6497bSSara Sharon * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
1243681021fSJohannes Berg * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's
125e705c121SKalle Valo * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
126bef99c7dSJohannes Berg * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd)
127bef99c7dSJohannes Berg * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd)
128e705c121SKalle Valo * @read: Shared index to newest available Rx buffer
129e705c121SKalle Valo * @write: Shared index to oldest written Rx packet
130e705c121SKalle Valo * @free_count: Number of pre-allocated buffers in rx_free
131e705c121SKalle Valo * @used_count: Number of RBDs handled to allocator to use for allocation
132e705c121SKalle Valo * @write_actual:
133e705c121SKalle Valo * @rx_free: list of RBDs with allocated RB ready for use
134e705c121SKalle Valo * @rx_used: list of RBDs with no RB attached
135e705c121SKalle Valo * @need_update: flag to indicate we need to update read/write index
136e705c121SKalle Valo * @rb_stts: driver's pointer to receive buffer status
137e705c121SKalle Valo * @rb_stts_dma: bus address of receive buffer status
138e705c121SKalle Valo * @lock:
13996a6497bSSara Sharon * @queue: actual rx queue. Not used for multi-rx queue.
140b1c860f6SJohannes Berg * @next_rb_is_fragment: indicates that the previous RB that we handled set
141b1c860f6SJohannes Berg * the fragmented flag, so the next one is still another fragment
142e705c121SKalle Valo *
143e705c121SKalle Valo * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
144e705c121SKalle Valo */
145e705c121SKalle Valo struct iwl_rxq {
14696a6497bSSara Sharon int id;
14796a6497bSSara Sharon void *bd;
148e705c121SKalle Valo dma_addr_t bd_dma;
1490307c839SGolan Ben Ami void *used_bd;
15096a6497bSSara Sharon dma_addr_t used_bd_dma;
151e705c121SKalle Valo u32 read;
152e705c121SKalle Valo u32 write;
153e705c121SKalle Valo u32 free_count;
154e705c121SKalle Valo u32 used_count;
155e705c121SKalle Valo u32 write_actual;
15696a6497bSSara Sharon u32 queue_size;
157e705c121SKalle Valo struct list_head rx_free;
158e705c121SKalle Valo struct list_head rx_used;
159b1c860f6SJohannes Berg bool need_update, next_rb_is_fragment;
1600307c839SGolan Ben Ami void *rb_stts;
161e705c121SKalle Valo dma_addr_t rb_stts_dma;
162e705c121SKalle Valo spinlock_t lock;
163bce97731SSara Sharon struct napi_struct napi;
164e705c121SKalle Valo struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
165e705c121SKalle Valo };
166e705c121SKalle Valo
167e705c121SKalle Valo /**
168e705c121SKalle Valo * struct iwl_rb_allocator - Rx allocator
169e705c121SKalle Valo * @req_pending: number of requests the allcator had not processed yet
170e705c121SKalle Valo * @req_ready: number of requests honored and ready for claiming
171e705c121SKalle Valo * @rbd_allocated: RBDs with pages allocated and ready to be handled to
172e705c121SKalle Valo * the queue. This is a list of &struct iwl_rx_mem_buffer
173e705c121SKalle Valo * @rbd_empty: RBDs with no page attached for allocator use. This is a list
174e705c121SKalle Valo * of &struct iwl_rx_mem_buffer
175e705c121SKalle Valo * @lock: protects the rbd_allocated and rbd_empty lists
176e705c121SKalle Valo * @alloc_wq: work queue for background calls
177e705c121SKalle Valo * @rx_alloc: work struct for background calls
178e705c121SKalle Valo */
179e705c121SKalle Valo struct iwl_rb_allocator {
180e705c121SKalle Valo atomic_t req_pending;
181e705c121SKalle Valo atomic_t req_ready;
182e705c121SKalle Valo struct list_head rbd_allocated;
183e705c121SKalle Valo struct list_head rbd_empty;
184e705c121SKalle Valo spinlock_t lock;
185e705c121SKalle Valo struct workqueue_struct *alloc_wq;
186e705c121SKalle Valo struct work_struct rx_alloc;
187e705c121SKalle Valo };
188e705c121SKalle Valo
189e705c121SKalle Valo /**
1900307c839SGolan Ben Ami * iwl_get_closed_rb_stts - get closed rb stts from different structs
1910307c839SGolan Ben Ami * @rxq - the rxq to get the rb stts from
1920307c839SGolan Ben Ami */
iwl_get_closed_rb_stts(struct iwl_trans * trans,struct iwl_rxq * rxq)1939fe75ad3SJohannes Berg static inline u16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
1940307c839SGolan Ben Ami struct iwl_rxq *rxq)
1950307c839SGolan Ben Ami {
1963681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1970307c839SGolan Ben Ami __le16 *rb_stts = rxq->rb_stts;
1980307c839SGolan Ben Ami
1999fe75ad3SJohannes Berg return le16_to_cpu(READ_ONCE(*rb_stts));
2000307c839SGolan Ben Ami } else {
2010307c839SGolan Ben Ami struct iwl_rb_status *rb_stts = rxq->rb_stts;
2020307c839SGolan Ben Ami
2039fe75ad3SJohannes Berg return le16_to_cpu(READ_ONCE(rb_stts->closed_rb_num)) & 0xFFF;
2040307c839SGolan Ben Ami }
2050307c839SGolan Ben Ami }
2060307c839SGolan Ben Ami
207f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS
208f7805b33SLior Cohen /**
209f7805b33SLior Cohen * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
210f7805b33SLior Cohen * debugfs file
211f7805b33SLior Cohen *
212f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
213f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
214f7805b33SLior Cohen * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
215f7805b33SLior Cohen * set the file can no longer be used.
216f7805b33SLior Cohen */
217f7805b33SLior Cohen enum iwl_fw_mon_dbgfs_state {
218f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_CLOSED,
219f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_OPEN,
220f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED,
221f7805b33SLior Cohen };
222f7805b33SLior Cohen #endif
223f7805b33SLior Cohen
224e705c121SKalle Valo /**
225496d83caSHaim Dreyfuss * enum iwl_shared_irq_flags - level of sharing for irq
226496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
227496d83caSHaim Dreyfuss * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
228496d83caSHaim Dreyfuss */
229496d83caSHaim Dreyfuss enum iwl_shared_irq_flags {
230496d83caSHaim Dreyfuss IWL_SHARED_IRQ_NON_RX = BIT(0),
231496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
232496d83caSHaim Dreyfuss };
233496d83caSHaim Dreyfuss
234496d83caSHaim Dreyfuss /**
2359b58419eSGolan Ben Ami * enum iwl_image_response_code - image response values
2369b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_DEF: the default value of the register
2379b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
2389b58419eSGolan Ben Ami * @IWL_IMAGE_RESP_FAIL: iml reading failed
2399b58419eSGolan Ben Ami */
2409b58419eSGolan Ben Ami enum iwl_image_response_code {
2419b58419eSGolan Ben Ami IWL_IMAGE_RESP_DEF = 0,
2429b58419eSGolan Ben Ami IWL_IMAGE_RESP_SUCCESS = 1,
2439b58419eSGolan Ben Ami IWL_IMAGE_RESP_FAIL = 2,
2449b58419eSGolan Ben Ami };
2459b58419eSGolan Ben Ami
2469b58419eSGolan Ben Ami /**
247f7805b33SLior Cohen * struct cont_rec: continuous recording data structure
248f7805b33SLior Cohen * @prev_wr_ptr: the last address that was read in monitor_data
249f7805b33SLior Cohen * debugfs file
250f7805b33SLior Cohen * @prev_wrap_cnt: the wrap count that was used during the last read in
251f7805b33SLior Cohen * monitor_data debugfs file
252f7805b33SLior Cohen * @state: the state of monitor_data debugfs file as described
253f7805b33SLior Cohen * in &iwl_fw_mon_dbgfs_state enum
254f7805b33SLior Cohen * @mutex: locked while reading from monitor_data debugfs file
255f7805b33SLior Cohen */
256f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS
257f7805b33SLior Cohen struct cont_rec {
258f7805b33SLior Cohen u32 prev_wr_ptr;
259f7805b33SLior Cohen u32 prev_wrap_cnt;
260f7805b33SLior Cohen u8 state;
261f7805b33SLior Cohen /* Used to sync monitor_data debugfs file with driver unload flow */
262f7805b33SLior Cohen struct mutex mutex;
263f7805b33SLior Cohen };
264f7805b33SLior Cohen #endif
265f7805b33SLior Cohen
266e63aafeaSJohannes Berg enum iwl_pcie_fw_reset_state {
267e63aafeaSJohannes Berg FW_RESET_IDLE,
268e63aafeaSJohannes Berg FW_RESET_REQUESTED,
269e63aafeaSJohannes Berg FW_RESET_OK,
270e63aafeaSJohannes Berg FW_RESET_ERROR,
271e63aafeaSJohannes Berg };
272e63aafeaSJohannes Berg
273f7805b33SLior Cohen /**
274c0941aceSMukesh Sisodiya * enum wl_pcie_imr_status - imr dma transfer state
275c0941aceSMukesh Sisodiya * @IMR_D2S_IDLE: default value of the dma transfer
276c0941aceSMukesh Sisodiya * @IMR_D2S_REQUESTED: dma transfer requested
277c0941aceSMukesh Sisodiya * @IMR_D2S_COMPLETED: dma transfer completed
278c0941aceSMukesh Sisodiya * @IMR_D2S_ERROR: dma transfer error
279c0941aceSMukesh Sisodiya */
280c0941aceSMukesh Sisodiya enum iwl_pcie_imr_status {
281c0941aceSMukesh Sisodiya IMR_D2S_IDLE,
282c0941aceSMukesh Sisodiya IMR_D2S_REQUESTED,
283c0941aceSMukesh Sisodiya IMR_D2S_COMPLETED,
284c0941aceSMukesh Sisodiya IMR_D2S_ERROR,
285c0941aceSMukesh Sisodiya };
286c0941aceSMukesh Sisodiya
287c0941aceSMukesh Sisodiya /**
288e705c121SKalle Valo * struct iwl_trans_pcie - PCIe transport specific data
289e705c121SKalle Valo * @rxq: all the RX queue data
29078485054SSara Sharon * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
29196a6497bSSara Sharon * @global_table: table mapping received VID from hw to rxb
292e705c121SKalle Valo * @rba: allocator for RX replenishing
293eda50cdeSSara Sharon * @ctxt_info: context information for FW self init
2942ee82402SGolan Ben Ami * @ctxt_info_gen3: context information for gen3 devices
2952ee82402SGolan Ben Ami * @prph_info: prph info for self init
2962ee82402SGolan Ben Ami * @prph_scratch: prph scratch for self init
2972ee82402SGolan Ben Ami * @ctxt_info_dma_addr: dma addr of context information
2982ee82402SGolan Ben Ami * @prph_info_dma_addr: dma addr of prph info
2992ee82402SGolan Ben Ami * @prph_scratch_dma_addr: dma addr of prph scratch
300eda50cdeSSara Sharon * @ctxt_info_dma_addr: dma addr of context information
301eda50cdeSSara Sharon * @init_dram: DRAM data of firmware image (including paging).
302eda50cdeSSara Sharon * Context information addresses will be taken from here.
303eda50cdeSSara Sharon * This is driver's local copy for keeping track of size and
304eda50cdeSSara Sharon * count for allocating and freeing the memory.
305310f60f5SJohannes Berg * @iml: image loader image virtual address
306310f60f5SJohannes Berg * @iml_dma_addr: image loader image DMA address
307e705c121SKalle Valo * @trans: pointer to the generic transport area
308e705c121SKalle Valo * @scd_base_addr: scheduler sram base address in SRAM
309e705c121SKalle Valo * @kw: keep warm address
3107c9c8477SAlon Giladi * @pnvm_data: holds info about pnvm payloads allocated in DRAM
3117c9c8477SAlon Giladi * @reduced_tables_data: holds info about power reduced tablse
3127c9c8477SAlon Giladi * payloads allocated in DRAM
313e705c121SKalle Valo * @pci_dev: basic pci-network driver stuff
314e705c121SKalle Valo * @hw_base: pci hardware address support
315e705c121SKalle Valo * @ucode_write_complete: indicates that the ucode has been copied.
316e705c121SKalle Valo * @ucode_write_waitq: wait queue for uCode load
317e705c121SKalle Valo * @cmd_queue - command queue number
3186c4fbcbcSEmmanuel Grumbach * @rx_buf_size: Rx buffer size
319e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue
320e705c121SKalle Valo * @rx_page_order: page order for receive buffer size
32180084e35SJohannes Berg * @rx_buf_bytes: RX buffer (RB) size in bytes
322e705c121SKalle Valo * @reg_lock: protect hw register access
323e705c121SKalle Valo * @mutex: to protect stop_device / start_fw / start_hw
324e705c121SKalle Valo * @cmd_in_flight: true when we have a host command in flight
325f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS
326f7805b33SLior Cohen * @fw_mon_data: fw continuous recording data
327f7805b33SLior Cohen #endif
3282e5d4a8fSHaim Dreyfuss * @msix_entries: array of MSI-X entries
3292e5d4a8fSHaim Dreyfuss * @msix_enabled: true if managed to enable MSI-X
330496d83caSHaim Dreyfuss * @shared_vec_mask: the type of causes the shared vector handles
331496d83caSHaim Dreyfuss * (see iwl_shared_irq_flags).
332496d83caSHaim Dreyfuss * @alloc_vecs: the number of interrupt vectors allocated by the OS
333496d83caSHaim Dreyfuss * @def_irq: default irq for non rx causes
3342e5d4a8fSHaim Dreyfuss * @fh_init_mask: initial unmasked fh causes
3352e5d4a8fSHaim Dreyfuss * @hw_init_mask: initial unmasked hw causes
3362e5d4a8fSHaim Dreyfuss * @fh_mask: current unmasked fh causes
3372e5d4a8fSHaim Dreyfuss * @hw_mask: current unmasked hw causes
33849564a80SLuca Coelho * @in_rescan: true if we have triggered a device rescan
3396cc6ba3aSTriebitz * @base_rb_stts: base virtual address of receive buffer status for all queues
3406cc6ba3aSTriebitz * @base_rb_stts_dma: base physical address of receive buffer status
341cfdc20efSJohannes Berg * @supported_dma_mask: DMA mask to validate the actual address against,
342cfdc20efSJohannes Berg * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device
343cfdc20efSJohannes Berg * @alloc_page_lock: spinlock for the page allocator
344cfdc20efSJohannes Berg * @alloc_page: allocated page to still use parts of
345cfdc20efSJohannes Berg * @alloc_page_used: how much of the allocated page was already used (bytes)
346c0941aceSMukesh Sisodiya * @imr_status: imr dma state machine
347c0941aceSMukesh Sisodiya * @wait_queue_head_t: imr wait queue for dma completion
348aa899e68SJohannes Berg * @rf_name: name/version of the CRF, if any
349e705c121SKalle Valo */
350e705c121SKalle Valo struct iwl_trans_pcie {
35178485054SSara Sharon struct iwl_rxq *rxq;
352c042f0c7SJohannes Berg struct iwl_rx_mem_buffer *rx_pool;
353c042f0c7SJohannes Berg struct iwl_rx_mem_buffer **global_table;
354e705c121SKalle Valo struct iwl_rb_allocator rba;
3552ee82402SGolan Ben Ami union {
356eda50cdeSSara Sharon struct iwl_context_info *ctxt_info;
3572ee82402SGolan Ben Ami struct iwl_context_info_gen3 *ctxt_info_gen3;
3582ee82402SGolan Ben Ami };
3592ee82402SGolan Ben Ami struct iwl_prph_info *prph_info;
3602ee82402SGolan Ben Ami struct iwl_prph_scratch *prph_scratch;
361310f60f5SJohannes Berg void *iml;
362eda50cdeSSara Sharon dma_addr_t ctxt_info_dma_addr;
3632ee82402SGolan Ben Ami dma_addr_t prph_info_dma_addr;
3642ee82402SGolan Ben Ami dma_addr_t prph_scratch_dma_addr;
3652ee82402SGolan Ben Ami dma_addr_t iml_dma_addr;
366e705c121SKalle Valo struct iwl_trans *trans;
367e705c121SKalle Valo
368e705c121SKalle Valo struct net_device napi_dev;
369e705c121SKalle Valo
370e705c121SKalle Valo /* INT ICT Table */
371e705c121SKalle Valo __le32 *ict_tbl;
372e705c121SKalle Valo dma_addr_t ict_tbl_dma;
373e705c121SKalle Valo int ict_index;
374e705c121SKalle Valo bool use_ict;
375326477e4SJohannes Berg bool is_down, opmode_down;
376c5bf4fa1SJohannes Berg s8 debug_rfkill;
377e705c121SKalle Valo struct isr_statistics isr_stats;
378e705c121SKalle Valo
379e705c121SKalle Valo spinlock_t irq_lock;
380e705c121SKalle Valo struct mutex mutex;
381e705c121SKalle Valo u32 inta_mask;
382e705c121SKalle Valo u32 scd_base_addr;
383e705c121SKalle Valo struct iwl_dma_ptr kw;
384e705c121SKalle Valo
385f6fa5835SAlon Giladi /* pnvm data */
3867c9c8477SAlon Giladi struct iwl_dram_regions pnvm_data;
3877c9c8477SAlon Giladi struct iwl_dram_regions reduced_tables_data;
3886654cd4eSLuca Coelho
389b2a3b1c1SSara Sharon struct iwl_txq *txq_memory;
390e705c121SKalle Valo
391e705c121SKalle Valo /* PCI bus related data */
392e705c121SKalle Valo struct pci_dev *pci_dev;
3933827cb59SJohannes Berg u8 __iomem *hw_base;
394e705c121SKalle Valo
395e705c121SKalle Valo bool ucode_write_complete;
396e5f3f215SHaim Dreyfuss bool sx_complete;
397e705c121SKalle Valo wait_queue_head_t ucode_write_waitq;
398e5f3f215SHaim Dreyfuss wait_queue_head_t sx_waitq;
399e705c121SKalle Valo
400e705c121SKalle Valo u8 n_no_reclaim_cmds;
401e705c121SKalle Valo u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
402c042f0c7SJohannes Berg u16 num_rx_bufs;
403e705c121SKalle Valo
4046c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size;
405e705c121SKalle Valo bool scd_set_active;
406a6d24fadSRajat Jain bool pcie_dbg_dumped_once;
407e705c121SKalle Valo u32 rx_page_order;
40880084e35SJohannes Berg u32 rx_buf_bytes;
409cfdc20efSJohannes Berg u32 supported_dma_mask;
410cfdc20efSJohannes Berg
411cfdc20efSJohannes Berg /* allocator lock for the two values below */
412cfdc20efSJohannes Berg spinlock_t alloc_page_lock;
413cfdc20efSJohannes Berg struct page *alloc_page;
414cfdc20efSJohannes Berg u32 alloc_page_used;
415e705c121SKalle Valo
416e705c121SKalle Valo /*protect hw register */
417e705c121SKalle Valo spinlock_t reg_lock;
418e705c121SKalle Valo bool cmd_hold_nic_awake;
419e705c121SKalle Valo
420f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS
421f7805b33SLior Cohen struct cont_rec fw_mon_data;
422f7805b33SLior Cohen #endif
423f7805b33SLior Cohen
4242e5d4a8fSHaim Dreyfuss struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
4252e5d4a8fSHaim Dreyfuss bool msix_enabled;
426496d83caSHaim Dreyfuss u8 shared_vec_mask;
427496d83caSHaim Dreyfuss u32 alloc_vecs;
428496d83caSHaim Dreyfuss u32 def_irq;
4292e5d4a8fSHaim Dreyfuss u32 fh_init_mask;
4302e5d4a8fSHaim Dreyfuss u32 hw_init_mask;
4312e5d4a8fSHaim Dreyfuss u32 fh_mask;
4322e5d4a8fSHaim Dreyfuss u32 hw_mask;
4337c8d91ebSHaim Dreyfuss cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
43449564a80SLuca Coelho u16 tx_cmd_queue_size;
43549564a80SLuca Coelho bool in_rescan;
4366cc6ba3aSTriebitz
4376cc6ba3aSTriebitz void *base_rb_stts;
4386cc6ba3aSTriebitz dma_addr_t base_rb_stts_dma;
439906d4eb8SJohannes Berg
440906d4eb8SJohannes Berg bool fw_reset_handshake;
441e63aafeaSJohannes Berg enum iwl_pcie_fw_reset_state fw_reset_state;
442906d4eb8SJohannes Berg wait_queue_head_t fw_reset_waitq;
443c0941aceSMukesh Sisodiya enum iwl_pcie_imr_status imr_status;
444c0941aceSMukesh Sisodiya wait_queue_head_t imr_waitq;
445aa899e68SJohannes Berg char rf_name[32];
446e705c121SKalle Valo };
447e705c121SKalle Valo
44885e5a387SJohannes Berg static inline struct iwl_trans_pcie *
IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans * trans)44985e5a387SJohannes Berg IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
45085e5a387SJohannes Berg {
45185e5a387SJohannes Berg return (void *)trans->trans_specific;
45285e5a387SJohannes Berg }
453e705c121SKalle Valo
iwl_pcie_clear_irq(struct iwl_trans * trans,int queue)45425edc8f2SJohannes Berg static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
455ff932f61SGolan Ben Ami {
456ff932f61SGolan Ben Ami /*
457ff932f61SGolan Ben Ami * Before sending the interrupt the HW disables it to prevent
458ff932f61SGolan Ben Ami * a nested interrupt. This is done by writing 1 to the corresponding
459ff932f61SGolan Ben Ami * bit in the mask register. After handling the interrupt, it should be
460ff932f61SGolan Ben Ami * re-enabled by clearing this bit. This register is defined as
461ff932f61SGolan Ben Ami * write 1 clear (W1C) register, meaning that it's being clear
462ff932f61SGolan Ben Ami * by writing 1 to the bit.
463ff932f61SGolan Ben Ami */
46425edc8f2SJohannes Berg iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
465ff932f61SGolan Ben Ami }
466ff932f61SGolan Ben Ami
467e705c121SKalle Valo static inline struct iwl_trans *
iwl_trans_pcie_get_trans(struct iwl_trans_pcie * trans_pcie)468e705c121SKalle Valo iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
469e705c121SKalle Valo {
470e705c121SKalle Valo return container_of((void *)trans_pcie, struct iwl_trans,
471e705c121SKalle Valo trans_specific);
472e705c121SKalle Valo }
473e705c121SKalle Valo
474e705c121SKalle Valo /*
475e705c121SKalle Valo * Convention: trans API functions: iwl_trans_pcie_XXX
476e705c121SKalle Valo * Other functions: iwl_pcie_XXX
477e705c121SKalle Valo */
4787e8258c0SLuca Coelho struct iwl_trans
4797e8258c0SLuca Coelho *iwl_trans_pcie_alloc(struct pci_dev *pdev,
480e705c121SKalle Valo const struct pci_device_id *ent,
4817e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans);
482e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans);
4837c9c8477SAlon Giladi void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
484f6fa5835SAlon Giladi struct device *dev);
485e705c121SKalle Valo
486c544d89bSJohannes Berg bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
487c544d89bSJohannes Berg #define _iwl_trans_pcie_grab_nic_access(trans) \
488c544d89bSJohannes Berg __cond_lock(nic_access_nobh, \
489c544d89bSJohannes Berg likely(__iwl_trans_pcie_grab_nic_access(trans)))
490c544d89bSJohannes Berg
491e705c121SKalle Valo /*****************************************************
492e705c121SKalle Valo * RX
493e705c121SKalle Valo ******************************************************/
494e705c121SKalle Valo int iwl_pcie_rx_init(struct iwl_trans *trans);
495eda50cdeSSara Sharon int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
4962e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
497e705c121SKalle Valo irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
4982e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
4992e5d4a8fSHaim Dreyfuss irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
500e705c121SKalle Valo int iwl_pcie_rx_stop(struct iwl_trans *trans);
501e705c121SKalle Valo void iwl_pcie_rx_free(struct iwl_trans *trans);
502ff932f61SGolan Ben Ami void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
503ff932f61SGolan Ben Ami void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
5045af2bb31SGregory Greenman void iwl_pcie_rx_napi_sync(struct iwl_trans *trans);
505ff932f61SGolan Ben Ami void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
506ff932f61SGolan Ben Ami struct iwl_rxq *rxq);
507e705c121SKalle Valo
508e705c121SKalle Valo /*****************************************************
509e705c121SKalle Valo * ICT - interrupt handling
510e705c121SKalle Valo ******************************************************/
511e705c121SKalle Valo irqreturn_t iwl_pcie_isr(int irq, void *data);
512e705c121SKalle Valo int iwl_pcie_alloc_ict(struct iwl_trans *trans);
513e705c121SKalle Valo void iwl_pcie_free_ict(struct iwl_trans *trans);
514e705c121SKalle Valo void iwl_pcie_reset_ict(struct iwl_trans *trans);
515e705c121SKalle Valo void iwl_pcie_disable_ict(struct iwl_trans *trans);
516e705c121SKalle Valo
517e705c121SKalle Valo /*****************************************************
518e705c121SKalle Valo * TX / HCMD
519e705c121SKalle Valo ******************************************************/
520e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans);
521e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
522e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans);
523e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans);
524dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
525e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg,
526e705c121SKalle Valo unsigned int wdg_timeout);
527e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
528e705c121SKalle Valo bool configure_scd);
52942db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
53042db09c1SLiad Kaufman bool shared_mode);
531e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
532a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int txq_id);
533e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
534e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
535e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
536e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb);
537e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
538e705c121SKalle Valo
539e705c121SKalle Valo /*****************************************************
540e705c121SKalle Valo * Error handling
541e705c121SKalle Valo ******************************************************/
542e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans);
543e705c121SKalle Valo
544e705c121SKalle Valo /*****************************************************
545e705c121SKalle Valo * Helpers
546e705c121SKalle Valo ******************************************************/
_iwl_disable_interrupts(struct iwl_trans * trans)547f16c3ebfSEmmanuel Grumbach static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
548e705c121SKalle Valo {
5492e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
550e705c121SKalle Valo
5512e5d4a8fSHaim Dreyfuss clear_bit(STATUS_INT_ENABLED, &trans->status);
5522e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) {
553e705c121SKalle Valo /* disable interrupts from uCode/NIC to host */
554e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, 0x00000000);
555e705c121SKalle Valo
556e705c121SKalle Valo /* acknowledge/clear/reset any interrupts still pending
557e705c121SKalle Valo * from uCode or flow handler (Rx/Tx DMA) */
558e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xffffffff);
559e705c121SKalle Valo iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
5602e5d4a8fSHaim Dreyfuss } else {
5612e5d4a8fSHaim Dreyfuss /* disable all the interrupt we might use */
5622e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
5632e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask);
5642e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
5652e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask);
5662e5d4a8fSHaim Dreyfuss }
567e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
568e705c121SKalle Valo }
569e705c121SKalle Valo
iwl_pcie_get_num_sections(const struct fw_img * fw,int start)5702ee82402SGolan Ben Ami static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
5712ee82402SGolan Ben Ami int start)
5722ee82402SGolan Ben Ami {
5732ee82402SGolan Ben Ami int i = 0;
5742ee82402SGolan Ben Ami
5752ee82402SGolan Ben Ami while (start < fw->num_sec &&
5762ee82402SGolan Ben Ami fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
5772ee82402SGolan Ben Ami fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
5782ee82402SGolan Ben Ami start++;
5792ee82402SGolan Ben Ami i++;
5802ee82402SGolan Ben Ami }
5812ee82402SGolan Ben Ami
5822ee82402SGolan Ben Ami return i;
5832ee82402SGolan Ben Ami }
5842ee82402SGolan Ben Ami
iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans * trans)5852ee82402SGolan Ben Ami static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
5862ee82402SGolan Ben Ami {
587505a00c0SShahar S Matityahu struct iwl_self_init_dram *dram = &trans->init_dram;
5882ee82402SGolan Ben Ami int i;
5892ee82402SGolan Ben Ami
5902ee82402SGolan Ben Ami if (!dram->fw) {
5912ee82402SGolan Ben Ami WARN_ON(dram->fw_cnt);
5922ee82402SGolan Ben Ami return;
5932ee82402SGolan Ben Ami }
5942ee82402SGolan Ben Ami
5952ee82402SGolan Ben Ami for (i = 0; i < dram->fw_cnt; i++)
5962ee82402SGolan Ben Ami dma_free_coherent(trans->dev, dram->fw[i].size,
5972ee82402SGolan Ben Ami dram->fw[i].block, dram->fw[i].physical);
5982ee82402SGolan Ben Ami
5992ee82402SGolan Ben Ami kfree(dram->fw);
6002ee82402SGolan Ben Ami dram->fw_cnt = 0;
6012ee82402SGolan Ben Ami dram->fw = NULL;
6022ee82402SGolan Ben Ami }
6032ee82402SGolan Ben Ami
iwl_disable_interrupts(struct iwl_trans * trans)604f16c3ebfSEmmanuel Grumbach static inline void iwl_disable_interrupts(struct iwl_trans *trans)
605f16c3ebfSEmmanuel Grumbach {
606f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
607f16c3ebfSEmmanuel Grumbach
60825edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock);
609f16c3ebfSEmmanuel Grumbach _iwl_disable_interrupts(trans);
61025edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock);
611f16c3ebfSEmmanuel Grumbach }
612f16c3ebfSEmmanuel Grumbach
_iwl_enable_interrupts(struct iwl_trans * trans)613f16c3ebfSEmmanuel Grumbach static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
614e705c121SKalle Valo {
615e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
616e705c121SKalle Valo
617e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
618e705c121SKalle Valo set_bit(STATUS_INT_ENABLED, &trans->status);
6192e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) {
620e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK;
621e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
6222e5d4a8fSHaim Dreyfuss } else {
6232e5d4a8fSHaim Dreyfuss /*
6242e5d4a8fSHaim Dreyfuss * fh/hw_mask keeps all the unmasked causes.
6252e5d4a8fSHaim Dreyfuss * Unlike msi, in msix cause is enabled when it is unset.
6262e5d4a8fSHaim Dreyfuss */
6272e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask;
6282e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask;
6292e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
6302e5d4a8fSHaim Dreyfuss ~trans_pcie->fh_mask);
6312e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
6322e5d4a8fSHaim Dreyfuss ~trans_pcie->hw_mask);
6332e5d4a8fSHaim Dreyfuss }
6342e5d4a8fSHaim Dreyfuss }
6352e5d4a8fSHaim Dreyfuss
iwl_enable_interrupts(struct iwl_trans * trans)636f16c3ebfSEmmanuel Grumbach static inline void iwl_enable_interrupts(struct iwl_trans *trans)
637f16c3ebfSEmmanuel Grumbach {
638f16c3ebfSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
639f16c3ebfSEmmanuel Grumbach
64025edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock);
641f16c3ebfSEmmanuel Grumbach _iwl_enable_interrupts(trans);
64225edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock);
643f16c3ebfSEmmanuel Grumbach }
iwl_enable_hw_int_msk_msix(struct iwl_trans * trans,u32 msk)6442e5d4a8fSHaim Dreyfuss static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
6452e5d4a8fSHaim Dreyfuss {
6462e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6472e5d4a8fSHaim Dreyfuss
6482e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
6492e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = msk;
6502e5d4a8fSHaim Dreyfuss }
6512e5d4a8fSHaim Dreyfuss
iwl_enable_fh_int_msk_msix(struct iwl_trans * trans,u32 msk)6522e5d4a8fSHaim Dreyfuss static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
6532e5d4a8fSHaim Dreyfuss {
6542e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
6552e5d4a8fSHaim Dreyfuss
6562e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
6572e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = msk;
658e705c121SKalle Valo }
659e705c121SKalle Valo
iwl_enable_fw_load_int(struct iwl_trans * trans)660a6bd005fSEmmanuel Grumbach static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
661a6bd005fSEmmanuel Grumbach {
662a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
663a6bd005fSEmmanuel Grumbach
664a6bd005fSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
6652e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) {
666a6bd005fSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
667a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
6682e5d4a8fSHaim Dreyfuss } else {
6692e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
6702e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask);
6712e5d4a8fSHaim Dreyfuss iwl_enable_fh_int_msk_msix(trans,
6722e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
6732e5d4a8fSHaim Dreyfuss }
674a6bd005fSEmmanuel Grumbach }
675a6bd005fSEmmanuel Grumbach
iwl_enable_fw_load_int_ctx_info(struct iwl_trans * trans)676ed3e4c6dSEmmanuel Grumbach static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
677ed3e4c6dSEmmanuel Grumbach {
678ed3e4c6dSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
679ed3e4c6dSEmmanuel Grumbach
680ed3e4c6dSEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
681ed3e4c6dSEmmanuel Grumbach
682ed3e4c6dSEmmanuel Grumbach if (!trans_pcie->msix_enabled) {
683ed3e4c6dSEmmanuel Grumbach /*
684ed3e4c6dSEmmanuel Grumbach * When we'll receive the ALIVE interrupt, the ISR will call
685ed3e4c6dSEmmanuel Grumbach * iwl_enable_fw_load_int_ctx_info again to set the ALIVE
686ed3e4c6dSEmmanuel Grumbach * interrupt (which is not really needed anymore) but also the
687ed3e4c6dSEmmanuel Grumbach * RX interrupt which will allow us to receive the ALIVE
688ed3e4c6dSEmmanuel Grumbach * notification (which is Rx) and continue the flow.
689ed3e4c6dSEmmanuel Grumbach */
690ed3e4c6dSEmmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX;
691ed3e4c6dSEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
692ed3e4c6dSEmmanuel Grumbach } else {
693ed3e4c6dSEmmanuel Grumbach iwl_enable_hw_int_msk_msix(trans,
694ed3e4c6dSEmmanuel Grumbach MSIX_HW_INT_CAUSES_REG_ALIVE);
695ed3e4c6dSEmmanuel Grumbach /*
696ed3e4c6dSEmmanuel Grumbach * Leave all the FH causes enabled to get the ALIVE
697ed3e4c6dSEmmanuel Grumbach * notification.
698ed3e4c6dSEmmanuel Grumbach */
699ed3e4c6dSEmmanuel Grumbach iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
700ed3e4c6dSEmmanuel Grumbach }
701ed3e4c6dSEmmanuel Grumbach }
702ed3e4c6dSEmmanuel Grumbach
queue_name(struct device * dev,struct iwl_trans_pcie * trans_p,int i)703ff932f61SGolan Ben Ami static inline const char *queue_name(struct device *dev,
704ff932f61SGolan Ben Ami struct iwl_trans_pcie *trans_p, int i)
705ff932f61SGolan Ben Ami {
706ff932f61SGolan Ben Ami if (trans_p->shared_vec_mask) {
707ff932f61SGolan Ben Ami int vec = trans_p->shared_vec_mask &
708ff932f61SGolan Ben Ami IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
709ff932f61SGolan Ben Ami
710ff932f61SGolan Ben Ami if (i == 0)
71102289645SLuca Coelho return DRV_NAME ":shared_IRQ";
712ff932f61SGolan Ben Ami
713ff932f61SGolan Ben Ami return devm_kasprintf(dev, GFP_KERNEL,
71402289645SLuca Coelho DRV_NAME ":queue_%d", i + vec);
715ff932f61SGolan Ben Ami }
716ff932f61SGolan Ben Ami if (i == 0)
71702289645SLuca Coelho return DRV_NAME ":default_queue";
718ff932f61SGolan Ben Ami
719ff932f61SGolan Ben Ami if (i == trans_p->alloc_vecs - 1)
720ff932f61SGolan Ben Ami return DRV_NAME ":exception";
721ff932f61SGolan Ben Ami
722ff932f61SGolan Ben Ami return devm_kasprintf(dev, GFP_KERNEL,
72302289645SLuca Coelho DRV_NAME ":queue_%d", i);
724ff932f61SGolan Ben Ami }
725ff932f61SGolan Ben Ami
iwl_enable_rfkill_int(struct iwl_trans * trans)726e705c121SKalle Valo static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
727e705c121SKalle Valo {
728e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
729e705c121SKalle Valo
730e705c121SKalle Valo IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
7312e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) {
732e705c121SKalle Valo trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
733e705c121SKalle Valo iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
7342e5d4a8fSHaim Dreyfuss } else {
7352e5d4a8fSHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
7362e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask);
7372e5d4a8fSHaim Dreyfuss iwl_enable_hw_int_msk_msix(trans,
7382e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL);
7392e5d4a8fSHaim Dreyfuss }
740ae5bb2a6SJohannes Berg
741286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
742ae5bb2a6SJohannes Berg /*
743ae5bb2a6SJohannes Berg * On 9000-series devices this bit isn't enabled by default, so
744ae5bb2a6SJohannes Berg * when we power down the device we need set the bit to allow it
745ae5bb2a6SJohannes Berg * to wake up the PCI-E bus for RF-kill interrupts.
746ae5bb2a6SJohannes Berg */
747ae5bb2a6SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL,
748ae5bb2a6SJohannes Berg CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
749ae5bb2a6SJohannes Berg }
750e705c121SKalle Valo }
751e705c121SKalle Valo
752ad1220bbSJohannes Berg void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans, bool from_irq);
753fa4de7f7SJohannes Berg
iwl_is_rfkill_set(struct iwl_trans * trans)754e705c121SKalle Valo static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
755e705c121SKalle Valo {
756fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
757fa4de7f7SJohannes Berg
758fa4de7f7SJohannes Berg lockdep_assert_held(&trans_pcie->mutex);
759fa4de7f7SJohannes Berg
760c5bf4fa1SJohannes Berg if (trans_pcie->debug_rfkill == 1)
761fa4de7f7SJohannes Berg return true;
76223aeea94SJohannes Berg
763e705c121SKalle Valo return !(iwl_read32(trans, CSR_GP_CNTRL) &
764e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
765e705c121SKalle Valo }
766e705c121SKalle Valo
__iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)767e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
768e705c121SKalle Valo u32 reg, u32 mask, u32 value)
769e705c121SKalle Valo {
770e705c121SKalle Valo u32 v;
771e705c121SKalle Valo
772e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG
773e705c121SKalle Valo WARN_ON_ONCE(value & ~mask);
774e705c121SKalle Valo #endif
775e705c121SKalle Valo
776e705c121SKalle Valo v = iwl_read32(trans, reg);
777e705c121SKalle Valo v &= ~mask;
778e705c121SKalle Valo v |= value;
779e705c121SKalle Valo iwl_write32(trans, reg, v);
780e705c121SKalle Valo }
781e705c121SKalle Valo
__iwl_trans_pcie_clear_bit(struct iwl_trans * trans,u32 reg,u32 mask)782e705c121SKalle Valo static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
783e705c121SKalle Valo u32 reg, u32 mask)
784e705c121SKalle Valo {
785e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
786e705c121SKalle Valo }
787e705c121SKalle Valo
__iwl_trans_pcie_set_bit(struct iwl_trans * trans,u32 reg,u32 mask)788e705c121SKalle Valo static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
789e705c121SKalle Valo u32 reg, u32 mask)
790e705c121SKalle Valo {
791e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
792e705c121SKalle Valo }
793e705c121SKalle Valo
iwl_pcie_dbg_on(struct iwl_trans * trans)7947a14c23dSSara Sharon static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
7957a14c23dSSara Sharon {
796a1af4c48SShahar S Matityahu return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
7977a14c23dSSara Sharon }
7987a14c23dSSara Sharon
799ad1220bbSJohannes Berg void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq);
8004290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
801e705c121SKalle Valo
802f8a1edb7SJohannes Berg #ifdef CONFIG_IWLWIFI_DEBUGFS
803cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
804f8a1edb7SJohannes Berg #else
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans)805cf5d5663SGreg Kroah-Hartman static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
806f8a1edb7SJohannes Berg #endif
807f8a1edb7SJohannes Berg
80810a54d81SLuca Coelho void iwl_pcie_rx_allocator_work(struct work_struct *data);
80910a54d81SLuca Coelho
810eda50cdeSSara Sharon /* common functions that are used by gen2 transport */
811b6fe2757SGolan Ben Ami int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
812eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans);
813eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
814eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
8159ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
816326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
817326477e4SJohannes Berg bool was_in_rfkill);
818e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
81977c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
82013a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
82113a3a390SSara Sharon struct iwl_dma_ptr *ptr, size_t size);
82213a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
823c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans);
824eda50cdeSSara Sharon
8259f358c17SGolan Ben Ami /* common functions that are used by gen3 transport */
8269f358c17SGolan Ben Ami void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
8279f358c17SGolan Ben Ami
828eda50cdeSSara Sharon /* transport gen 2 exported functions */
829eda50cdeSSara Sharon int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
830eda50cdeSSara Sharon const struct fw_img *fw, bool run_in_rfkill);
831eda50cdeSSara Sharon void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
832ca60da2eSSara Sharon int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
833ca60da2eSSara Sharon struct iwl_host_cmd *cmd);
834bab3cb92SEmmanuel Grumbach void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
835bab3cb92SEmmanuel Grumbach void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
836e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
837e5f3f215SHaim Dreyfuss bool test, bool reset);
83813f028b4SMordechay Goodstein int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
83913f028b4SMordechay Goodstein struct iwl_host_cmd *cmd);
84013f028b4SMordechay Goodstein int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
84113f028b4SMordechay Goodstein struct iwl_host_cmd *cmd);
842c0941aceSMukesh Sisodiya void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
843c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, u32 byte_cnt);
844c0941aceSMukesh Sisodiya int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
845c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, u32 byte_cnt);
846c0941aceSMukesh Sisodiya
847e705c121SKalle Valo #endif /* __iwl_trans_int_pcie_h__ */
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