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/openbmc/linux/Documentation/devicetree/bindings/power/
H A Dmti,mips-cpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Cluster Power Controller
10 Defines a location of the MIPS Cluster Power Controller registers.
13 - Paul Burton <paulburton@kernel.org>
17 const: mti,mips-cpc
22 used to map the MIPS CPC registers block.
26 - compatible
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/openbmc/linux/arch/mips/include/asm/
H A Dmips-cpc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cpc.h
17 /* The base address of the CPC registers */
21 * mips_cpc_default_phys_base - retrieve the default physical base address of
22 * the CPC
26 * implemented per-platform.
31 * mips_cpc_probe - probe for a Cluster Power Controller
34 * a CPC is successfully detected, else -errno.
41 return -ENODEV; in mips_cpc_probe()
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H A Dmips-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
105 #include <asm/mips-cm.h>
106 #include <asm/mips-cpc.h>
107 #include <asm/mips-gic.h>
110 * mips_cps_numclusters - return the number of clusters present in the system
123 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
145 * GCR_CONFIG via the redirect region, since the CPC is always in mips_cps_cluster_config()
157 * mips_cps_numcores - return the number of cores present in a cluster
174 * mips_cps_numiocu - return the number of IOCUs present in a cluster
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H A Dpm-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
13 * enter or exit states requiring CM or CPC assistance in unison.
25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
32 * cps_pm_support_state - determine whether the system supports a PM state
40 * cps_pm_enter_state - enter a PM state
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
H A Ddsemul.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
24 * mips_dsemul() - 'Emulate' an instruction from a branch delay slot
30 * Emulate or execute an arbitrary MIPS instruction within the context of
41 * do_dsemulret() - Return from a delay slot 'emulation' frame
47 * passed as the cpc parameter to mips_dsemul().
61 * dsemul_thread_cleanup() - Cleanup thread 'emulation' frame
78 * dsemul_thread_rollback() - Rollback from an 'emulation' frame
99 * dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state
103 * for delay slot 'emulation' book-keeping is freed. This is to be called
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H A Dmips-cm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
21 /* The base address of the CM L2-only sync region */
25 * __mips_cm_phys_base - retrieve the physical base address of the CM
37 * mips_cm_is64 - determine CM register width
42 * or vice-versa. This variable indicates the width of the memory accesses
46 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
51 * mips_cm_error_report - Report CM cache errors
60 * mips_cm_probe - probe for a Coherence Manager
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/openbmc/linux/arch/mips/kernel/
H A Dmips-cpc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
14 #include <asm/mips-cps.h>
28 cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc"); in mips_cpc_default_phys_base()
40 * mips_cpc_phys_base - retrieve the physical base address of the CPC
56 /* If the CPC is already enabled, leave it so */ in mips_cpc_phys_base()
66 /* Enable the CPC, mapped at the default address */ in mips_cpc_phys_base()
81 return -ENODEV; in mips_cpc_probe()
85 return -ENXIO; in mips_cpc_probe()
95 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ in mips_cpc_lock_other()
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H A Dpm-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
21 #include <asm/smp-cps.h>
25 * cps_nc_entry_fn - type of a generated non-coherent state entry function
27 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
29 * The code entering & exiting non-coherent states is generated at runtime
32 * core-specific code particularly for cache routines. If coupled_coherence
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/MIPS kernel.
6 extra-y := vmlinux.lds
8 obj-y += head.o branch.o cmpxchg.o elf.o entry.o genex.o idle.o irq.o \
14 obj-y += cpu-r3k-probe.o
16 obj-y += cpu-probe.o
26 obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
27 obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
28 obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
29 obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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H A Dmips-r2-to-r6-emul.c10 * MIPS R2 user space instruction emulator for MIPS R6
28 #include <asm/mips-r2-to-r6-emul.h>
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
101 return -SIGFPE; in mipsr6_emul()
106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
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H A Dsmp-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
18 #include <asm/mips-cps.h>
21 #include <asm/pm-cps.h>
24 #include <asm/smp-cps.h>
64 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { in cps_smp_setup()
103 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cps_smp_setup()
117 /* Detect whether the CCA is unsuited to multi-core SMP */ in cps_prepare_cpus()
122 /* The CCA is coherent, multi-core is fine */ in cps_prepare_cpus()
127 /* CCA is not coherent, multi-core is not usable */ in cps_prepare_cpus()
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H A Dmips-cm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
11 #include <asm/mips-cps.h>
20 "0x04", "cpc", "0x06", "0x07"
198 return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); in __mips_cm_phys_base()
209 * If the L2-only sync region is already enabled then leave it at it's in __mips_cm_l2sync_phys_base()
228 /* L2-only sync was introduced with CM major revision 6 */ in mips_cm_probe_l2sync()
262 return -ENODEV; in mips_cm_probe()
266 return -ENXIO; in mips_cm_probe()
275 return -ENODEV; in mips_cm_probe()
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/openbmc/qemu/hw/mips/
H A Dcps.c23 #include "hw/mips/cps.h"
24 #include "hw/mips/mips.h"
25 #include "hw/qdev-clock.h"
26 #include "hw/qdev-properties.h"
32 assert(pin_number < s->num_irq); in get_cps_irq()
33 return s->gic.irq_state[pin_number].irq; in get_cps_irq()
41 s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0); in mips_cps_init()
44 * constraints for the base address of CPC and GIC. in mips_cps_init()
46 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); in mips_cps_init()
47 sysbus_init_mmio(sbd, &s->container); in mips_cps_init()
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H A Dboston.c2 * MIPS Boston development board emulation.
25 #include "hw/char/serial-mm.h"
27 #include "hw/ide/ahci-pci.h"
29 #include "hw/loader-fit.h"
30 #include "hw/mips/bootloader.h"
31 #include "hw/mips/cps.h"
32 #include "hw/pci-host/xilinx-pcie.h"
33 #include "hw/qdev-clock.h"
34 #include "hw/qdev-properties.h"
36 #include "qemu/error-report.h"
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/openbmc/qemu/hw/misc/
H A Dmips_cpc.c29 #include "hw/qdev-properties.h"
31 static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc) in cpc_vp_run_mask() argument
33 return (1ULL << cpc->num_vp) - 1; in cpc_vp_run_mask()
38 MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr; in mips_cpu_reset_async_work() local
41 cs->halted = 0; in mips_cpu_reset_async_work()
42 cpc->vp_running |= 1ULL << cs->cpu_index; in mips_cpu_reset_async_work()
45 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run) in cpc_run_vp() argument
50 uint64_t i = 1ULL << cs->cpu_index; in cpc_run_vp()
51 if (i & vp_run & ~cpc->vp_running) { in cpc_run_vp()
58 RUN_ON_CPU_HOST_PTR(cpc)); in cpc_run_vp()
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H A Dmips_cmgcr.c6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
19 #include "hw/qdev-properties.h"
24 return s->cpc_mr != NULL; in is_cpc_connected()
29 return s->gic_mr != NULL; in is_gic_connected()
37 gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK; in update_gcr_base()
38 memory_region_set_address(&gcr->iomem, gcr->gcr_base); in update_gcr_base()
42 mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4; in update_gcr_base()
49 gcr->cpc_base = val & GCR_CPC_BASE_MSK; in update_cpc_base()
51 memory_region_set_address(gcr->cpc_mr, in update_cpc_base()
52 gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK); in update_cpc_base()
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/openbmc/qemu/include/hw/misc/
H A Dmips_cpc.h28 /* CPC blocks offsets relative to base address */
32 /* CPC register offsets relative to block offsets */
37 #define TYPE_MIPS_CPC "mips-cpc"
/openbmc/linux/arch/mips/boot/dts/img/
H A Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
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H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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/openbmc/linux/arch/mips/include/asm/mips-boards/
H A Dmalta.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
6 * Defines of the Malta board specific address-MAP, registers, etc.
13 #include <asm/mips-boards/msc01_pci.h>
16 /* Mips interrupt controller found in SOCit variations */
55 * CPC Specific definitions
71 * Malta RTC-device indirect register access.
/openbmc/qemu/include/hw/mips/
H A Dcps.h29 #include "target/mips/cpu.h"
32 #define TYPE_MIPS_CPS "mips-cps"
46 MIPSCPCState cpc; member
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Dmt7621.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "mediatek,mt7621-soc";
13 #address-cells = <1>;
14 #size-cells = <0>;
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/openbmc/linux/drivers/clocksource/
H A Dmips-gic-timer.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
4 #define pr_fmt(fmt) "mips-gic-timer: " fmt
17 #include <asm/mips-cps.h>
54 int cpu = cpumask_first(evt->cpumask); in gic_next_event()
66 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; in gic_next_event()
75 cd->event_handler(cd); in gic_compare_interrupt()
89 cd->name = "MIPS GIC"; in gic_clockevent_cpu_init()
90 cd->features = CLOCK_EVT_FEAT_ONESHOT | in gic_clockevent_cpu_init()
93 cd->rating = 350; in gic_clockevent_cpu_init()
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/openbmc/linux/arch/mips/ralink/
H A Dmt7621.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <asm/smp-ops.h>
19 #include <asm/mips-cps.h>
20 #include <asm/mach-ralink/ralink_regs.h>
21 #include <asm/mach-ralink/mt7621.h>
35 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); in pcibios_root_bridge_prepare()
38 return -EINVAL; in pcibios_root_bridge_prepare()
46 mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK; in pcibios_root_bridge_prepare()
47 WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask); in pcibios_root_bridge_prepare()
49 write_gcr_reg1_base(entry->res->start); in pcibios_root_bridge_prepare()
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/openbmc/linux/arch/mips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 config MIPS config
135 bool "Generic board-agnostic MIPS kernel"
224 Support for the Texas Instruments AR7 System-on-a-Chip
298 Build a generic DT-based kernel image that boots on select
299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
390 This enables support for DEC's MIPS based workstations. For details
391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
392 DECstation porting pages on <http://decstation.unix-ag.org/>.
429 This a family of machines based on the MIPS R4030 chipset which was
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