Lines Matching +full:mips +full:- +full:cpc

10  *      MIPS R2 user space instruction emulator for MIPS R6
28 #include <asm/mips-r2-to-r6-emul.h>
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
101 return -SIGFPE; in mipsr6_emul()
106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
107 regs->regs[MIPSInst_RS(ir)] | in mipsr6_emul()
108 regs->regs[MIPSInst_RT(ir)]; in mipsr6_emul()
115 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
116 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) << in mipsr6_emul()
124 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
125 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >> in mipsr6_emul()
133 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
134 (s32)((u32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
135 (u32)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
142 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
143 (s32)((u32)regs->regs[MIPSInst_RS(ir)] - in mipsr6_emul()
144 (u32)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
151 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
152 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) << in mipsr6_emul()
160 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
161 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >> in mipsr6_emul()
169 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
170 (u64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
171 (u64)regs->regs[MIPSInst_RT(ir)]; in mipsr6_emul()
178 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
179 (s64)((u64)regs->regs[MIPSInst_RS(ir)] - in mipsr6_emul()
180 (u64)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
193 * movf_func - Emulate a MOVF instruction
204 csr = current->thread.fpu.fcr31; in movf_func()
208 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movf_func()
216 * movt_func - Emulate a MOVT instruction
227 csr = current->thread.fpu.fcr31; in movt_func()
231 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movt_func()
239 * jr_func - Emulate a JR instruction.
257 nepc = regs->cp0_epc; in jr_func()
259 regs->cp0_epc -= 4; in jr_func()
260 epc = regs->cp0_epc; in jr_func()
268 cepc = regs->cp0_epc; in jr_func()
280 * Negative err means FPU instruction in BD-slot, in jr_func()
281 * Zero err means 'BD-slot emulation done' in jr_func()
286 regs->cp0_epc = nepc; in jr_func()
298 * movz_func - Emulate a MOVZ instruction
306 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir)) in movz_func()
307 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movz_func()
314 * movn_func - Emulate a MOVZ instruction
322 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir)) in movn_func()
323 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movn_func()
330 * mfhi_func - Emulate a MFHI instruction
339 regs->regs[MIPSInst_RD(ir)] = regs->hi; in mfhi_func()
347 * mthi_func - Emulate a MTHI instruction
355 regs->hi = regs->regs[MIPSInst_RS(ir)]; in mthi_func()
363 * mflo_func - Emulate a MFLO instruction
372 regs->regs[MIPSInst_RD(ir)] = regs->lo; in mflo_func()
380 * mtlo_func - Emulate a MTLO instruction
388 regs->lo = regs->regs[MIPSInst_RS(ir)]; in mtlo_func()
396 * mult_func - Emulate a MULT instruction
407 rt = regs->regs[MIPSInst_RT(ir)]; in mult_func()
408 rs = regs->regs[MIPSInst_RS(ir)]; in mult_func()
412 regs->lo = (s64)rs; in mult_func()
415 regs->hi = res; in mult_func()
423 * multu_func - Emulate a MULTU instruction
434 rt = regs->regs[MIPSInst_RT(ir)]; in multu_func()
435 rs = regs->regs[MIPSInst_RS(ir)]; in multu_func()
438 regs->lo = (s64)(s32)rt; in multu_func()
439 regs->hi = (s64)(s32)(res >> 32); in multu_func()
447 * div_func - Emulate a DIV instruction
457 rt = regs->regs[MIPSInst_RT(ir)]; in div_func()
458 rs = regs->regs[MIPSInst_RS(ir)]; in div_func()
460 regs->lo = (s64)(rs / rt); in div_func()
461 regs->hi = (s64)(rs % rt); in div_func()
469 * divu_func - Emulate a DIVU instruction
479 rt = regs->regs[MIPSInst_RT(ir)]; in divu_func()
480 rs = regs->regs[MIPSInst_RS(ir)]; in divu_func()
482 regs->lo = (s64)(rs / rt); in divu_func()
483 regs->hi = (s64)(rs % rt); in divu_func()
491 * dmult_func - Emulate a DMULT instruction
495 * Returns 0 on success or SIGILL for 32-bit kernels.
505 rt = regs->regs[MIPSInst_RT(ir)]; in dmult_func()
506 rs = regs->regs[MIPSInst_RS(ir)]; in dmult_func()
509 regs->lo = res; in dmult_func()
515 regs->hi = res; in dmult_func()
523 * dmultu_func - Emulate a DMULTU instruction
527 * Returns 0 on success or SIGILL for 32-bit kernels.
537 rt = regs->regs[MIPSInst_RT(ir)]; in dmultu_func()
538 rs = regs->regs[MIPSInst_RS(ir)]; in dmultu_func()
541 regs->lo = res; in dmultu_func()
547 regs->hi = res; in dmultu_func()
555 * ddiv_func - Emulate a DDIV instruction
559 * Returns 0 on success or SIGILL for 32-bit kernels.
568 rt = regs->regs[MIPSInst_RT(ir)]; in ddiv_func()
569 rs = regs->regs[MIPSInst_RS(ir)]; in ddiv_func()
571 regs->lo = rs / rt; in ddiv_func()
572 regs->hi = rs % rt; in ddiv_func()
580 * ddivu_func - Emulate a DDIVU instruction
584 * Returns 0 on success or SIGILL for 32-bit kernels.
593 rt = regs->regs[MIPSInst_RT(ir)]; in ddivu_func()
594 rs = regs->regs[MIPSInst_RS(ir)]; in ddivu_func()
596 regs->lo = rs / rt; in ddivu_func()
597 regs->hi = rs % rt; in ddivu_func()
627 * madd_func - Emulate a MADD instruction
638 rt = regs->regs[MIPSInst_RT(ir)]; in madd_func()
639 rs = regs->regs[MIPSInst_RS(ir)]; in madd_func()
641 rt = regs->hi; in madd_func()
642 rs = regs->lo; in madd_func()
646 regs->lo = (s64)rt; in madd_func()
648 regs->hi = (s64)rs; in madd_func()
656 * maddu_func - Emulate a MADDU instruction
667 rt = regs->regs[MIPSInst_RT(ir)]; in maddu_func()
668 rs = regs->regs[MIPSInst_RS(ir)]; in maddu_func()
670 rt = regs->hi; in maddu_func()
671 rs = regs->lo; in maddu_func()
675 regs->lo = (s64)(s32)rt; in maddu_func()
677 regs->hi = (s64)(s32)rs; in maddu_func()
685 * msub_func - Emulate a MSUB instruction
696 rt = regs->regs[MIPSInst_RT(ir)]; in msub_func()
697 rs = regs->regs[MIPSInst_RS(ir)]; in msub_func()
699 rt = regs->hi; in msub_func()
700 rs = regs->lo; in msub_func()
701 res = ((((s64)rt) << 32) | (u32)rs) - res; in msub_func()
704 regs->lo = (s64)rt; in msub_func()
706 regs->hi = (s64)rs; in msub_func()
714 * msubu_func - Emulate a MSUBU instruction
725 rt = regs->regs[MIPSInst_RT(ir)]; in msubu_func()
726 rs = regs->regs[MIPSInst_RS(ir)]; in msubu_func()
728 rt = regs->hi; in msubu_func()
729 rs = regs->lo; in msubu_func()
730 res = ((((s64)rt) << 32) | (u32)rs) - res; in msubu_func()
733 regs->lo = (s64)(s32)rt; in msubu_func()
735 regs->hi = (s64)(s32)rs; in msubu_func()
743 * mul_func - Emulate a MUL instruction
756 rt = regs->regs[MIPSInst_RT(ir)]; in mul_func()
757 rs = regs->regs[MIPSInst_RS(ir)]; in mul_func()
761 regs->regs[MIPSInst_RD(ir)] = (s64)rs; in mul_func()
769 * clz_func - Emulate a CLZ instruction
783 rs = regs->regs[MIPSInst_RS(ir)]; in clz_func()
785 regs->regs[MIPSInst_RD(ir)] = res; in clz_func()
793 * clo_func - Emulate a CLO instruction
808 rs = regs->regs[MIPSInst_RS(ir)]; in clo_func()
810 regs->regs[MIPSInst_RD(ir)] = res; in clo_func()
818 * dclz_func - Emulate a DCLZ instruction
835 rs = regs->regs[MIPSInst_RS(ir)]; in dclz_func()
837 regs->regs[MIPSInst_RD(ir)] = res; in dclz_func()
845 * dclo_func - Emulate a DCLO instruction
862 rs = regs->regs[MIPSInst_RS(ir)]; in dclo_func()
864 regs->regs[MIPSInst_RD(ir)] = res; in dclo_func()
891 for (p = table; p->func; p++) { in mipsr2_find_op_func()
892 if ((inst & p->mask) == p->code) { in mipsr2_find_op_func()
893 err = (p->func)(regs, inst); in mipsr2_find_op_func()
901 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction
911 unsigned long cpc, epc, nepc, r31, res, rs, rt; in mipsr2_decoder() local
917 r31 = regs->regs[31]; in mipsr2_decoder()
918 epc = regs->cp0_epc; in mipsr2_decoder()
932 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
944 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) in mipsr2_decoder()
951 if (regs->regs[rs] >= MIPSInst_UIMM(inst)) in mipsr2_decoder()
958 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) in mipsr2_decoder()
965 if (regs->regs[rs] < MIPSInst_UIMM(inst)) in mipsr2_decoder()
972 if (regs->regs[rs] == MIPSInst_SIMM(inst)) in mipsr2_decoder()
979 if (regs->regs[rs] != MIPSInst_SIMM(inst)) in mipsr2_decoder()
993 regs->regs[31] = r31; in mipsr2_decoder()
994 regs->cp0_epc = epc; in mipsr2_decoder()
1000 cpc = regs->cp0_epc; in mipsr2_decoder()
1031 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1037 err = mips_dsemul(regs, nir, epc, cpc); in mipsr2_decoder()
1050 regs->regs[31] = r31; in mipsr2_decoder()
1051 regs->cp0_epc = epc; in mipsr2_decoder()
1055 cpc = regs->cp0_epc; in mipsr2_decoder()
1080 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1086 err = mips_dsemul(regs, nir, epc, cpc); in mipsr2_decoder()
1094 regs->regs[31] = r31; in mipsr2_decoder()
1095 regs->cp0_epc = epc; in mipsr2_decoder()
1105 * is not the case, this may be an encoding of a MIPS R6 in mipsr2_decoder()
1119 regs->regs[31] = r31; in mipsr2_decoder()
1120 regs->cp0_epc = epc; in mipsr2_decoder()
1126 cpc = regs->cp0_epc; in mipsr2_decoder()
1157 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1163 err = mips_dsemul(regs, nir, epc, cpc); in mipsr2_decoder()
1175 regs->regs[31] = r31; in mipsr2_decoder()
1176 regs->cp0_epc = epc; in mipsr2_decoder()
1178 err = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0, in mipsr2_decoder()
1185 *fcr31 = res = mask_fcr31_x(current->thread.fpu.fcr31); in mipsr2_decoder()
1186 current->thread.fpu.fcr31 &= ~res; in mipsr2_decoder()
1189 * this is a tricky issue - lose_fpu() uses LL/SC atomics in mipsr2_decoder()
1193 * more often than LL-FPU-SC and I prefer loop here until in mipsr2_decoder()
1199 current->thread.cp0_baduaddr = (unsigned long)fault_addr; in mipsr2_decoder()
1206 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1207 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1209 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1221 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1226 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1231 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1272 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1279 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1280 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1282 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1313 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1318 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1323 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1346 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1353 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1354 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1356 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1368 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1373 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1378 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1423 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1424 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1426 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1456 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1461 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1466 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1498 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1499 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1501 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1513 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1518 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1523 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1528 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1533 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1538 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1543 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1606 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1617 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1618 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1620 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1670 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1675 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1680 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1685 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1690 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1695 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1700 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1725 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1736 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1737 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1739 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1751 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1756 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1761 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1766 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1771 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1776 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1781 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1854 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1855 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1857 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1907 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1912 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1917 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1922 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1927 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1932 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1937 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1967 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1969 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1974 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1986 * an exception. MIPS R2 LL/SC instructions trap with an in mipsr2_decoder()
2017 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2023 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2025 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2030 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2042 * an exception. MIPS R2 LL/SC instructions trap with an in mipsr2_decoder()
2055 res = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
2074 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2086 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2088 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2093 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2105 * an exception. MIPS R2 LL/SC instructions trap with an in mipsr2_decoder()
2135 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2147 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2149 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2154 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2166 * an exception. MIPS R2 LL/SC instructions trap with an in mipsr2_decoder()
2179 res = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
2198 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2215 regs->cp0_cause &= ~CAUSEF_BD; in mipsr2_decoder()
2216 err = get_user(inst, (u32 __user *)regs->cp0_epc); in mipsr2_decoder()
2225 regs->regs[31] = r31; in mipsr2_decoder()
2226 regs->cp0_epc = epc; in mipsr2_decoder()
2229 /* Likely a MIPS R6 compatible instruction */ in mipsr2_decoder()
2241 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n"); in mipsr2_emul_show()