1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Author: Paul Burton <paul.burton@mips.com>
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
21 #include <asm/smp-cps.h>
25  * cps_nc_entry_fn - type of a generated non-coherent state entry function
27  * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
29  * The code entering & exiting non-coherent states is generated at runtime
32  * core-specific code particularly for cache routines. If coupled_coherence
33  * is non-zero and this is the entry function for the CPS_PM_NC_WAIT state,
41  * The entry point of the generated non-coherent idle state entry/exit
42  * functions. Actually per-core rather than per-CPU.
51  * Indicates the number of coupled VPEs ready to operate in a non-coherent
52  * state. Actually per-core rather than per-CPU.
60  * Used to synchronize entry to deep idle states. Actually per-core rather
61  * than per-CPU.
125 		return -EINVAL;  in cps_pm_enter_state()
145 			return -EINVAL;  in cps_pm_enter_state()
148 		vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(&current_cpu_data)];  in cps_pm_enter_state()
149 		vpe_cfg->pc = (unsigned long)mips_cps_pm_restore;  in cps_pm_enter_state()
150 		vpe_cfg->gp = (unsigned long)current_thread_info();  in cps_pm_enter_state()
151 		vpe_cfg->sp = 0;  in cps_pm_enter_state()
158 	/* Create a non-coherent mapping of the core ready_count */  in cps_pm_enter_state()
165 	/* Ensure ready_count is zero-initialised before the assembly runs */  in cps_pm_enter_state()
172 	/* Remove the non-coherent mapping of ready_count */  in cps_pm_enter_state()
179 	 * If this VPE is the first to leave the non-coherent wait state then  in cps_pm_enter_state()
197 	unsigned cache_size = cache->ways << cache->waybit;  in cps_gen_cache_routine()
202 	if (cache->flags & MIPS_CACHE_NOT_PRESENT)  in cps_gen_cache_routine()
221 			uasm_i_addiu(pp, t0, t0, cache->linesz);  in cps_gen_cache_routine()
223 			uasm_i_cache(pp, op, i * cache->linesz, t0);  in cps_gen_cache_routine()
229 		uasm_i_addiu(pp, t0, t0, unroll_lines * cache->linesz);  in cps_gen_cache_routine()
244 	unsigned line_size = cpu_info->dcache.linesz;  in cps_gen_flush_fsb()
246 	unsigned revision = cpu_info->processor_id & PRID_REV_MASK;  in cps_gen_flush_fsb()
252 	switch (__get_cpu_type(cpu_info->cputype)) {  in cps_gen_flush_fsb()
264 		return -1;  in cps_gen_flush_fsb()
273 	 * of a prefetch, since if it is then the CPC sequencer may become  in cps_gen_flush_fsb()
299 	 * Invalidate the new D-cache entries so that the cache will need  in cps_gen_flush_fsb()
382 		 * Save CPU state. Note the non-standard calling convention  in cps_gen_entry_code()
392 	 * Load addresses of required CM & CPC registers. This is done early  in cps_gen_entry_code()
412 		 * If this is the last VPE to become ready for non-coherence  in cps_gen_entry_code()
421 			 * for non-coherence. It needs to wait until coherence  in cps_gen_entry_code()
425 			uasm_i_addiu(&p, t1, zero, -1);  in cps_gen_entry_code()
444 				/* Halt the VP via the CPC VP_STOP register */  in cps_gen_entry_code()
461 	 * This is the point of no return - this VPE will now proceed to  in cps_gen_entry_code()
504 		/* Determine the CPC command to issue */  in cps_gen_entry_code()
517 		/* Issue the CPC command */  in cps_gen_entry_code()
536 		/* Barrier to ensure write to CPC command is complete */  in cps_gen_entry_code()
563 	 * Re-enable coherence. Note that for CPS_PM_NC_WAIT all coupled VPEs  in cps_gen_entry_code()
564 	 * will run this. The first will actually re-enable coherence & the  in cps_gen_entry_code()
583 		uasm_i_addiu(&p, t2, t1, -1);  in cps_gen_entry_code()
586 		uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);  in cps_gen_entry_code()
602 		 * power-up command to the CPC in order to resume operation.  in cps_gen_entry_code()
605 		 * be the one to re-enable it. The rest will continue from here  in cps_gen_entry_code()
620 	BUG_ON((p - buf) > max_instrs);  in cps_gen_entry_code()
621 	BUG_ON((l - labels) > ARRAY_SIZE(labels));  in cps_gen_entry_code()
622 	BUG_ON((r - relocs) > ARRAY_SIZE(relocs));  in cps_gen_entry_code()
662 			return -ENOMEM;  in cps_pm_online_cpu()
680 		 * of the cores, the JTAG detect bit indicates that the CPC will  in cps_pm_power_notifier()
681 		 * instead put the cores into clock-off state. In this state  in cps_pm_power_notifier()
689 			pr_warn("JTAG probe is connected - abort suspend\n");  in cps_pm_power_notifier()
700 	/* A CM is required for all non-coherent states */  in cps_pm_init()
702 		pr_warn("pm-cps: no CM, non-coherent states unavailable\n");  in cps_pm_init()
708 	 * non-coherent core then the VPE may end up processing interrupts  in cps_pm_init()
709 	 * whilst non-coherent. That would be bad.  in cps_pm_init()
714 		pr_warn("pm-cps: non-coherent wait unavailable\n");  in cps_pm_init()
716 	/* Detect whether a CPC is present */  in cps_pm_init()
722 			pr_warn("pm-cps: CPC does not support clock gating\n");  in cps_pm_init()
724 		/* Power gating is available with CPS SMP & any CPC */  in cps_pm_init()
728 			pr_warn("pm-cps: CPS SMP not in use, power gating unavailable\n");  in cps_pm_init()
730 		pr_warn("pm-cps: no CPC, clock & power gating unavailable\n");  in cps_pm_init()
735 	return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mips/cps_pm:online",  in cps_pm_init()