Lines Matching +full:mips +full:- +full:cpc
2 * MIPS Boston development board emulation.
25 #include "hw/char/serial-mm.h"
27 #include "hw/ide/ahci-pci.h"
29 #include "hw/loader-fit.h"
30 #include "hw/mips/bootloader.h"
31 #include "hw/mips/cps.h"
32 #include "hw/pci-host/xilinx-pcie.h"
33 #include "hw/qdev-clock.h"
34 #include "hw/qdev-properties.h"
36 #include "qemu/error-report.h"
37 #include "qemu/guest-random.h"
49 #define TYPE_BOSTON "mips-boston"
158 if (event == CHR_EVENT_OPENED && !s->lcd_inited) { in boston_lcd_event()
159 qemu_chr_fe_printf(&s->lcd_display, " "); in boston_lcd_event()
160 s->lcd_inited = true; in boston_lcd_event()
172 val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56; in boston_lcd_read()
173 val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48; in boston_lcd_read()
174 val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40; in boston_lcd_read()
175 val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32; in boston_lcd_read()
178 val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24; in boston_lcd_read()
179 val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16; in boston_lcd_read()
182 val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8; in boston_lcd_read()
185 val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7]; in boston_lcd_read()
199 s->lcd_content[(addr + 7) & 0x7] = val >> 56; in boston_lcd_write()
200 s->lcd_content[(addr + 6) & 0x7] = val >> 48; in boston_lcd_write()
201 s->lcd_content[(addr + 5) & 0x7] = val >> 40; in boston_lcd_write()
202 s->lcd_content[(addr + 4) & 0x7] = val >> 32; in boston_lcd_write()
205 s->lcd_content[(addr + 3) & 0x7] = val >> 24; in boston_lcd_write()
206 s->lcd_content[(addr + 2) & 0x7] = val >> 16; in boston_lcd_write()
209 s->lcd_content[(addr + 1) & 0x7] = val >> 8; in boston_lcd_write()
212 s->lcd_content[(addr + 0) & 0x7] = val; in boston_lcd_write()
216 qemu_chr_fe_printf(&s->lcd_display, in boston_lcd_write()
217 "\r%-8.8s", s->lcd_content); in boston_lcd_write()
245 gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000; in boston_platreg_read()
257 val = s->mach->ram_size / GiB; in boston_platreg_read()
309 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); in mips_boston_instance_init()
310 clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */ in mips_boston_instance_init()
341 /* Move & enable CPC GCRs */ in type_init()
350 * a0/$4 = -2 in type_init()
356 true, 0, true, (int32_t)-2, in type_init()
365 MachineState *machine = s->mach; in boston_fdt_filter()
380 qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); in boston_fdt_filter()
382 cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0]) in boston_fdt_filter()
383 ? machine->kernel_cmdline : " "; in boston_fdt_filter()
390 ram_low_sz = MIN(256 * MiB, machine->ram_size); in boston_fdt_filter()
391 ram_high_sz = machine->ram_size - ram_low_sz; in boston_fdt_filter()
400 s->fdt_base = *load_addr; in boston_fdt_filter()
410 s->kernel_entry = *entry_addr; in boston_kernel_filter()
470 "xlnx,axi-pcie-host-1.00.a"); in fdt_create_pcie()
474 qemu_fdt_setprop_cell(fdt, name, "#address-cells", 3); in fdt_create_pcie()
475 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 2); in fdt_create_pcie()
476 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 1); in fdt_create_pcie()
478 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", gic_ph); in fdt_create_pcie()
484 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0x00, 0xff); in fdt_create_pcie()
488 intc_name = g_strdup_printf("%s/interrupt-controller", name); in fdt_create_pcie()
490 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); in fdt_create_pcie()
491 qemu_fdt_setprop_cell(fdt, intc_name, "#address-cells", 0); in fdt_create_pcie()
492 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); in fdt_create_pcie()
495 qemu_fdt_setprop_cells(fdt, name, "interrupt-map-mask", 0, 0, 0, 7); in fdt_create_pcie()
506 qemu_fdt_setprop(fdt, name, "interrupt-map", in fdt_create_pcie()
518 MachineState *ms = s->mach; in create_fdt()
522 "img,boston-platform-regs", "syscon" in create_fdt()
537 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); in create_fdt()
538 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); in create_fdt()
542 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in create_fdt()
543 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in create_fdt()
545 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { in create_fdt()
548 qemu_fdt_setprop_string(fdt, name, "compatible", "img,mips"); in create_fdt()
558 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); in create_fdt()
559 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); in create_fdt()
560 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1); in create_fdt()
575 gic_name = g_strdup_printf("/soc/interrupt-controller@%" HWADDR_PRIx, in create_fdt()
581 qemu_fdt_setprop(fdt, gic_name, "interrupt-controller", NULL, 0); in create_fdt()
582 qemu_fdt_setprop_cell(fdt, gic_name, "#interrupt-cells", 3); in create_fdt()
587 qemu_fdt_setprop_string(fdt, name, "compatible", "mti,gic-timer"); in create_fdt()
597 qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cdmm"); in create_fdt()
602 /* CPC node */ in create_fdt()
603 name = g_strdup_printf("/soc/cpc@%" HWADDR_PRIx, memmap[BOSTON_CPC].base); in create_fdt()
605 qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cpc"); in create_fdt()
611 platreg_name = g_strdup_printf("/soc/system-controller@%" HWADDR_PRIx, in create_fdt()
624 qemu_fdt_setprop_string(fdt, name, "compatible", "img,boston-clock"); in create_fdt()
625 qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 1); in create_fdt()
633 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); in create_fdt()
645 qemu_fdt_setprop_cell(fdt, name, "reg-shift", 0x2); in create_fdt()
646 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", gic_ph); in create_fdt()
653 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", stdout_name); in create_fdt()
660 qemu_fdt_setprop_string(fdt, name, "compatible", "img,boston-lcd"); in create_fdt()
686 if ((machine->ram_size % GiB) || in boston_mach_init()
687 (machine->ram_size > (2 * GiB))) { in boston_mach_init()
696 s->mach = machine; in boston_mach_init()
698 if (!cpu_type_supports_cps_smp(machine->cpu_type)) { in boston_mach_init()
703 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); in boston_mach_init()
704 object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, in boston_mach_init()
706 object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus, in boston_mach_init()
708 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", in boston_mach_init()
709 qdev_get_clock_out(dev, "cpu-refclk")); in boston_mach_init()
710 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); in boston_mach_init()
712 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); in boston_mach_init()
723 machine->ram, 0); in boston_mach_init()
727 machine->ram, 0, in boston_mach_init()
728 MIN(machine->ram_size, (256 * MiB))); in boston_mach_init()
736 get_cps_irq(&s->cps, 2)); in boston_mach_init()
743 get_cps_irq(&s->cps, 1)); in boston_mach_init()
750 get_cps_irq(&s->cps, 0)); in boston_mach_init()
754 "boston-platregs", in boston_mach_init()
759 s->uart = serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2, in boston_mach_init()
760 get_cps_irq(&s->cps, 3), 10000000, in boston_mach_init()
764 memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); in boston_mach_init()
769 qemu_chr_fe_init(&s->lcd_display, chr, NULL); in boston_mach_init()
770 qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, in boston_mach_init()
773 pdev = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, in boston_mach_init()
776 g_assert(ARRAY_SIZE(hd) == ich9->ahci.ports); in boston_mach_init()
777 ide_drive_get(hd, ich9->ahci.ports); in boston_mach_init()
778 ahci_ide_create_devs(&ich9->ahci, hd); in boston_mach_init()
780 if (machine->firmware) { in boston_mach_init()
781 fw_size = load_image_targphys(machine->firmware, in boston_mach_init()
783 if (fw_size == -1) { in boston_mach_init()
785 machine->firmware); in boston_mach_init()
788 } else if (machine->kernel_filename) { in boston_mach_init()
792 kernel_size = load_elf(machine->kernel_filename, NULL, in boston_mach_init()
804 s->kernel_entry = kernel_entry; in boston_mach_init()
805 if (machine->dtb) { in boston_mach_init()
806 dtb_file_data = load_device_tree(machine->dtb, &dt_size); in boston_mach_init()
821 fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); in boston_mach_init()
829 s->kernel_entry, s->fdt_base); in boston_mach_init()
831 error_report("Please provide either a -kernel or -bios argument"); in boston_mach_init()
838 mc->desc = "MIPS Boston"; in boston_mach_class_init()
839 mc->init = boston_mach_init; in boston_mach_class_init()
840 mc->block_default_type = IF_IDE; in boston_mach_class_init()
841 mc->default_ram_size = 1 * GiB; in boston_mach_class_init()
842 mc->default_ram_id = "boston.ddr"; in boston_mach_class_init()
843 mc->max_cpus = 16; in boston_mach_class_init()
844 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); in boston_mach_class_init()