Revision tags: v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6 |
|
#
2874c5fd |
| 27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify it under the terms of th
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 3029 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17, v4.16, v4.15, v4.13.16, v4.14 |
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#
fb615d61 |
| 25-Oct-2017 |
Paul Burton <paul.burton@mips.com> |
Update MIPS email addresses
MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those
Update MIPS email addresses
MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those who:
- Have 10 or more patches in mainline authored using an @imgtec.com email address, or any patches dated within the past year.
- Are still with Imagination but leaving as part of the MIPS business unit, as determined from an internal email address list.
- Haven't already updated their email address (ie. JamesH) or expressed a desire to be excluded (ie. Maciej).
- Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt & myself.
New addresses are of the form firstname.lastname@mips.com, and all verified against an internal email address list. An entry is added to .mailmap for each person such that get_maintainer.pl will report the new addresses rather than @imgtec.com addresses which will soon be dead.
Instances of the affected addresses throughout the tree are then mechanically replaced with the new @mips.com address.
Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@mips.com> Acked-by: Dengcheng Zhu <dengcheng.zhu@mips.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Matt Redfearn <matt.redfearn@mips.com> Acked-by: Matt Redfearn <matt.redfearn@mips.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
48c834be |
| 25-Oct-2017 |
Paul Burton <paul.burton@mips.com> |
Update MIPS email addresses
MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those
Update MIPS email addresses
MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those who:
- Have 10 or more patches in mainline authored using an @imgtec.com email address, or any patches dated within the past year.
- Are still with Imagination but leaving as part of the MIPS business unit, as determined from an internal email address list.
- Haven't already updated their email address (ie. JamesH) or expressed a desire to be excluded (ie. Maciej).
- Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt & myself.
New addresses are of the form firstname.lastname@mips.com, and all verified against an internal email address list. An entry is added to .mailmap for each person such that get_maintainer.pl will report the new addresses rather than @imgtec.com addresses which will soon be dead.
Instances of the affected addresses throughout the tree are then mechanically replaced with the new @mips.com address.
Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@mips.com> Acked-by: Dengcheng Zhu <dengcheng.zhu@mips.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Matt Redfearn <matt.redfearn@mips.com> Acked-by: Matt Redfearn <matt.redfearn@mips.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17540/ Signed-off-by: James Hogan <jhogan@kernel.org>
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Revision tags: v4.13.5, v4.13 |
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#
e83f7e02 |
| 12-Aug-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers
With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from
MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers
With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from the CM, is now also provided by the Cluster Power Controller (CPC). This includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG.
In preparation for adjusting functions such as mips_cm_numcores(), which have previously only needed to access the CM, to also access the CPC this patch modifies the way we use the various CPS headers. Rather than having users include asm/mips-cm.h or asm/mips-cpc.h individually we instead have users include asm/mips-cps.h which in turn includes asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access to both CM & CPC registers by including one header, and most importantly it makes asm/mips-cps.h an ideal location for helper functions which need to access the various components of the CPS.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17015/ Patchwork: https://patchwork.linux-mips.org/patch/17217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
23cb600e |
| 12-Aug-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPS: Add CM/CPC 3.5 register definitions
Introduce definitions & accessors for a selection of Coherence Manager (CM) & Cluster Power Controller (CPC) registers that are new with CM v3.5 & the
MIPS: CPS: Add CM/CPC 3.5 register definitions
Introduce definitions & accessors for a selection of Coherence Manager (CM) & Cluster Power Controller (CPC) registers that are new with CM v3.5 & the MIPS I6500. These are primarily registers that will be used in supporting multiple CPU clusters.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
829ca2be |
| 12-Aug-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shifts
Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts" did for asm/m
MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shifts
Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts" did for asm/mips-cm.h.
We use BIT() & GENMASK() to simplify the definition of register fields, drop the _SHF definitions since that information can be found in the _MSK ones, and then drop the _MSK suffix.
Fields definitions are moved to be next to the appropriate register definition, making it easier to link the two & keep everything ordered by register address. Comments are added including the name of each register & a brief description of its purpose which helps to understand what registers are for, link them back to hardware documentation or grep for them.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
2c981e32 |
| 12-Aug-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPC: Use common CPS accessor generation macros
Switch the MIPS Cluster Power Controller (CPC) accessor functions to be generated by the new common Coherent Processing System (CPS) macros share
MIPS: CPC: Use common CPS accessor generation macros
Switch the MIPS Cluster Power Controller (CPC) accessor functions to be generated by the new common Coherent Processing System (CPS) macros shared with the Coherence Manager (CM).
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17002/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v4.12, v4.10.17, v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7, v4.10.6, v4.10.5, v4.10.4, v4.10.3, v4.10.2, v4.10.1, v4.10, v4.9, openbmc-4.4-20161121-1, v4.4.33, v4.4.32, v4.4.31, v4.4.30, v4.4.29, v4.4.28, v4.4.27, v4.7.10, openbmc-4.4-20161021-1, v4.7.9, v4.4.26, v4.7.8, v4.4.25, v4.4.24, v4.7.7, v4.8, v4.4.23, v4.7.6, v4.7.5, v4.4.22, v4.4.21, v4.7.4, v4.7.3, v4.4.20, v4.7.2, v4.4.19, openbmc-4.4-20160819-1, v4.7.1, v4.4.18, v4.4.17, openbmc-4.4-20160804-1, v4.4.16, v4.7, openbmc-4.4-20160722-1, openbmc-20160722-1, openbmc-20160713-1, v4.4.15, v4.6.4, v4.6.3, v4.4.14, v4.6.2, v4.4.13, openbmc-20160606-1, v4.6.1, v4.4.12, openbmc-20160521-1, v4.4.11, openbmc-20160518-1, v4.6, v4.4.10, openbmc-20160511-1, openbmc-20160505-1, v4.4.9, v4.4.8, v4.4.7, openbmc-20160329-2, openbmc-20160329-1, openbmc-20160321-1, v4.4.6, v4.5, v4.4.5, v4.4.4, v4.4.3, openbmc-20160222-1, v4.4.2, openbmc-20160212-1, openbmc-20160210-1 |
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#
88036557 |
| 02-Feb-2016 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: CPC: Add start, stop and running CM3 CPC registers
Add the new CM3 registers for controlling bringing up and powering down VPs on MIPSR6 cores.
Signed-off-by: Markos Chandras <markos.chandras
MIPS: CPC: Add start, stop and running CM3 CPC registers
Add the new CM3 registers for controlling bringing up and powering down VPs on MIPSR6 cores.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12330/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: openbmc-20160202-2, openbmc-20160202-1, v4.4.1, openbmc-20160127-1, openbmc-20160120-1, v4.4, openbmc-20151217-1, openbmc-20151210-1, openbmc-20151202-1, openbmc-20151123-1, openbmc-20151118-1, openbmc-20151104-1, v4.3, openbmc-20151102-1, openbmc-20151028-1 |
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#
4ede3161 |
| 22-Sep-2015 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CM: make use of mips_cm_{lock,unlock}_other
Document that CPC core-other accesses must take place within the bounds of the CM lock, and begin using the CM lock functions where we access the GC
MIPS: CM: make use of mips_cm_{lock,unlock}_other
Document that CPC core-other accesses must take place within the bounds of the CM lock, and begin using the CM lock functions where we access the GCRs of other cores. This is required because with CM3 the CPC began using GCR_CL_OTHER instead of CPC_CL_OTHER.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-kernel@vger.kernel.org Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/11208/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v4.3-rc1, v4.2, v4.2-rc8, v4.2-rc7, v4.2-rc6, v4.2-rc5, v4.2-rc4, v4.2-rc3 |
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#
8dedde6b |
| 12-Jul-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it static
There's only one implementation of mips_cpc_phys_base(), and it's only used within the same file, so it doesn't need to be weak,
MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it static
There's only one implementation of mips_cpc_phys_base(), and it's only used within the same file, so it doesn't need to be weak, and it doesn't need an extern declaration.
Remove the extern mips_cpc_phys_base() declaration and make it static.
[ralf@linux-mips.org: Fixed conflict.]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: linux-mips@linux-mips.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10681/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v4.2-rc2, v4.2-rc1, v4.1, v4.1-rc8, v4.1-rc7, v4.1-rc6, v4.1-rc5, v4.1-rc4, v4.1-rc3, v4.1-rc2, v4.1-rc1, v4.0, v4.0-rc7, v4.0-rc6, v4.0-rc5, v4.0-rc4, v4.0-rc3, v4.0-rc2, v4.0-rc1, v3.19, v3.19-rc7, v3.19-rc6, v3.19-rc5, v3.19-rc4, v3.19-rc3, v3.19-rc2, v3.19-rc1, v3.18, v3.18-rc7, v3.18-rc6 |
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#
15d45cce |
| 21-Nov-2014 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Replace use of phys_t with phys_addr_t.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v3.18-rc5, v3.18-rc4, v3.18-rc3, v3.18-rc2, v3.18-rc1, v3.17, v3.17-rc7, v3.17-rc6, v3.17-rc5, v3.17-rc4, v3.17-rc3, v3.17-rc2, v3.17-rc1, v3.16, v3.16-rc7, v3.16-rc6, v3.16-rc5, v3.16-rc4, v3.16-rc3, v3.16-rc2, v3.16-rc1, v3.15, v3.15-rc8, v3.15-rc7, v3.15-rc6, v3.15-rc5, v3.15-rc4, v3.15-rc3, v3.15-rc2, v3.15-rc1, v3.14, v3.14-rc8, v3.14-rc7, v3.14-rc6, v3.14-rc5, v3.14-rc4, v3.14-rc3 |
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#
76ae6584 |
| 14-Feb-2014 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPC: provide locking functions
This patch provides functions to lock & unlock access to the "core-other" register region of the CPC. Without performing appropriate locking it is possible for c
MIPS: CPC: provide locking functions
This patch provides functions to lock & unlock access to the "core-other" register region of the CPC. Without performing appropriate locking it is possible for code using this region to be preempted or to race with code on another VPE within the same core, with one changing the core which the "core-other" region is acting upon at an inopportune time for the other.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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#
2ba60250 |
| 14-Feb-2014 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPC: provide functions to retrieve register addresses
This patch introduces addr_ functions in addition to the existing read_ & write_ functions. The new functions simply return the address of
MIPS: CPC: provide functions to retrieve register addresses
This patch introduces addr_ functions in addition to the existing read_ & write_ functions. The new functions simply return the address of the appropriate CPC register rather than performing a memory access. This will be used in a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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#
9a1724c7 |
| 24-Mar-2014 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPC: Use __raw_ memory access functions
The CPC registers use native endianness, so using plain readl & writel will produce incorrect results on big endian systems.
Reported-by: Jeffrey Deans
MIPS: CPC: Use __raw_ memory access functions
The CPC registers use native endianness, so using plain readl & writel will produce incorrect results on big endian systems.
Reported-by: Jeffrey Deans <jeffrey.deans@imgtec.com> Reported-by: Keng Koh <keng.koh@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6657/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v3.14-rc2, v3.14-rc1, v3.13 |
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#
9c38cf44 |
| 15-Jan-2014 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Add CPC probe, access functions
This patch introduces code to probe for a MIPS Cluster Power Controller & accessor functions to allow for easy register access. This support code will be used b
MIPS: Add CPC probe, access functions
This patch introduces code to probe for a MIPS Cluster Power Controller & accessor functions to allow for easy register access. This support code will be used by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6361/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6 |
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#
2874c5fd |
| 27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it u
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17, v4.16, v4.15, v4.13.16, v4.14 |
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#
fb615d61 |
| 25-Oct-2017 |
Paul Burton <paul.burton@mips.com> |
Update MIPS email addresses MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the add
Update MIPS email addresses MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those who: - Have 10 or more patches in mainline authored using an @imgtec.com email address, or any patches dated within the past year. - Are still with Imagination but leaving as part of the MIPS business unit, as determined from an internal email address list. - Haven't already updated their email address (ie. JamesH) or expressed a desire to be excluded (ie. Maciej). - Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt & myself. New addresses are of the form firstname.lastname@mips.com, and all verified against an internal email address list. An entry is added to .mailmap for each person such that get_maintainer.pl will report the new addresses rather than @imgtec.com addresses which will soon be dead. Instances of the affected addresses throughout the tree are then mechanically replaced with the new @mips.com address. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@mips.com> Acked-by: Dengcheng Zhu <dengcheng.zhu@mips.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Matt Redfearn <matt.redfearn@mips.com> Acked-by: Matt Redfearn <matt.redfearn@mips.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Revision tags: v4.13.5, v4.13 |
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#
e83f7e02 |
| 12-Aug-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & a
MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from the CM, is now also provided by the Cluster Power Controller (CPC). This includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG. In preparation for adjusting functions such as mips_cm_numcores(), which have previously only needed to access the CM, to also access the CPC this patch modifies the way we use the various CPS headers. Rather than having users include asm/mips-cm.h or asm/mips-cpc.h individually we instead have users include asm/mips-cps.h which in turn includes asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access to both CM & CPC registers by including one header, and most importantly it makes asm/mips-cps.h an ideal location for helper functions which need to access the various components of the CPS. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17015/ Patchwork: https://patchwork.linux-mips.org/patch/17217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
23cb600e |
| 12-Aug-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPS: Add CM/CPC 3.5 register definitions Introduce definitions & accessors for a selection of Coherence Manager (CM) & Cluster Power Controller (CPC) registers that are new with CM
MIPS: CPS: Add CM/CPC 3.5 register definitions Introduce definitions & accessors for a selection of Coherence Manager (CM) & Cluster Power Controller (CPC) registers that are new with CM v3.5 & the MIPS I6500. These are primarily registers that will be used in supporting multiple CPU clusters. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
829ca2be |
| 12-Aug-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shifts Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts" d
MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shifts Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts" did for asm/mips-cm.h. We use BIT() & GENMASK() to simplify the definition of register fields, drop the _SHF definitions since that information can be found in the _MSK ones, and then drop the _MSK suffix. Fields definitions are moved to be next to the appropriate register definition, making it easier to link the two & keep everything ordered by register address. Comments are added including the name of each register & a brief description of its purpose which helps to understand what registers are for, link them back to hardware documentation or grep for them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
2c981e32 |
| 12-Aug-2017 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CPC: Use common CPS accessor generation macros Switch the MIPS Cluster Power Controller (CPC) accessor functions to be generated by the new common Coherent Processing System (CPS)
MIPS: CPC: Use common CPS accessor generation macros Switch the MIPS Cluster Power Controller (CPC) accessor functions to be generated by the new common Coherent Processing System (CPS) macros shared with the Coherence Manager (CM). Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17002/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v4.12, v4.10.17, v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7, v4.10.6, v4.10.5, v4.10.4, v4.10.3, v4.10.2, v4.10.1, v4.10, v4.9, openbmc-4.4-20161121-1, v4.4.33, v4.4.32, v4.4.31, v4.4.30, v4.4.29, v4.4.28, v4.4.27, v4.7.10, openbmc-4.4-20161021-1, v4.7.9, v4.4.26, v4.7.8, v4.4.25, v4.4.24, v4.7.7, v4.8, v4.4.23, v4.7.6, v4.7.5, v4.4.22, v4.4.21, v4.7.4, v4.7.3, v4.4.20, v4.7.2, v4.4.19, openbmc-4.4-20160819-1, v4.7.1, v4.4.18, v4.4.17, openbmc-4.4-20160804-1, v4.4.16, v4.7, openbmc-4.4-20160722-1, openbmc-20160722-1, openbmc-20160713-1, v4.4.15, v4.6.4, v4.6.3, v4.4.14, v4.6.2, v4.4.13, openbmc-20160606-1, v4.6.1, v4.4.12, openbmc-20160521-1, v4.4.11, openbmc-20160518-1, v4.6, v4.4.10, openbmc-20160511-1, openbmc-20160505-1, v4.4.9, v4.4.8, v4.4.7, openbmc-20160329-2, openbmc-20160329-1, openbmc-20160321-1, v4.4.6, v4.5, v4.4.5, v4.4.4, v4.4.3, openbmc-20160222-1, v4.4.2, openbmc-20160212-1, openbmc-20160210-1 |
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#
88036557 |
| 02-Feb-2016 |
Markos Chandras <markos.chandras@imgtec.com> |
MIPS: CPC: Add start, stop and running CM3 CPC registers Add the new CM3 registers for controlling bringing up and powering down VPs on MIPSR6 cores. Signed-off-by: Markos Chand
MIPS: CPC: Add start, stop and running CM3 CPC registers Add the new CM3 registers for controlling bringing up and powering down VPs on MIPSR6 cores. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12330/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: openbmc-20160202-2, openbmc-20160202-1, v4.4.1, openbmc-20160127-1, openbmc-20160120-1, v4.4, openbmc-20151217-1, openbmc-20151210-1, openbmc-20151202-1, openbmc-20151123-1, openbmc-20151118-1, openbmc-20151104-1, v4.3, openbmc-20151102-1, openbmc-20151028-1 |
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#
4ede3161 |
| 22-Sep-2015 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: CM: make use of mips_cm_{lock,unlock}_other Document that CPC core-other accesses must take place within the bounds of the CM lock, and begin using the CM lock functions where we a
MIPS: CM: make use of mips_cm_{lock,unlock}_other Document that CPC core-other accesses must take place within the bounds of the CM lock, and begin using the CM lock functions where we access the GCRs of other cores. This is required because with CM3 the CPC began using GCR_CL_OTHER instead of CPC_CL_OTHER. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-kernel@vger.kernel.org Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/11208/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v4.3-rc1, v4.2, v4.2-rc8, v4.2-rc7, v4.2-rc6, v4.2-rc5, v4.2-rc4, v4.2-rc3 |
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#
8dedde6b |
| 12-Jul-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it static There's only one implementation of mips_cpc_phys_base(), and it's only used within the same file, so it doesn't need
MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it static There's only one implementation of mips_cpc_phys_base(), and it's only used within the same file, so it doesn't need to be weak, and it doesn't need an extern declaration. Remove the extern mips_cpc_phys_base() declaration and make it static. [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: linux-mips@linux-mips.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10681/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Revision tags: v4.2-rc2, v4.2-rc1, v4.1, v4.1-rc8, v4.1-rc7, v4.1-rc6, v4.1-rc5, v4.1-rc4, v4.1-rc3, v4.1-rc2, v4.1-rc1, v4.0, v4.0-rc7, v4.0-rc6, v4.0-rc5, v4.0-rc4, v4.0-rc3, v4.0-rc2, v4.0-rc1, v3.19, v3.19-rc7, v3.19-rc6, v3.19-rc5, v3.19-rc4, v3.19-rc3, v3.19-rc2, v3.19-rc1, v3.18, v3.18-rc7, v3.18-rc6 |
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#
15d45cce |
| 21-Nov-2014 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Replace use of phys_t with phys_addr_t. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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