Home
last modified time | relevance | path

Searched +full:max +full:- +full:clk +full:- +full:rate +full:- +full:hz (Results 1 – 25 of 220) sorted by relevance

123456789

/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
[all …]
/openbmc/linux/include/linux/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
25 * to indicate that the rate change will proceed. Drivers must
27 * rate change. Callbacks may either return NOTIFY_DONE, NOTIFY_OK,
30 * ABORT_RATE_CHANGE: called if the rate change failed for some reason
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk-hsdk-cgu.c13 #include <clk-uclass.h>
21 * ------------------
23 * ------------------
25 * | -----------
26 * |-->| ARC PLL |
27 * | -----------
29 * | |-->|CGU_ARC_IDIV|----------->
30 * | |-->|CREG_CORE_IF_DIV|------->
32 * | --------------
33 * |-->| SYSTEM PLL |
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dsh-cpufreq.c4 * Copyright (C) 2002 - 2012 Paul Mundt
7 * Clock framework bits from arch/avr32/mach-at32ap/cpufreq.c
9 * Copyright (C) 2004-2007 Atmel Corporation
26 #include <linux/clk.h>
30 static DEFINE_PER_CPU(struct clk, sh_cpuclk);
45 struct cpufreq_policy *policy = target->policy; in __sh_cpufreq_target()
46 int cpu = policy->cpu; in __sh_cpufreq_target()
47 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in __sh_cpufreq_target()
53 return -ENODEV; in __sh_cpufreq_target()
57 /* Convert target_freq from kHz to Hz */ in __sh_cpufreq_target()
[all …]
H A Dimx6q-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
11 #include <linux/nvmem-consumer.h>
68 old_freq = clk_get_rate(clks[ARM].clk) / 1000; in imx6q_set_target()
81 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", in imx6q_set_target()
111 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change in imx6q_set_target()
114 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it in imx6q_set_target()
115 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it in imx6q_set_target()
116 * - Disable pll2_pfd2_396m_clk in imx6q_set_target()
127 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); in imx6q_set_target()
[all …]
H A Darmada-8k-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/clk.h>
25 { .compatible = "marvell,ap806-cpu-clock" },
26 { .compatible = "marvell,ap807-cpu-clock" },
32 * Setup the opps list with the divider for the max frequency, that
45 static void __init armada_8k_get_sharing_cpus(struct clk *cur_clk, in armada_8k_get_sharing_cpus()
52 struct clk *clk; in armada_8k_get_sharing_cpus() local
60 clk = clk_get(cpu_dev, 0); in armada_8k_get_sharing_cpus()
61 if (IS_ERR(clk)) { in armada_8k_get_sharing_cpus()
64 if (clk_is_match(clk, cur_clk)) in armada_8k_get_sharing_cpus()
[all …]
/openbmc/linux/drivers/clocksource/
H A Dnomadik-mtu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
16 #include <linux/clk.h>
33 /* per-timer registers take 0..3 as argument */
41 #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
66 static u32 nmdk_cycle; /* write-once */
79 return -readl(mtu_base + MTU_VAL(0)); in nomadik_read_sched_clock()
87 /* Clockevent device: use one-shot mode */
103 /* Timer: configure load and background-load, and fire it up */ in nmdk_clkevt_reset()
145 /* ClockSource: configure load and background-load, and fire it up */ in nmdk_clksrc_reset()
[all …]
H A Dasm9260_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
10 #include <linux/clk.h>
19 #define DRIVER_NAME "asm9260-timer"
23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
48 * 1 - Timer Counter and Prescale Counter are enabled for counting
49 * 0 - counters are disabled */
[all …]
H A Dtimer-vf-pit.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
8 #include <linux/clk.h>
56 static int __init pit_clocksource_init(unsigned long rate) in pit_clocksource_init() argument
58 /* set the max load value and start the clock source counter */ in pit_clocksource_init()
63 sched_clock_register(pit_read_sched_clock, 32, rate); in pit_clocksource_init()
64 return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, in pit_clocksource_init()
79 __raw_writel(delta - 1, clkevt_base + PITLDVAL); in pit_set_next_event()
112 evt->event_handler(evt); in pit_timer_interrupt()
126 static int __init pit_clockevent_init(unsigned long rate, int irq) in pit_clockevent_init() argument
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3128-cru.h>
29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dstm32f7_i2c.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <clk.h>
130 * struct stm32_i2c_spec - private i2c specification timing
131 * @rate: I2C bus speed (Hz)
132 * @rate_min: 80% of I2C bus speed (Hz)
133 * @rate_max: 120% of I2C bus speed (Hz)
134 * @fall_max: Max fall time of both SDA and SCL signals (ns)
135 * @rise_max: Max rise time of both SDA and SCL signals (ns)
137 * @vddat_max: Max data valid time (ns)
144 u32 rate; member
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/imu/
H A Dadi,adis16480.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - adi,adis16375
16 - adi,adis16480
17 - adi,adis16485
18 - adi,adis16488
19 - adi,adis16490
20 - adi,adis16495-1
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2012
29 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
30 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
36 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
38 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
42 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
43 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
57 &ccm->apb1_clk_div_cfg); in clock_init_uart()
[all …]
/openbmc/linux/include/sound/sof/
H A Ddai-intel.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
58 /* DMIC max. four controllers for eight microphone channels */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
67 uint32_t mclk_rate; /* mclk frequency in Hz */
68 uint32_t fsync_rate; /* fsync frequency in Hz */
69 uint32_t bclk_rate; /* bclk frequency in Hz */
93 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
97 uint32_t rate; member
101 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
105 uint32_t rate; member
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
104 * struct sdhci_s3c - S3C SDHCI instance
114 * @no_divider: No or non-standard internal clock divider.
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
132 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
[all …]
/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8195.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/nvmem-consumer.h>
16 #include "phy-mtk-io.h"
17 #include "phy-mtk-hdmi.h"
18 #include "phy-mtk-hdmi-mt8195.h"
23 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN); in mtk_hdmi_ana_fifo_en()
29 void __iomem *regs = hdmi_phy->regs; in mtk_phy_tmds_clk_ratio()
33 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G, in mtk_phy_tmds_clk_ratio()
45 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_sel_src()
57 void __iomem *regs = hdmi_phy->regs; in mtk_hdmi_pll_perf()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-bcm63xx-hsspi.c4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
13 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
24 #include <linux/mtd/spi-nor.h>
124 if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO) \
125 dev_dbg(&bs->pdev->dev, fmt, ##__VA_ARGS__); \
126 else if (bs->xfer_mode == HSSPI_XFER_MODE_PREPEND) \
127 dev_err(&bs->pdev->dev, fmt, ##__VA_ARGS__); \
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Dlpc32xx_ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * LPC32xx built-in touchscreen driver
12 #include <linux/clk.h>
43 #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
44 #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
57 #define MOD_NAME "ts-lpc32xx"
60 __raw_readl((dev)->tsc_base + (reg))
62 __raw_writel((val), (dev)->tsc_base + (reg))
68 struct clk *clk; member
83 struct input_dev *input = tsc->dev; in lpc32xx_ts_interrupt()
[all …]
/openbmc/linux/drivers/interconnect/qcom/
H A Dicc-rpm.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <linux/soc/qcom/smd-rpm.h>
11 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
12 #include <linux/clk.h>
13 #include <linux/interconnect-provider.h>
29 * struct rpm_clk_resource - RPM bus clock resource
41 * struct qcom_icc_provider - Qualcomm specific interconnect provider
47 * @bus_clk_rate: bus clock rate in Hz
49 * @bus_clk: a pointer to a HLOS-owned bus clock
62 struct clk *bus_clk;
[all …]
/openbmc/linux/drivers/media/rc/img-ir/
H A Dimg-ir-hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2014 Imagination Technologies Ltd.
7 * This ties into the input subsystem using the RC-core. Protocol support is
14 #include <linux/clk.h>
18 #include <media/rc-core.h>
19 #include "img-ir.h"
63 /* functions for preprocessing timings, ensuring max is set */
68 if (range->max < range->min) in img_ir_timing_preprocess()
69 range->max = range->min; in img_ir_timing_preprocess()
72 range->min = (range->min*unit)/1000; in img_ir_timing_preprocess()
[all …]
/openbmc/linux/drivers/gpu/drm/pl111/
H A Dpl111_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
7 * Copyright (c) 2006-2008 Intel Corporation
12 #include <linux/clk.h>
14 #include <linux/dma-buf.h>
15 #include <linux/media-bus-format.h>
33 irq_stat = readl(priv->regs + CLCD_PL111_MIS); in pl111_irq()
39 drm_crtc_handle_vblank(&priv->pipe.crtc); in pl111_irq()
45 writel(irq_stat, priv->regs + CLCD_PL111_ICR); in pl111_irq()
54 struct drm_device *drm = pipe->crtc.dev; in pl111_mode_valid()
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
17 #include <linux/clk.h>
18 #include "clk.h"
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
57 if (rate == rate_table[i].rate) in rockchip_get_pll_settings()
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dda7219.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7219.c - DA7219 ALSA SoC Codec Driver
11 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
26 #include <sound/soc-dapm.h>
33 #include "da7219-aad.h"
41 static const DECLARE_TLV_DB_SCALE(da7219_mic_gain_tlv, -600, 600, 0);
42 static const DECLARE_TLV_DB_SCALE(da7219_mixin_gain_tlv, -450, 150, 0);
43 static const DECLARE_TLV_DB_SCALE(da7219_adc_dig_gain_tlv, -8325, 75, 0);
44 static const DECLARE_TLV_DB_SCALE(da7219_alc_threshold_tlv, -9450, 150, 0);
[all …]
/openbmc/linux/drivers/memory/tegra/
H A Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk/tegra.h>
14 #include <linux/interconnect-provider.h>
181 unsigned long rate; member
202 struct clk *clk; member
217 * a min/max clock rate, these rates are contained in this array.
221 /* protect shared rate-change code path */
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]

123456789