1 // SPDX-License-Identifier: GPL-2.0+
5  * (C) Copyright 2007-2012
29 	       &ccm->cpu_ahb_apb0_cfg);  in clock_init_safe()
30 	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);  in clock_init_safe()
36 	       &ccm->cpu_ahb_apb0_cfg);  in clock_init_safe()
38 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);  in clock_init_safe()
40 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);  in clock_init_safe()
42 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);  in clock_init_safe()
43 	setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);  in clock_init_safe()
57 	       &ccm->apb1_clk_div_cfg);  in clock_init_uart()
60 	setbits_le32(&ccm->apb1_gate,  in clock_init_uart()
61 		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1));  in clock_init_uart()
71 		setbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
74 		clrbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
118 void clock_set_pll1(unsigned int hz)  in clock_set_pll1()  argument
126 	while (pll1_para[i].freq > hz)  in clock_set_pll1()
129 	hz = pll1_para[i].freq;  in clock_set_pll1()
130 	if (! hz)  in clock_set_pll1()
131 		hz = 384000000;  in clock_set_pll1()
134 	axi = DIV_ROUND_UP(hz, 432000000);	/* Max 450MHz */  in clock_set_pll1()
135 	ahb = DIV_ROUND_UP(hz/axi, 204000000);	/* Max 250MHz */  in clock_set_pll1()
136 	apb0 = 2;				/* Max 150MHz */  in clock_set_pll1()
138 	printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);  in clock_set_pll1()
141 	axi = axi - 1;  in clock_set_pll1()
151 	apb0 = apb0 - 1;  in clock_set_pll1()
158 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
166 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
169 	writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);  in clock_set_pll1()
177 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
182 void clock_set_pll3(unsigned int clk)  in clock_set_pll3()  argument
187 	if (clk == 0) {  in clock_set_pll3()
188 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);  in clock_set_pll3()
192 	/* PLL3 rate = 3000000 * m */  in clock_set_pll3()
194 	       CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);  in clock_set_pll3()
201 	uint32_t rval = readl(&ccm->pll3_cfg);  in clock_get_pll3()
210 	uint32_t rval = readl(&ccm->pll5_cfg);  in clock_get_pll5p()
221 	uint32_t rval = readl(&ccm->pll6_cfg);  in clock_get_pll6()
227 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)  in clock_set_de_mod_clock()  argument
232 	while ((pll / div) > hz)  in clock_set_de_mod_clock()