1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/cpu.h>
8 #include <linux/cpufreq.h>
9 #include <linux/err.h>
10 #include <linux/module.h>
11 #include <linux/nvmem-consumer.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_opp.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
17 
18 #define PU_SOC_VOLTAGE_NORMAL	1250000
19 #define PU_SOC_VOLTAGE_HIGH	1275000
20 #define FREQ_1P2_GHZ		1200000000
21 
22 static struct regulator *arm_reg;
23 static struct regulator *pu_reg;
24 static struct regulator *soc_reg;
25 
26 enum IMX6_CPUFREQ_CLKS {
27 	ARM,
28 	PLL1_SYS,
29 	STEP,
30 	PLL1_SW,
31 	PLL2_PFD2_396M,
32 	/* MX6UL requires two more clks */
33 	PLL2_BUS,
34 	SECONDARY_SEL,
35 };
36 #define IMX6Q_CPUFREQ_CLK_NUM		5
37 #define IMX6UL_CPUFREQ_CLK_NUM		7
38 
39 static int num_clks;
40 static struct clk_bulk_data clks[] = {
41 	{ .id = "arm" },
42 	{ .id = "pll1_sys" },
43 	{ .id = "step" },
44 	{ .id = "pll1_sw" },
45 	{ .id = "pll2_pfd2_396m" },
46 	{ .id = "pll2_bus" },
47 	{ .id = "secondary_sel" },
48 };
49 
50 static struct device *cpu_dev;
51 static struct cpufreq_frequency_table *freq_table;
52 static unsigned int max_freq;
53 static unsigned int transition_latency;
54 
55 static u32 *imx6_soc_volt;
56 static u32 soc_opp_count;
57 
imx6q_set_target(struct cpufreq_policy * policy,unsigned int index)58 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
59 {
60 	struct dev_pm_opp *opp;
61 	unsigned long freq_hz, volt, volt_old;
62 	unsigned int old_freq, new_freq;
63 	bool pll1_sys_temp_enabled = false;
64 	int ret;
65 
66 	new_freq = freq_table[index].frequency;
67 	freq_hz = new_freq * 1000;
68 	old_freq = clk_get_rate(clks[ARM].clk) / 1000;
69 
70 	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
71 	if (IS_ERR(opp)) {
72 		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
73 		return PTR_ERR(opp);
74 	}
75 
76 	volt = dev_pm_opp_get_voltage(opp);
77 	dev_pm_opp_put(opp);
78 
79 	volt_old = regulator_get_voltage(arm_reg);
80 
81 	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
82 		old_freq / 1000, volt_old / 1000,
83 		new_freq / 1000, volt / 1000);
84 
85 	/* scaling up?  scale voltage before frequency */
86 	if (new_freq > old_freq) {
87 		if (!IS_ERR(pu_reg)) {
88 			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
89 			if (ret) {
90 				dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
91 				return ret;
92 			}
93 		}
94 		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
95 		if (ret) {
96 			dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
97 			return ret;
98 		}
99 		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
100 		if (ret) {
101 			dev_err(cpu_dev,
102 				"failed to scale vddarm up: %d\n", ret);
103 			return ret;
104 		}
105 	}
106 
107 	/*
108 	 * The setpoints are selected per PLL/PDF frequencies, so we need to
109 	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
110 	 * PLL1 is as below.
111 	 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
112 	 * flow is slightly different from other i.MX6 OSC.
113 	 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
114 	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
115 	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
116 	 *  - Disable pll2_pfd2_396m_clk
117 	 */
118 	if (of_machine_is_compatible("fsl,imx6ul") ||
119 	    of_machine_is_compatible("fsl,imx6ull")) {
120 		/*
121 		 * When changing pll1_sw_clk's parent to pll1_sys_clk,
122 		 * CPU may run at higher than 528MHz, this will lead to
123 		 * the system unstable if the voltage is lower than the
124 		 * voltage of 528MHz, so lower the CPU frequency to one
125 		 * half before changing CPU frequency.
126 		 */
127 		clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
128 		clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
129 		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
130 			clk_set_parent(clks[SECONDARY_SEL].clk,
131 				       clks[PLL2_BUS].clk);
132 		else
133 			clk_set_parent(clks[SECONDARY_SEL].clk,
134 				       clks[PLL2_PFD2_396M].clk);
135 		clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
136 		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
137 		if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
138 			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
139 			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
140 		}
141 	} else {
142 		clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
143 		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
144 		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
145 			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
146 			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
147 		} else {
148 			/* pll1_sys needs to be enabled for divider rate change to work. */
149 			pll1_sys_temp_enabled = true;
150 			clk_prepare_enable(clks[PLL1_SYS].clk);
151 		}
152 	}
153 
154 	/* Ensure the arm clock divider is what we expect */
155 	ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
156 	if (ret) {
157 		int ret1;
158 
159 		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
160 		ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
161 		if (ret1)
162 			dev_warn(cpu_dev,
163 				 "failed to restore vddarm voltage: %d\n", ret1);
164 		return ret;
165 	}
166 
167 	/* PLL1 is only needed until after ARM-PODF is set. */
168 	if (pll1_sys_temp_enabled)
169 		clk_disable_unprepare(clks[PLL1_SYS].clk);
170 
171 	/* scaling down?  scale voltage after frequency */
172 	if (new_freq < old_freq) {
173 		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
174 		if (ret)
175 			dev_warn(cpu_dev,
176 				 "failed to scale vddarm down: %d\n", ret);
177 		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
178 		if (ret)
179 			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
180 		if (!IS_ERR(pu_reg)) {
181 			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
182 			if (ret)
183 				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
184 		}
185 	}
186 
187 	return 0;
188 }
189 
imx6q_cpufreq_init(struct cpufreq_policy * policy)190 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
191 {
192 	policy->clk = clks[ARM].clk;
193 	cpufreq_generic_init(policy, freq_table, transition_latency);
194 	policy->suspend_freq = max_freq;
195 
196 	return 0;
197 }
198 
199 static struct cpufreq_driver imx6q_cpufreq_driver = {
200 	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
201 		 CPUFREQ_IS_COOLING_DEV,
202 	.verify = cpufreq_generic_frequency_table_verify,
203 	.target_index = imx6q_set_target,
204 	.get = cpufreq_generic_get,
205 	.init = imx6q_cpufreq_init,
206 	.register_em = cpufreq_register_em_with_opp,
207 	.name = "imx6q-cpufreq",
208 	.attr = cpufreq_generic_attr,
209 	.suspend = cpufreq_generic_suspend,
210 };
211 
imx6x_disable_freq_in_opp(struct device * dev,unsigned long freq)212 static void imx6x_disable_freq_in_opp(struct device *dev, unsigned long freq)
213 {
214 	int ret = dev_pm_opp_disable(dev, freq);
215 
216 	if (ret < 0 && ret != -ENODEV)
217 		dev_warn(dev, "failed to disable %ldMHz OPP\n", freq / 1000000);
218 }
219 
220 #define OCOTP_CFG3			0x440
221 #define OCOTP_CFG3_SPEED_SHIFT		16
222 #define OCOTP_CFG3_SPEED_1P2GHZ		0x3
223 #define OCOTP_CFG3_SPEED_996MHZ		0x2
224 #define OCOTP_CFG3_SPEED_852MHZ		0x1
225 
imx6q_opp_check_speed_grading(struct device * dev)226 static int imx6q_opp_check_speed_grading(struct device *dev)
227 {
228 	struct device_node *np;
229 	void __iomem *base;
230 	u32 val;
231 	int ret;
232 
233 	if (of_property_present(dev->of_node, "nvmem-cells")) {
234 		ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
235 		if (ret)
236 			return ret;
237 	} else {
238 		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
239 		if (!np)
240 			return -ENOENT;
241 
242 		base = of_iomap(np, 0);
243 		of_node_put(np);
244 		if (!base) {
245 			dev_err(dev, "failed to map ocotp\n");
246 			return -EFAULT;
247 		}
248 
249 		/*
250 		 * SPEED_GRADING[1:0] defines the max speed of ARM:
251 		 * 2b'11: 1200000000Hz;
252 		 * 2b'10: 996000000Hz;
253 		 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
254 		 * 2b'00: 792000000Hz;
255 		 * We need to set the max speed of ARM according to fuse map.
256 		 */
257 		val = readl_relaxed(base + OCOTP_CFG3);
258 		iounmap(base);
259 	}
260 
261 	val >>= OCOTP_CFG3_SPEED_SHIFT;
262 	val &= 0x3;
263 
264 	if (val < OCOTP_CFG3_SPEED_996MHZ)
265 		imx6x_disable_freq_in_opp(dev, 996000000);
266 
267 	if (of_machine_is_compatible("fsl,imx6q") ||
268 	    of_machine_is_compatible("fsl,imx6qp")) {
269 		if (val != OCOTP_CFG3_SPEED_852MHZ)
270 			imx6x_disable_freq_in_opp(dev, 852000000);
271 
272 		if (val != OCOTP_CFG3_SPEED_1P2GHZ)
273 			imx6x_disable_freq_in_opp(dev, 1200000000);
274 	}
275 
276 	return 0;
277 }
278 
279 #define OCOTP_CFG3_6UL_SPEED_696MHZ	0x2
280 #define OCOTP_CFG3_6ULL_SPEED_792MHZ	0x2
281 #define OCOTP_CFG3_6ULL_SPEED_900MHZ	0x3
282 
imx6ul_opp_check_speed_grading(struct device * dev)283 static int imx6ul_opp_check_speed_grading(struct device *dev)
284 {
285 	u32 val;
286 	int ret = 0;
287 
288 	if (of_property_present(dev->of_node, "nvmem-cells")) {
289 		ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
290 		if (ret)
291 			return ret;
292 	} else {
293 		struct device_node *np;
294 		void __iomem *base;
295 
296 		np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
297 		if (!np)
298 			np = of_find_compatible_node(NULL, NULL,
299 						     "fsl,imx6ull-ocotp");
300 		if (!np)
301 			return -ENOENT;
302 
303 		base = of_iomap(np, 0);
304 		of_node_put(np);
305 		if (!base) {
306 			dev_err(dev, "failed to map ocotp\n");
307 			return -EFAULT;
308 		}
309 
310 		val = readl_relaxed(base + OCOTP_CFG3);
311 		iounmap(base);
312 	}
313 
314 	/*
315 	 * Speed GRADING[1:0] defines the max speed of ARM:
316 	 * 2b'00: Reserved;
317 	 * 2b'01: 528000000Hz;
318 	 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
319 	 * 2b'11: 900000000Hz on i.MX6ULL only;
320 	 * We need to set the max speed of ARM according to fuse map.
321 	 */
322 	val >>= OCOTP_CFG3_SPEED_SHIFT;
323 	val &= 0x3;
324 
325 	if (of_machine_is_compatible("fsl,imx6ul"))
326 		if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
327 			imx6x_disable_freq_in_opp(dev, 696000000);
328 
329 	if (of_machine_is_compatible("fsl,imx6ull")) {
330 		if (val < OCOTP_CFG3_6ULL_SPEED_792MHZ)
331 			imx6x_disable_freq_in_opp(dev, 792000000);
332 
333 		if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
334 			imx6x_disable_freq_in_opp(dev, 900000000);
335 	}
336 
337 	return ret;
338 }
339 
imx6q_cpufreq_probe(struct platform_device * pdev)340 static int imx6q_cpufreq_probe(struct platform_device *pdev)
341 {
342 	struct device_node *np;
343 	struct dev_pm_opp *opp;
344 	unsigned long min_volt, max_volt;
345 	int num, ret;
346 	const struct property *prop;
347 	const __be32 *val;
348 	u32 nr, i, j;
349 
350 	cpu_dev = get_cpu_device(0);
351 	if (!cpu_dev) {
352 		pr_err("failed to get cpu0 device\n");
353 		return -ENODEV;
354 	}
355 
356 	np = of_node_get(cpu_dev->of_node);
357 	if (!np) {
358 		dev_err(cpu_dev, "failed to find cpu0 node\n");
359 		return -ENOENT;
360 	}
361 
362 	if (of_machine_is_compatible("fsl,imx6ul") ||
363 	    of_machine_is_compatible("fsl,imx6ull"))
364 		num_clks = IMX6UL_CPUFREQ_CLK_NUM;
365 	else
366 		num_clks = IMX6Q_CPUFREQ_CLK_NUM;
367 
368 	ret = clk_bulk_get(cpu_dev, num_clks, clks);
369 	if (ret)
370 		goto put_node;
371 
372 	arm_reg = regulator_get(cpu_dev, "arm");
373 	pu_reg = regulator_get_optional(cpu_dev, "pu");
374 	soc_reg = regulator_get(cpu_dev, "soc");
375 	if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
376 			PTR_ERR(soc_reg) == -EPROBE_DEFER ||
377 			PTR_ERR(pu_reg) == -EPROBE_DEFER) {
378 		ret = -EPROBE_DEFER;
379 		dev_dbg(cpu_dev, "regulators not ready, defer\n");
380 		goto put_reg;
381 	}
382 	if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
383 		dev_err(cpu_dev, "failed to get regulators\n");
384 		ret = -ENOENT;
385 		goto put_reg;
386 	}
387 
388 	ret = dev_pm_opp_of_add_table(cpu_dev);
389 	if (ret < 0) {
390 		dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
391 		goto put_reg;
392 	}
393 
394 	if (of_machine_is_compatible("fsl,imx6ul") ||
395 	    of_machine_is_compatible("fsl,imx6ull")) {
396 		ret = imx6ul_opp_check_speed_grading(cpu_dev);
397 	} else {
398 		ret = imx6q_opp_check_speed_grading(cpu_dev);
399 	}
400 	if (ret) {
401 		dev_err_probe(cpu_dev, ret, "failed to read ocotp\n");
402 		goto out_free_opp;
403 	}
404 
405 	num = dev_pm_opp_get_opp_count(cpu_dev);
406 	if (num < 0) {
407 		ret = num;
408 		dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
409 		goto out_free_opp;
410 	}
411 
412 	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
413 	if (ret) {
414 		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
415 		goto out_free_opp;
416 	}
417 
418 	/* Make imx6_soc_volt array's size same as arm opp number */
419 	imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
420 				     GFP_KERNEL);
421 	if (imx6_soc_volt == NULL) {
422 		ret = -ENOMEM;
423 		goto free_freq_table;
424 	}
425 
426 	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
427 	if (!prop || !prop->value)
428 		goto soc_opp_out;
429 
430 	/*
431 	 * Each OPP is a set of tuples consisting of frequency and
432 	 * voltage like <freq-kHz vol-uV>.
433 	 */
434 	nr = prop->length / sizeof(u32);
435 	if (nr % 2 || (nr / 2) < num)
436 		goto soc_opp_out;
437 
438 	for (j = 0; j < num; j++) {
439 		val = prop->value;
440 		for (i = 0; i < nr / 2; i++) {
441 			unsigned long freq = be32_to_cpup(val++);
442 			unsigned long volt = be32_to_cpup(val++);
443 			if (freq_table[j].frequency == freq) {
444 				imx6_soc_volt[soc_opp_count++] = volt;
445 				break;
446 			}
447 		}
448 	}
449 
450 soc_opp_out:
451 	/* use fixed soc opp volt if no valid soc opp info found in dtb */
452 	if (soc_opp_count != num) {
453 		dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
454 		for (j = 0; j < num; j++)
455 			imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
456 		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
457 			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
458 	}
459 
460 	if (of_property_read_u32(np, "clock-latency", &transition_latency))
461 		transition_latency = CPUFREQ_ETERNAL;
462 
463 	/*
464 	 * Calculate the ramp time for max voltage change in the
465 	 * VDDSOC and VDDPU regulators.
466 	 */
467 	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
468 	if (ret > 0)
469 		transition_latency += ret * 1000;
470 	if (!IS_ERR(pu_reg)) {
471 		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
472 		if (ret > 0)
473 			transition_latency += ret * 1000;
474 	}
475 
476 	/*
477 	 * OPP is maintained in order of increasing frequency, and
478 	 * freq_table initialised from OPP is therefore sorted in the
479 	 * same order.
480 	 */
481 	max_freq = freq_table[--num].frequency;
482 	opp = dev_pm_opp_find_freq_exact(cpu_dev,
483 				  freq_table[0].frequency * 1000, true);
484 	min_volt = dev_pm_opp_get_voltage(opp);
485 	dev_pm_opp_put(opp);
486 	opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
487 	max_volt = dev_pm_opp_get_voltage(opp);
488 	dev_pm_opp_put(opp);
489 
490 	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
491 	if (ret > 0)
492 		transition_latency += ret * 1000;
493 
494 	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
495 	if (ret) {
496 		dev_err(cpu_dev, "failed register driver: %d\n", ret);
497 		goto free_freq_table;
498 	}
499 
500 	of_node_put(np);
501 	return 0;
502 
503 free_freq_table:
504 	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
505 out_free_opp:
506 	dev_pm_opp_of_remove_table(cpu_dev);
507 put_reg:
508 	if (!IS_ERR(arm_reg))
509 		regulator_put(arm_reg);
510 	if (!IS_ERR(pu_reg))
511 		regulator_put(pu_reg);
512 	if (!IS_ERR(soc_reg))
513 		regulator_put(soc_reg);
514 
515 	clk_bulk_put(num_clks, clks);
516 put_node:
517 	of_node_put(np);
518 
519 	return ret;
520 }
521 
imx6q_cpufreq_remove(struct platform_device * pdev)522 static void imx6q_cpufreq_remove(struct platform_device *pdev)
523 {
524 	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
525 	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
526 	dev_pm_opp_of_remove_table(cpu_dev);
527 	regulator_put(arm_reg);
528 	if (!IS_ERR(pu_reg))
529 		regulator_put(pu_reg);
530 	regulator_put(soc_reg);
531 
532 	clk_bulk_put(num_clks, clks);
533 }
534 
535 static struct platform_driver imx6q_cpufreq_platdrv = {
536 	.driver = {
537 		.name	= "imx6q-cpufreq",
538 	},
539 	.probe		= imx6q_cpufreq_probe,
540 	.remove_new	= imx6q_cpufreq_remove,
541 };
542 module_platform_driver(imx6q_cpufreq_platdrv);
543 
544 MODULE_ALIAS("platform:imx6q-cpufreq");
545 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
546 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
547 MODULE_LICENSE("GPL");
548