162feb14eSJun Nie /* SPDX-License-Identifier: GPL-2.0 */ 262feb14eSJun Nie /* 362feb14eSJun Nie * Copyright (C) 2020 Linaro Ltd 462feb14eSJun Nie */ 562feb14eSJun Nie 662feb14eSJun Nie #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 762feb14eSJun Nie #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 862feb14eSJun Nie 919ced2aeSKonrad Dybcio #include <linux/soc/qcom/smd-rpm.h> 1019ced2aeSKonrad Dybcio 11*6ed0e5e6SKonrad Dybcio #include <dt-bindings/interconnect/qcom,rpm-icc.h> 1240cdeed6SKonrad Dybcio #include <linux/clk.h> 1340cdeed6SKonrad Dybcio #include <linux/interconnect-provider.h> 1440cdeed6SKonrad Dybcio #include <linux/platform_device.h> 15dcbce7b0SLeo Yan 1662feb14eSJun Nie #define RPM_BUS_MASTER_REQ 0x73616d62 1762feb14eSJun Nie #define RPM_BUS_SLAVE_REQ 0x766c7362 1862feb14eSJun Nie 1962feb14eSJun Nie #define to_qcom_provider(_provider) \ 2062feb14eSJun Nie container_of(_provider, struct qcom_icc_provider, provider) 2162feb14eSJun Nie 22e9d54c26SShawn Guo enum qcom_icc_type { 23e9d54c26SShawn Guo QCOM_ICC_NOC, 24e9d54c26SShawn Guo QCOM_ICC_BIMC, 2508c59040SShawn Guo QCOM_ICC_QNOC, 26e9d54c26SShawn Guo }; 27e9d54c26SShawn Guo 28a927eb09SKonrad Dybcio /** 29a927eb09SKonrad Dybcio * struct rpm_clk_resource - RPM bus clock resource 30a927eb09SKonrad Dybcio * @resource_type: RPM resource type of the clock resource 31a927eb09SKonrad Dybcio * @clock_id: index of the clock resource of a specific resource type 32a927eb09SKonrad Dybcio * @branch: whether the resource represents a branch clock 33a927eb09SKonrad Dybcio */ 34a927eb09SKonrad Dybcio struct rpm_clk_resource { 35a927eb09SKonrad Dybcio u32 resource_type; 36a927eb09SKonrad Dybcio u32 clock_id; 37a927eb09SKonrad Dybcio bool branch; 38a927eb09SKonrad Dybcio }; 39a927eb09SKonrad Dybcio 4062feb14eSJun Nie /** 4162feb14eSJun Nie * struct qcom_icc_provider - Qualcomm specific interconnect provider 4262feb14eSJun Nie * @provider: generic interconnect provider 432e2113c8SKonrad Dybcio * @num_intf_clks: the total number of intf_clks clk_bulk_data entries 44e9d54c26SShawn Guo * @type: the ICC provider type 452b6c7d64SDmitry Baryshkov * @regmap: regmap for QoS registers read/write access 4682a4b285SKonrad Dybcio * @qos_offset: offset to QoS registers 4765fac3b3SLeo Yan * @bus_clk_rate: bus clock rate in Hz 4811f63efeSKonrad Dybcio * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks 4911f63efeSKonrad Dybcio * @bus_clk: a pointer to a HLOS-owned bus clock 502e2113c8SKonrad Dybcio * @intf_clks: a clk_bulk_data array of interface clocks 51b979049cSKonrad Dybcio * @keep_alive: whether to always keep a minimum vote on the bus clocks 522e2113c8SKonrad Dybcio * @is_on: whether the bus is powered on 5362feb14eSJun Nie */ 5462feb14eSJun Nie struct qcom_icc_provider { 5562feb14eSJun Nie struct icc_provider provider; 562e2113c8SKonrad Dybcio int num_intf_clks; 57e9d54c26SShawn Guo enum qcom_icc_type type; 582b6c7d64SDmitry Baryshkov struct regmap *regmap; 590788f4d5SDmitry Baryshkov unsigned int qos_offset; 6011f63efeSKonrad Dybcio u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; 61a927eb09SKonrad Dybcio const struct rpm_clk_resource *bus_clk_desc; 6211f63efeSKonrad Dybcio struct clk *bus_clk; 632e2113c8SKonrad Dybcio struct clk_bulk_data *intf_clks; 64b979049cSKonrad Dybcio bool keep_alive; 652e2113c8SKonrad Dybcio bool is_on; 6662feb14eSJun Nie }; 6762feb14eSJun Nie 6862feb14eSJun Nie /** 692b6c7d64SDmitry Baryshkov * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters 702b6c7d64SDmitry Baryshkov * @areq_prio: node requests priority 712b6c7d64SDmitry Baryshkov * @prio_level: priority level for bus communication 722b6c7d64SDmitry Baryshkov * @limit_commands: activate/deactivate limiter mode during runtime 732b6c7d64SDmitry Baryshkov * @ap_owned: indicates if the node is owned by the AP or by the RPM 742b6c7d64SDmitry Baryshkov * @qos_mode: default qos mode for this node 752b6c7d64SDmitry Baryshkov * @qos_port: qos port number for finding qos registers of this node 7608c59040SShawn Guo * @urg_fwd_en: enable urgent forwarding 772b6c7d64SDmitry Baryshkov */ 782b6c7d64SDmitry Baryshkov struct qcom_icc_qos { 792b6c7d64SDmitry Baryshkov u32 areq_prio; 802b6c7d64SDmitry Baryshkov u32 prio_level; 812b6c7d64SDmitry Baryshkov bool limit_commands; 822b6c7d64SDmitry Baryshkov bool ap_owned; 832b6c7d64SDmitry Baryshkov int qos_mode; 842b6c7d64SDmitry Baryshkov int qos_port; 8508c59040SShawn Guo bool urg_fwd_en; 862b6c7d64SDmitry Baryshkov }; 872b6c7d64SDmitry Baryshkov 882b6c7d64SDmitry Baryshkov /** 8962feb14eSJun Nie * struct qcom_icc_node - Qualcomm specific interconnect nodes 9062feb14eSJun Nie * @name: the node name used in debugfs 9162feb14eSJun Nie * @id: a unique node identifier 9262feb14eSJun Nie * @links: an array of nodes where we can go next while traversing 9362feb14eSJun Nie * @num_links: the total number of @links 9402819953SKonrad Dybcio * @channels: number of channels at this node (e.g. DDR channels) 9562feb14eSJun Nie * @buswidth: width of the interconnect between a node and the bus (bytes) 96dcbce7b0SLeo Yan * @sum_avg: current sum aggregate value of all avg bw requests 97dcbce7b0SLeo Yan * @max_peak: current max aggregate value of all peak bw requests 9862feb14eSJun Nie * @mas_rpm_id: RPM id for devices that are bus masters 9962feb14eSJun Nie * @slv_rpm_id: RPM id for devices that are bus slaves 1002b6c7d64SDmitry Baryshkov * @qos: NoC QoS setting parameters 10162feb14eSJun Nie */ 10262feb14eSJun Nie struct qcom_icc_node { 10362feb14eSJun Nie unsigned char *name; 10462feb14eSJun Nie u16 id; 1052b6c7d64SDmitry Baryshkov const u16 *links; 10662feb14eSJun Nie u16 num_links; 10702819953SKonrad Dybcio u16 channels; 10862feb14eSJun Nie u16 buswidth; 109*6ed0e5e6SKonrad Dybcio u64 sum_avg[QCOM_SMD_RPM_STATE_NUM]; 110*6ed0e5e6SKonrad Dybcio u64 max_peak[QCOM_SMD_RPM_STATE_NUM]; 11162feb14eSJun Nie int mas_rpm_id; 11262feb14eSJun Nie int slv_rpm_id; 1132b6c7d64SDmitry Baryshkov struct qcom_icc_qos qos; 11462feb14eSJun Nie }; 11562feb14eSJun Nie 11662feb14eSJun Nie struct qcom_icc_desc { 1172ccf33c0SKrzysztof Kozlowski struct qcom_icc_node * const *nodes; 11862feb14eSJun Nie size_t num_nodes; 119a927eb09SKonrad Dybcio const struct rpm_clk_resource *bus_clk_desc; 1202e2113c8SKonrad Dybcio const char * const *intf_clocks; 1212e2113c8SKonrad Dybcio size_t num_intf_clocks; 122b979049cSKonrad Dybcio bool keep_alive; 123e9d54c26SShawn Guo enum qcom_icc_type type; 1242b6c7d64SDmitry Baryshkov const struct regmap_config *regmap_cfg; 1250788f4d5SDmitry Baryshkov unsigned int qos_offset; 12662feb14eSJun Nie }; 12762feb14eSJun Nie 1281d779317SKonrad Dybcio /* Valid for all bus types */ 1291d779317SKonrad Dybcio enum qos_mode { 1301d779317SKonrad Dybcio NOC_QOS_MODE_INVALID = 0, 1311d779317SKonrad Dybcio NOC_QOS_MODE_FIXED, 1321d779317SKonrad Dybcio NOC_QOS_MODE_BYPASS, 1331d779317SKonrad Dybcio }; 13462feb14eSJun Nie 135918b8604SKonrad Dybcio extern const struct rpm_clk_resource aggre1_clk; 136918b8604SKonrad Dybcio extern const struct rpm_clk_resource aggre2_clk; 137918b8604SKonrad Dybcio extern const struct rpm_clk_resource bimc_clk; 138918b8604SKonrad Dybcio extern const struct rpm_clk_resource bus_0_clk; 139918b8604SKonrad Dybcio extern const struct rpm_clk_resource bus_1_clk; 140918b8604SKonrad Dybcio extern const struct rpm_clk_resource bus_2_clk; 141918b8604SKonrad Dybcio extern const struct rpm_clk_resource mmaxi_0_clk; 142918b8604SKonrad Dybcio extern const struct rpm_clk_resource mmaxi_1_clk; 143918b8604SKonrad Dybcio extern const struct rpm_clk_resource qup_clk; 144918b8604SKonrad Dybcio 145918b8604SKonrad Dybcio extern const struct rpm_clk_resource aggre1_branch_clk; 146918b8604SKonrad Dybcio extern const struct rpm_clk_resource aggre2_branch_clk; 147918b8604SKonrad Dybcio 14863e8ab61SDmitry Baryshkov int qnoc_probe(struct platform_device *pdev); 14962feb14eSJun Nie int qnoc_remove(struct platform_device *pdev); 15062feb14eSJun Nie 15119ced2aeSKonrad Dybcio bool qcom_icc_rpm_smd_available(void); 15219ced2aeSKonrad Dybcio int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); 153a927eb09SKonrad Dybcio int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, int ctx, u32 rate); 15419ced2aeSKonrad Dybcio 15562feb14eSJun Nie #endif 156