Lines Matching +full:max +full:- +full:clk +full:- +full:rate +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
17 #include <linux/clk.h>
18 #include "clk.h"
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
57 if (rate == rate_table[i].rate) in rockchip_get_pll_settings()
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
73 if (drate >= rate_table[i].rate) in rockchip_pll_round_rate()
74 return rate_table[i].rate; in rockchip_pll_round_rate()
78 return rate_table[i - 1].rate; in rockchip_pll_round_rate()
88 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
92 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, in rockchip_pll_wait_lock()
93 val & BIT(pll->lock_shift), 0, 1000); in rockchip_pll_wait_lock()
126 * Lock time typical 250, max 500 input clock cycles @24MHz in rockchip_rk3036_pll_wait_lock()
129 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1), in rockchip_rk3036_pll_wait_lock()
140 struct rockchip_pll_rate_table *rate) in rockchip_rk3036_pll_get_params() argument
144 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_get_params()
145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) in rockchip_rk3036_pll_get_params()
150 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_get_params()
151 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
155 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) in rockchip_rk3036_pll_get_params()
158 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_get_params()
159 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) in rockchip_rk3036_pll_get_params()
190 const struct rockchip_pll_rate_table *rate) in rockchip_rk3036_pll_set_params() argument
192 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3036_pll_set_params()
193 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params()
200 …pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, … in rockchip_rk3036_pll_set_params()
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
202 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
205 cur.rate = 0; in rockchip_rk3036_pll_set_params()
207 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3036_pll_set_params()
209 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
218 pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_set_params()
220 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
222 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
224 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
226 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_set_params()
229 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
231 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; in rockchip_rk3036_pll_set_params()
232 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
252 const struct rockchip_pll_rate_table *rate; in rockchip_rk3036_pll_set_rate() local
254 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", in rockchip_rk3036_pll_set_rate()
255 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3036_pll_set_rate()
257 /* Get required rate settings from table */ in rockchip_rk3036_pll_set_rate()
258 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_set_rate()
259 if (!rate) { in rockchip_rk3036_pll_set_rate()
260 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3036_pll_set_rate()
261 drate, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_set_rate()
262 return -EINVAL; in rockchip_rk3036_pll_set_rate()
265 return rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_set_rate()
273 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_enable()
285 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_disable()
291 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_is_enabled()
299 const struct rockchip_pll_rate_table *rate; in rockchip_rk3036_pll_init() local
303 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3036_pll_init()
307 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_init()
309 /* when no rate setting for the current rate, rely on clk_set_rate */ in rockchip_rk3036_pll_init()
310 if (!rate) in rockchip_rk3036_pll_init()
315 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3036_pll_init()
317 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_init()
320 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
322 rate->dsmpd, rate->frac); in rockchip_rk3036_pll_init()
324 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
325 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
326 rate->dsmpd != cur.dsmpd || in rockchip_rk3036_pll_init()
327 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3036_pll_init()
328 struct clk *parent = clk_get_parent(hw->clk); in rockchip_rk3036_pll_init()
332 __func__, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_init()
336 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3036_pll_init()
337 __func__, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_init()
338 rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_init()
381 struct rockchip_pll_rate_table *rate) in rockchip_rk3066_pll_get_params() argument
385 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_get_params()
386 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) in rockchip_rk3066_pll_get_params()
388 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) in rockchip_rk3066_pll_get_params()
391 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_get_params()
392 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) in rockchip_rk3066_pll_get_params()
395 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_get_params()
396 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) in rockchip_rk3066_pll_get_params()
408 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_recalc_rate()
425 const struct rockchip_pll_rate_table *rate) in rockchip_rk3066_pll_set_params() argument
427 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3066_pll_set_params()
428 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params()
434 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", in rockchip_rk3066_pll_set_params()
435 __func__, rate->rate, rate->nr, rate->no, rate->nf); in rockchip_rk3066_pll_set_params()
438 cur.rate = 0; in rockchip_rk3066_pll_set_params()
440 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3066_pll_set_params()
442 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
448 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
451 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
453 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_params()
455 pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_set_params()
457 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, in rockchip_rk3066_pll_set_params()
459 pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_set_params()
460 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, in rockchip_rk3066_pll_set_params()
462 pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_set_params()
466 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
467 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); in rockchip_rk3066_pll_set_params()
478 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
487 const struct rockchip_pll_rate_table *rate; in rockchip_rk3066_pll_set_rate() local
489 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", in rockchip_rk3066_pll_set_rate()
492 /* Get required rate settings from table */ in rockchip_rk3066_pll_set_rate()
493 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_set_rate()
494 if (!rate) { in rockchip_rk3066_pll_set_rate()
495 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3066_pll_set_rate()
497 return -EINVAL; in rockchip_rk3066_pll_set_rate()
500 return rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_set_rate()
508 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_enable()
520 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_disable()
526 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_is_enabled()
534 const struct rockchip_pll_rate_table *rate; in rockchip_rk3066_pll_init() local
538 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3066_pll_init()
542 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_init()
544 /* when no rate setting for the current rate, rely on clk_set_rate */ in rockchip_rk3066_pll_init()
545 if (!rate) in rockchip_rk3066_pll_init()
551 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, in rockchip_rk3066_pll_init()
552 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); in rockchip_rk3066_pll_init()
553 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf in rockchip_rk3066_pll_init()
554 || rate->nb != cur.nb) { in rockchip_rk3066_pll_init()
555 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3066_pll_init()
557 rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_init()
606 * Lock time typical 250, max 500 input clock cycles @24MHz in rockchip_rk3399_pll_wait_lock()
609 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2), in rockchip_rk3399_pll_wait_lock()
620 struct rockchip_pll_rate_table *rate) in rockchip_rk3399_pll_get_params() argument
624 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3399_pll_get_params()
625 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) in rockchip_rk3399_pll_get_params()
628 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3399_pll_get_params()
629 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) in rockchip_rk3399_pll_get_params()
631 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) in rockchip_rk3399_pll_get_params()
633 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3399_pll_get_params()
636 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_get_params()
637 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) in rockchip_rk3399_pll_get_params()
640 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_get_params()
641 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) in rockchip_rk3399_pll_get_params()
672 const struct rockchip_pll_rate_table *rate) in rockchip_rk3399_pll_set_params() argument
674 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3399_pll_set_params()
675 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3399_pll_set_params()
682 …pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, … in rockchip_rk3399_pll_set_params()
683 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
684 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
687 cur.rate = 0; in rockchip_rk3399_pll_set_params()
689 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3399_pll_set_params()
691 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3399_pll_set_params()
696 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, in rockchip_rk3399_pll_set_params()
698 pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3399_pll_set_params()
700 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, in rockchip_rk3399_pll_set_params()
702 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, in rockchip_rk3399_pll_set_params()
704 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, in rockchip_rk3399_pll_set_params()
706 pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3399_pll_set_params()
709 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_set_params()
711 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; in rockchip_rk3399_pll_set_params()
712 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_set_params()
714 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, in rockchip_rk3399_pll_set_params()
716 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_set_params()
727 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
736 const struct rockchip_pll_rate_table *rate; in rockchip_rk3399_pll_set_rate() local
738 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", in rockchip_rk3399_pll_set_rate()
739 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3399_pll_set_rate()
741 /* Get required rate settings from table */ in rockchip_rk3399_pll_set_rate()
742 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_set_rate()
743 if (!rate) { in rockchip_rk3399_pll_set_rate()
744 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3399_pll_set_rate()
745 drate, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_set_rate()
746 return -EINVAL; in rockchip_rk3399_pll_set_rate()
749 return rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_set_rate()
757 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_enable()
769 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_disable()
775 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_is_enabled()
783 const struct rockchip_pll_rate_table *rate; in rockchip_rk3399_pll_init() local
787 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3399_pll_init()
791 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_init()
793 /* when no rate setting for the current rate, rely on clk_set_rate */ in rockchip_rk3399_pll_init()
794 if (!rate) in rockchip_rk3399_pll_init()
799 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3399_pll_init()
801 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3399_pll_init()
804 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3399_pll_init()
805 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3399_pll_init()
806 rate->dsmpd, rate->frac); in rockchip_rk3399_pll_init()
808 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3399_pll_init()
809 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3399_pll_init()
810 rate->dsmpd != cur.dsmpd || in rockchip_rk3399_pll_init()
811 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3399_pll_init()
812 struct clk *parent = clk_get_parent(hw->clk); in rockchip_rk3399_pll_init()
816 __func__, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_init()
820 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3399_pll_init()
821 __func__, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_init()
822 rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_init()
867 * Lock time typical 250, max 500 input clock cycles @24MHz in rockchip_rk3588_pll_wait_lock()
870 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6), in rockchip_rk3588_pll_wait_lock()
881 struct rockchip_pll_rate_table *rate) in rockchip_rk3588_pll_get_params() argument
885 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); in rockchip_rk3588_pll_get_params()
886 rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK); in rockchip_rk3588_pll_get_params()
888 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_get_params()
889 rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK); in rockchip_rk3588_pll_get_params()
890 rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK); in rockchip_rk3588_pll_get_params()
892 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); in rockchip_rk3588_pll_get_params()
893 rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK); in rockchip_rk3588_pll_get_params()
921 const struct rockchip_pll_rate_table *rate) in rockchip_rk3588_pll_set_params() argument
923 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3588_pll_set_params()
924 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3588_pll_set_params()
930 pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", in rockchip_rk3588_pll_set_params()
931 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); in rockchip_rk3588_pll_set_params()
934 cur.rate = 0; in rockchip_rk3588_pll_set_params()
936 if (pll->type == pll_rk3588) { in rockchip_rk3588_pll_set_params()
937 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3588_pll_set_params()
939 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3588_pll_set_params()
947 pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3588_pll_set_params()
950 writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT), in rockchip_rk3588_pll_set_params()
951 pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3588_pll_set_params()
953 writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) | in rockchip_rk3588_pll_set_params()
954 HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT), in rockchip_rk3588_pll_set_params()
955 pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3588_pll_set_params()
957 writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT), in rockchip_rk3588_pll_set_params()
958 pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3588_pll_set_params()
962 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_set_params()
972 if ((pll->type == pll_rk3588) && rate_change_remuxed) in rockchip_rk3588_pll_set_params()
973 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3588_pll_set_params()
982 const struct rockchip_pll_rate_table *rate; in rockchip_rk3588_pll_set_rate() local
984 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", in rockchip_rk3588_pll_set_rate()
985 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3588_pll_set_rate()
987 /* Get required rate settings from table */ in rockchip_rk3588_pll_set_rate()
988 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3588_pll_set_rate()
989 if (!rate) { in rockchip_rk3588_pll_set_rate()
990 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3588_pll_set_rate()
991 drate, __clk_get_name(hw->clk)); in rockchip_rk3588_pll_set_rate()
992 return -EINVAL; in rockchip_rk3588_pll_set_rate()
995 return rockchip_rk3588_pll_set_params(pll, rate); in rockchip_rk3588_pll_set_rate()
1003 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_enable()
1014 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_disable()
1020 u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_is_enabled()
1029 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3588_pll_init()
1056 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, in rockchip_clk_register_pll()
1068 struct clk *pll_clk, *mux_clk; in rockchip_clk_register_pll()
1074 return ERR_PTR(-EINVAL); in rockchip_clk_register_pll()
1082 return ERR_PTR(-ENOMEM); in rockchip_clk_register_pll()
1085 pll->pll_mux_ops = &clk_mux_ops; in rockchip_clk_register_pll()
1086 pll_mux = &pll->pll_mux; in rockchip_clk_register_pll()
1087 pll_mux->reg = ctx->reg_base + mode_offset; in rockchip_clk_register_pll()
1088 pll_mux->shift = mode_shift; in rockchip_clk_register_pll()
1090 pll_mux->mask = PLL_RK3328_MODE_MASK; in rockchip_clk_register_pll()
1092 pll_mux->mask = PLL_MODE_MASK; in rockchip_clk_register_pll()
1093 pll_mux->flags = 0; in rockchip_clk_register_pll()
1094 pll_mux->lock = &ctx->lock; in rockchip_clk_register_pll()
1095 pll_mux->hw.init = &init; in rockchip_clk_register_pll()
1102 pll_mux->flags |= CLK_MUX_HIWORD_MASK; in rockchip_clk_register_pll()
1104 /* the actual muxing is xin24m, pll-output, xin32k */ in rockchip_clk_register_pll()
1111 init.ops = pll->pll_mux_ops; in rockchip_clk_register_pll()
1118 mux_clk = clk_register(NULL, &pll_mux->hw); in rockchip_clk_register_pll()
1135 for (len = 0; rate_table[len].rate != 0; ) in rockchip_clk_register_pll()
1138 pll->rate_count = len; in rockchip_clk_register_pll()
1139 pll->rate_table = kmemdup(rate_table, in rockchip_clk_register_pll()
1140 pll->rate_count * in rockchip_clk_register_pll()
1143 WARN(!pll->rate_table, in rockchip_clk_register_pll()
1144 "%s: could not allocate rate table for %s\n", in rockchip_clk_register_pll()
1151 if (!pll->rate_table) in rockchip_clk_register_pll()
1157 if (!pll->rate_table || IS_ERR(ctx->grf)) in rockchip_clk_register_pll()
1163 if (!pll->rate_table) in rockchip_clk_register_pll()
1170 if (!pll->rate_table) in rockchip_clk_register_pll()
1177 pr_warn("%s: Unknown pll type for pll clk %s\n", in rockchip_clk_register_pll()
1181 pll->hw.init = &init; in rockchip_clk_register_pll()
1182 pll->type = pll_type; in rockchip_clk_register_pll()
1183 pll->reg_base = ctx->reg_base + con_offset; in rockchip_clk_register_pll()
1184 pll->lock_offset = grf_lock_offset; in rockchip_clk_register_pll()
1185 pll->lock_shift = lock_shift; in rockchip_clk_register_pll()
1186 pll->flags = clk_pll_flags; in rockchip_clk_register_pll()
1187 pll->lock = &ctx->lock; in rockchip_clk_register_pll()
1188 pll->ctx = ctx; in rockchip_clk_register_pll()
1190 pll_clk = clk_register(NULL, &pll->hw); in rockchip_clk_register_pll()
1200 kfree(pll->rate_table); in rockchip_clk_register_pll()