/openbmc/linux/drivers/phy/freescale/ |
H A D | phy-fsl-imx8m-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0+ 12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 18 #include <linux/reset.h> 20 #include <dt-bindings/phy/phy-imx8-pcie.h> 51 IMX8MP, enumerator 65 struct reset_control *reset; member 79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on() 80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on() 82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on() 84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on() [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | fsl,imx6q-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lucas Stach <l.stach@pengutronix.de> 11 - Richard Zhu <hongxing.zhu@nxp.com> 15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. 22 - fsl,imx8mm-pcie-ep 23 - fsl,imx8mq-pcie-ep 24 - fsl,imx8mp-pcie-ep [all …]
|
H A D | fsl,imx6q-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lucas Stach <l.stach@pengutronix.de> 11 - Richard Zhu <hongxing.zhu@nxp.com> 15 and thus inherits all the common properties defined in snps,dw-pcie.yaml. 19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree 25 - fsl,imx6q-pcie 26 - fsl,imx6sx-pcie [all …]
|
H A D | fsl,imx6q-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lucas Stach <l.stach@pengutronix.de> 11 - Richard Zhu <hongxing.zhu@nxp.com> 22 clock-names: 26 num-lanes: 29 fsl,imx7d-pcie-phy: 31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | fsl,xcvr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Viorel Suman <viorel.suman@nxp.com> 13 NXP XCVR (Audio Transceiver) is a on-chip functional module 23 - fsl,imx8mp-xcvr 24 - fsl,imx93-xcvr 28 - description: 20K RAM for code and data 29 - description: registers space 30 - description: RX FIFO address [all …]
|
/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx8mp-clock.h> 7 #include <dt-bindings/power/imx8mp-power.h> 8 #include <dt-bindings/reset/imx8mp-reset.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/interconnect/fsl,imx8mp.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 15 #include "imx8mp-pinfunc.h" [all …]
|
H A D | imx8mp-dhcom-pdk2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * DHCOM iMX8MP variant: 6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2 7 * DHCOM PCB number: 660-100 or newer 8 * PDK2 PCB number: 516-400 or newer 11 /dts-v1/; 13 #include <dt-bindings/leds/common.h> 14 #include <dt-bindings/phy/phy-imx8-pcie.h> 15 #include "imx8mp-dhcom-som.dtsi" 19 compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som", [all …]
|
H A D | imx8mp-dhcom-pdk3.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * DHCOM iMX8MP variant: 6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2 7 * DHCOM PCB number: 660-100 or newer 8 * PDK3 PCB number: 669-100 or newer 11 /dts-v1/; 13 #include <dt-bindings/leds/common.h> 14 #include <dt-bindings/phy/phy-imx8-pcie.h> 15 #include "imx8mp-dhcom-som.dtsi" 19 compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som", [all …]
|
H A D | imx8mp-debix-som-a-bmb-08.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 9 #include "imx8mp-debix-som-a.dtsi" 12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08"; 13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a", 14 "fsl,imx8mp"; 22 stdout-path = &uart2; 25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { 26 compatible = "regulator-fixed"; 27 regulator-min-microvolt = <3300000>; [all …]
|
H A D | imx8mp-debix-model-a.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/usb/pd.h> 13 #include "imx8mp.dtsi" 17 compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; 20 stdout-path = &uart2; 24 compatible = "gpio-leds"; 25 pinctrl-names = "default"; [all …]
|
H A D | imx8mp-beacon-kit.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include <dt-bindings/usb/pd.h> 9 #include <dt-bindings/phy/phy-imx8-pcie.h> 10 #include "imx8mp.dtsi" 11 #include "imx8mp-beacon-som.dtsi" 15 compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp"; 23 stdout-path = &uart2; 27 compatible = "usb-c-connector"; 28 label = "USB-C"; [all …]
|
H A D | imx8mp-debix-som-a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "imx8mp.dtsi" 11 compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp"; 13 reg_usdhc2_vmmc: regulator-usdhc2 { 14 compatible = "regulator-fixed"; 15 pinctrl-names = "default"; 16 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 17 regulator-name = "VSD_3V3"; 18 regulator-min-microvolt = <3300000>; 19 regulator-max-microvolt = <3300000>; [all …]
|
H A D | imx8mp-phycore-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <dt-bindings/net/ti-dp83867.h> 8 #include "imx8mp.dtsi" 11 model = "PHYTEC phyCORE-i.MX8MP"; 12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 26 cpu-supply = <&buck2>; 30 cpu-supply = <&buck2>; 34 cpu-supply = <&buck2>; 38 cpu-supply = <&buck2>; 43 pinctrl-names = "default"; [all …]
|
H A D | imx8mp-tqma8mpql.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 7 #include "imx8mp.dtsi" 10 model = "TQ-Systems i.MX8MPlus TQMa8MPxL"; 11 compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 19 reg_vcc3v3: regulator-vcc3v3 { 20 compatible = "regulator-fixed"; 21 regulator-name = "VCC3V3"; 22 regulator-min-microvolt = <3300000>; [all …]
|
H A D | imx8mp-tqma8mpql-mba8mpxl.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 7 /dts-v1/; 9 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/phy/phy-imx8-pcie.h> 12 #include <dt-bindings/pwm/pwm.h> 13 #include "imx8mp-tqma8mpql.dtsi" 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; [all …]
|
H A D | imx8mp-evk.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 9 #include "imx8mp.dtsi" 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 16 stdout-path = &uart2; 19 hdmi-connector { 20 compatible = "hdmi-connector"; 26 remote-endpoint = <&adv7535_out>; 31 gpio-leds { [all …]
|
H A D | imx8mp-data-modul-edm-sbc.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include <dt-bindings/net/qca-ar803x.h> 9 #include "imx8mp.dtsi" 13 compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp"; 21 stdout-path = &uart3; 31 compatible = "pwm-backlight"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_panel_backlight>; 34 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/reset/ |
H A D | fsl,imx7-src.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale i.MX7 System Reset Controller 10 - Andrey Smirnov <andrew.smirnov@gmail.com> 13 The system reset controller can be used to reset various set of 14 peripherals. Device nodes that need access to reset lines should 15 specify them as a reset phandle in their corresponding node as 16 specified in reset.txt. [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/power/ |
H A D | fsl,imx-gpcv2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andrey Smirnov <andrew.smirnov@gmail.com> 18 Documentation/devicetree/bindings/power/power-domain.yaml, which are 21 IP cores belonging to a power domain should contain a 'power-domains' 27 - fsl,imx7d-gpc 28 - fsl,imx8mn-gpc 29 - fsl,imx8mq-gpc [all …]
|
/openbmc/linux/drivers/pci/controller/dwc/ |
H A D | pci-imx6.c | 1 // SPDX-License-Identifier: GPL-2.0 17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 31 #include <linux/reset.h> 36 #include "pcie-designware.h" 45 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 54 IMX8MP, enumerator 109 /* PCIe Port Logic registers (memory-mapped) */ 122 /* PHY registers (not memory-mapped) */ 159 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && in imx6_pcie_grp_offset() [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | fsl,imx8-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Richard Zhu <hongxing.zhu@nxp.com> 13 "#phy-cells": 18 - fsl,imx8mm-pcie-phy 19 - fsl,imx8mp-pcie-phy 27 clock-names: 29 - const: ref [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/watchdog/ |
H A D | fsl-imx-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Anson Huang <Anson.Huang@nxp.com> 15 - const: fsl,imx21-wdt 16 - items: 17 - enum: 18 - fsl,imx25-wdt 19 - fsl,imx27-wdt [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
H A D | fsl,imx-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX Co-Processor 10 This binding provides support for ARM Cortex M4 Co-processor found on some NXP iMX SoCs. 13 - Peng Fan <peng.fan@nxp.com> 18 - fsl,imx6sx-cm4 19 - fsl,imx7d-cm4 20 - fsl,imx7ulp-cm4 [all …]
|
/openbmc/linux/drivers/reset/ |
H A D | reset-imx7.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * i.MX7 System Reset Controller (SRC) driver 14 #include <linux/reset-controller.h> 16 #include <dt-bindings/reset/imx7-reset.h> 17 #include <dt-bindings/reset/imx8mq-reset.h> 18 #include <dt-bindings/reset/imx8mp-reset.h> 51 const struct imx7_src_signal *signal = &imx7src->signals[id]; in imx7_reset_update() 53 return regmap_update_bits(imx7src->regmap, in imx7_reset_update() 54 signal->offset, signal->bit, value); in imx7_reset_update() 95 const unsigned int bit = imx7src->signals[id].bit; in imx7_reset_set() [all …]
|
/openbmc/linux/drivers/pmdomain/imx/ |
H A D | imx8mp-blk-ctrl.c | 1 // SPDX-License-Identifier: GPL-2.0+ 9 #include <linux/clk-provider.h> 19 #include <dt-bindings/power/imx8mp-power.h> 104 regmap_update_bits(clk->regmap, GPR_REG2, in clk_hsio_pll_prepare() 110 /* de-assert PLL reset */ in clk_hsio_pll_prepare() 111 regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST); in clk_hsio_pll_prepare() 114 regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE); in clk_hsio_pll_prepare() 116 return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val, in clk_hsio_pll_prepare() 124 regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0); in clk_hsio_pll_unprepare() 131 return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK); in clk_hsio_pll_is_prepared() [all …]
|