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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39 |
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| #
6fe88df7 |
| 19-Jul-2023 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Update regulator output voltages
Set the regulator voltages to the min and max values the i.MX8MP
requires and not what the PMIC provides.
Signed-off-by: Teresa Remm
arm64: dts: imx8mp-phycore-som: Update regulator output voltages
Set the regulator voltages to the min and max values the i.MX8MP
requires and not what the PMIC provides.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
c2d28a0c |
| 19-Jul-2023 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Add regulator names
Add regulator-names for more meaningful description.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.
arm64: dts: imx8mp-phycore-som: Add regulator names
Add regulator-names for more meaningful description.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
1a5a0343 |
| 19-Jul-2023 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Remove LDO2 and LDO4 pmic nodes
We do not touch LDO2 and LDO4 in linux as they are bypassed.
So remove them completely from device tree.
Signed-off-by: Teresa Remmet
arm64: dts: imx8mp-phycore-som: Remove LDO2 and LDO4 pmic nodes
We do not touch LDO2 and LDO4 in linux as they are bypassed.
So remove them completely from device tree.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
b34f6681 |
| 19-Jul-2023 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Correct pad settings
Do not set reserved bits 0 and 3 in pad configuration.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kern
arm64: dts: imx8mp-phycore-som: Correct pad settings
Do not set reserved bits 0 and 3 in pad configuration.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
2d3779dd |
| 19-Jul-2023 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Order properties alphabetically
Rearrange properties in order:
- compatible
- reg
- other generic properties
- device specific properties
- vendor specific properties
arm64: dts: imx8mp-phycore-som: Order properties alphabetically
Rearrange properties in order:
- compatible
- reg
- other generic properties
- device specific properties
- vendor specific properties
- status
And use alphabetical order inside a group.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
312ab094 |
| 19-Jul-2023 |
Christian Hemp <c.hemp@phytec.de> |
arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt
In some occasions the ethernet phy IRQ can not be detected correctly
by the SoC. This leads to a non detected link in Linux. The problem is
c
arm64: dts: imx8mp-phycore-som: Remove eth phy interrupt
In some occasions the ethernet phy IRQ can not be detected correctly
by the SoC. This leads to a non detected link in Linux. The problem is
caused by the buffer that adjusts the voltage between ethernet phy
and SoC. To workaround this, remove the IRQ support for the ethernet
phy and use polling instead.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80 |
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| #
cfd04dd1 |
| 21-Nov-2022 |
Fabio Estevam <festevam@denx.de> |
arm64: dts: imx8mp-phycore-som: Remove invalid PMIC property
'regulator-compatible' is not a valid property according to
nxp,pca9450-regulator.yaml and causes the following warning:
DTC_CHK arch/
arm64: dts: imx8mp-phycore-som: Remove invalid PMIC property
'regulator-compatible' is not a valid property according to
nxp,pca9450-regulator.yaml and causes the following warning:
DTC_CHK arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb
...
pmic@25: regulators:LDO1: Unevaluated properties are not allowed ('regulator-compatible' was unexpected)
Remove the invalid 'regulator-compatible' property.
Cc: Teresa Remmet <t.remmet@phytec.de>
Fixes: 88f7f6bcca37 ("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25 |
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| #
59f5ae05 |
| 18-Feb-2022 |
Jonas Kuenstler <j.kuenstler@phytec.de> |
arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC
Set the usdhc root clock to 400MHz to be able to support
HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM.
Signed-off-by: Jonas Kuen
arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC
Set the usdhc root clock to 400MHz to be able to support
HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM.
Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
b00e3e03 |
| 18-Feb-2022 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4
LDO4 is not connected so disable it. And LDO5 is used for VSEL of
the NVCC_SD2 SD-Card bus. Having it disabled seems not to h
arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4
LDO4 is not connected so disable it. And LDO5 is used for VSEL of
the NVCC_SD2 SD-Card bus. Having it disabled seems not to have an
impact on the functionality. We enable it, as it is used.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
8c0d1785 |
| 18-Feb-2022 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage
Add bindings for VDD_ARM (BUCK2) run and standby voltage.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn
arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage
Add bindings for VDD_ARM (BUCK2) run and standby voltage.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
2aeded99 |
| 18-Feb-2022 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Update WDOG muxing
To be able to trigger a reset also from an external source we
need to configure the WDOG pin as open drain.
Signed-off-by: Teresa Remmet <t.remmet
arm64: dts: imx8mp-phycore-som: Update WDOG muxing
To be able to trigger a reset also from an external source we
need to configure the WDOG pin as open drain.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
97c8800e |
| 18-Feb-2022 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines
Reduce drive strength on fec tx lines for signal quality improvements.
Measurements showed that TD0 and TD1 require X4 and the
arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines
Reduce drive strength on fec tx lines for signal quality improvements.
Measurements showed that TD0 and TD1 require X4 and the other lines
X2 for optimized settings.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
c173a181 |
| 18-Feb-2022 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
Set eMMC drive strength for USDHC3_DATA lines (200Mhz)
to X4 for signal improvement.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Revi
arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
Set eMMC drive strength for USDHC3_DATA lines (200Mhz)
to X4 for signal improvement.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
4fab14f0 |
| 18-Feb-2022 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy
To fit spec requirements set minimum output impedance for dp83867
ethernet phy.
Signed-off-by: Teresa Remmet <t.remmet@phyte
arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy
To fit spec requirements set minimum output impedance for dp83867
ethernet phy.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61 |
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| #
04aa946d |
| 20-Aug-2021 |
Haibo Chen <haibo.chen@nxp.com> |
arm64: dts: imx8: change the spi-nor tx
Before commit 0e30f47232ab5 ("mtd: spi-nor: add support for DTR protocol"),
for all PP command, it only support 1-1-1 mode, no matter the tx setting
in dts. B
arm64: dts: imx8: change the spi-nor tx
Before commit 0e30f47232ab5 ("mtd: spi-nor: add support for DTR protocol"),
for all PP command, it only support 1-1-1 mode, no matter the tx setting
in dts. But after the upper commit, the logic change. It will choose
the best mode(fastest mode) which flash device and spi-nor host controller
both support.
qspi and fspi host controller do not support read 1-4-4 mode. so need to
set the tx to 1, let the common code finally select read 1-1-4 mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22 |
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| #
a4f27c75 |
| 08-Mar-2021 |
Heiko Schocher <hs@denx.de> |
arm64: dts: imx8mp-phycore-som: enable spi nor
enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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| #
412627f6 |
| 11-Mar-2021 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: imx8mp-phyboard-pollux-rdk: Add missing pinctrl entry
Add missing pinctrl-names for i2c gpio recovery mode.
Fixes: 88f7f6bcca37 ("arm64: dts: freescale: Add support for phyBOARD-Pollux-
arm64: dts: imx8mp-phyboard-pollux-rdk: Add missing pinctrl entry
Add missing pinctrl-names for i2c gpio recovery mode.
Fixes: 88f7f6bcca37 ("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP")
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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| #
88f7f6bc |
| 07-Jan-2021 |
Teresa Remmet <t.remmet@phytec.de> |
arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP
Add initial support for phyBOARD-Pollux-i.MX8MP.
Supported basic features:
* eMMC
* i2c EEPROM
* i2c RTC
* i2c LED
* PMIC
* debug
arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP
Add initial support for phyBOARD-Pollux-i.MX8MP.
Supported basic features:
* eMMC
* i2c EEPROM
* i2c RTC
* i2c LED
* PMIC
* debug UART
* SD card
* 1Gbit Ethernet (fec)
* watchdog
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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