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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28 |
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| #
8bbec86c |
| 08-May-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
dt-bindings: PCI: fsl,imx6q: fix assigned-clocks warning
assigned-clocks are a dependency of clocks, however the dtschema has
limitation and expects clocks to be present in the binding using
assigne
dt-bindings: PCI: fsl,imx6q: fix assigned-clocks warning
assigned-clocks are a dependency of clocks, however the dtschema has
limitation and expects clocks to be present in the binding using
assigned-clocks, not in other referenced bindings. The clocks were
defined in common fsl,imx6q-pcie-common.yaml, which is referenced by
fsl,imx6q-pcie-ep.yaml. The fsl,imx6q-pcie-ep.yaml used assigned-clocks
thus leading to warnings:
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.example.dtb: pcie-ep@33800000:
Unevaluated properties are not allowed ('assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks' were unexpected)
From schema: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
Fix this by moving clocks to each specific schema from the common one
and narrowing them to strictly match what is expected for given device.
Fixes: b10f82380eeb ("dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Link: https://lore.kernel.org/r/20230508071837.68552-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
show more ...
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Revision tags: v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2 |
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| #
b10f8238 |
| 15-Feb-2023 |
Richard Zhu <hongxing.zhu@nxp.com> |
dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
Restruct i.MX PCIe schema, derive the common properties, thus they can
be shared by both the RC and Endpoint schema.
Update the description of fsl
dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
Restruct i.MX PCIe schema, derive the common properties, thus they can
be shared by both the RC and Endpoint schema.
Update the description of fsl,imx6q-pcie.yaml, and move the EP mode
compatible to fsl,imx6q-pcie-ep.yaml.
Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER
accordingly.
Link: https://lore.kernel.org/r/1676441915-1394-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
show more ...
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Revision tags: v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7 |
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| #
2dd6dc57 |
| 15-Jan-2023 |
Richard Zhu <hongxing.zhu@nxp.com> |
dt-bindings: imx6q-pcie: Add i.MX8MP PCIe EP mode compatible string
Add i.MX8MP PCIe endpoint mode compatible string.
Link: https://lore.kernel.org/r/1673847684-31893-4-git-send-email-hongxing.zhu@
dt-bindings: imx6q-pcie: Add i.MX8MP PCIe EP mode compatible string
Add i.MX8MP PCIe endpoint mode compatible string.
Link: https://lore.kernel.org/r/1673847684-31893-4-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
show more ...
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| #
dea44b62 |
| 15-Jan-2023 |
Richard Zhu <hongxing.zhu@nxp.com> |
dt-bindings: imx6q-pcie: Add i.MX8MQ PCIe EP mode compatible string
Add i.MX8MQ PCIe endpoint mode compatible string.
Link: https://lore.kernel.org/r/1673847684-31893-3-git-send-email-hongxing.zhu@
dt-bindings: imx6q-pcie: Add i.MX8MQ PCIe EP mode compatible string
Add i.MX8MQ PCIe endpoint mode compatible string.
Link: https://lore.kernel.org/r/1673847684-31893-3-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
show more ...
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| #
1af5ea1d |
| 15-Jan-2023 |
Richard Zhu <hongxing.zhu@nxp.com> |
dt-bindings: imx6q-pcie: Add i.MX8MM PCIe EP mode compatible string
Add i.MX8MM PCIe endpoint mode compatible string.
Link: https://lore.kernel.org/r/1673847684-31893-2-git-send-email-hongxing.zhu@
dt-bindings: imx6q-pcie: Add i.MX8MM PCIe EP mode compatible string
Add i.MX8MM PCIe endpoint mode compatible string.
Link: https://lore.kernel.org/r/1673847684-31893-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
show more ...
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Revision tags: v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1 |
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| #
1a2cead1 |
| 10-Dec-2022 |
Marek Vasut <marex@denx.de> |
dt-bindings: imx6q-pcie: Handle more resets on legacy platforms
The i.MX6 and i.MX7D does not use block controller to toggle PCIe
reset, hence the PCIe DT description contains three reset entries
on
dt-bindings: imx6q-pcie: Handle more resets on legacy platforms
The i.MX6 and i.MX7D does not use block controller to toggle PCIe
reset, hence the PCIe DT description contains three reset entries
on these older SoCs. Add this exception into the binding document.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20221211024859.672076-3-marex@denx.de
Signed-off-by: Rob Herring <robh@kernel.org>
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| #
8b8161ed |
| 10-Dec-2022 |
Marek Vasut <marex@denx.de> |
dt-bindings: imx6q-pcie: Handle various PD configurations
The i.MX SoCs have various power domain configurations routed into
the PCIe IP. MX6SX is the only one which contains 2 domains and also
uses
dt-bindings: imx6q-pcie: Handle various PD configurations
The i.MX SoCs have various power domain configurations routed into
the PCIe IP. MX6SX is the only one which contains 2 domains and also
uses power-domain-names. MX6QDL do not use any domains. All the rest
uses one domain and does not use power-domain-names anymore.
Document all those configurations in the DT binding document.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20221211024859.672076-2-marex@denx.de
Signed-off-by: Rob Herring <robh@kernel.org>
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| #
22c9f190 |
| 10-Dec-2022 |
Marek Vasut <marex@denx.de> |
dt-bindings: imx6q-pcie: Handle various clock configurations
The i.MX SoCs have various clock configurations routed into the PCIe IP,
the list of clock is below. Document all those configurations in
dt-bindings: imx6q-pcie: Handle various clock configurations
The i.MX SoCs have various clock configurations routed into the PCIe IP,
the list of clock is below. Document all those configurations in the DT
binding document.
All SoCs: pcie, pcie_bus
6QDL, 7D: + pcie_phy
6SX: + pcie_phy pcie_inbound_axi
8MQ: + pcie_phy pcie_aux
8MM, 8MP: + pcie_aux
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20221211024859.672076-1-marex@denx.de
Signed-off-by: Rob Herring <robh@kernel.org>
show more ...
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Revision tags: v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79 |
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| #
b8a83e60 |
| 13-Nov-2022 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
dt-bindings: imx6q-pcie: Fix clock names for imx6sx and imx8mq
Originally as it was defined the legacy bindings the pcie_inbound_axi and
pcie_aux clock names were supposed to be used in the fsl,imx6
dt-bindings: imx6q-pcie: Fix clock names for imx6sx and imx8mq
Originally as it was defined the legacy bindings the pcie_inbound_axi and
pcie_aux clock names were supposed to be used in the fsl,imx6sx-pcie and
fsl,imx8mq-pcie devices respectively. But the bindings conversion has been
incorrectly so now the fourth clock name is defined as "pcie_inbound_axi
for imx6sx-pcie, pcie_aux for imx8mq-pcie", which is completely wrong.
Let's fix that by conditionally apply the clock-names constraints based on
the compatible string content.
Link: https://lore.kernel.org/r/20221113191301.5526-2-Sergey.Semin@baikalelectronics.ru
Fixes: 751ca492f131 ("dt-bindings: PCI: imx6: convert the imx pcie controller to dtschema")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
show more ...
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Revision tags: v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56 |
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| #
fba48662 |
| 19-Jul-2022 |
Rob Herring <robh@kernel.org> |
dt-bindings: PCI: fsl,imx6q-pcie: Add missing type for 'reset-gpio-active-high'
'reset-gpio-active-high' is missing a type definition and is not a common
property. The type is boolean.
Signed-off-b
dt-bindings: PCI: fsl,imx6q-pcie: Add missing type for 'reset-gpio-active-high'
'reset-gpio-active-high' is missing a type definition and is not a common
property. The type is boolean.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
Link: https://lore.kernel.org/r/20220719215031.1875860-1-robh@kernel.org
show more ...
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Revision tags: v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27 |
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| #
9be01ee2 |
| 07-Mar-2022 |
Richard Zhu <hongxing.zhu@nxp.com> |
dt-bindings: imx6q-pcie: Add iMX8MP PCIe compatible string
Add i.MX8MP PCIe compatible string.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: h
dt-bindings: imx6q-pcie: Add iMX8MP PCIe compatible string
Add i.MX8MP PCIe compatible string.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1646644054-24421-5-git-send-email-hongxing.zhu@nxp.com
show more ...
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| #
21d5929f |
| 03-Mar-2022 |
Richard Zhu <hongxing.zhu@nxp.com> |
dt-bindings: imx6q-pcie: Add iMX8MM PCIe compatible string
Add the i.MX8MM PCIe compatible string.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de
dt-bindings: imx6q-pcie: Add iMX8MM PCIe compatible string
Add the i.MX8MM PCIe compatible string.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1646293805-18248-1-git-send-email-hongxing.zhu@nxp.com
show more ...
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Revision tags: v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7 |
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| #
3e15f623 |
| 02-Dec-2021 |
Richard Zhu <hongxing.zhu@nxp.com> |
dt-bindings: imx6q-pcie: Add PHY phandles and name properties
i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties
in the binding document.
Link: https://lore.kernel.org/r/1638432158-411
dt-bindings: imx6q-pcie: Add PHY phandles and name properties
i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties
in the binding document.
Link: https://lore.kernel.org/r/1638432158-4119-4-git-send-email-hongxing.zhu@nxp.com
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
show more ...
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Revision tags: v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9 |
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| #
67006e30 |
| 28-Sep-2021 |
Rob Herring <robh@kernel.org> |
dt-bindings: Drop more redundant 'maxItems/minItems'
Another round of removing redundant minItems/maxItems from new schema in
the recent merge window.
If a property has an 'items' list, then a 'min
dt-bindings: Drop more redundant 'maxItems/minItems'
Another round of removing redundant minItems/maxItems from new schema in
the recent merge window.
If a property has an 'items' list, then a 'minItems' or 'maxItems' with the
same size as the list is redundant and can be dropped. Note that is DT
schema specific behavior and not standard json-schema behavior. The tooling
will fixup the final schema adding any unspecified minItems/maxItems.
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Evgeniy Polyakov <zbr@ioremap.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Joakim Zhang <qiangqing.zhang@nxp.com>
Cc: dri-devel@lists.freedesktop.org
Cc: netdev@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210928222920.2204761-1-robh@kernel.org
show more ...
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Revision tags: v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14 |
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| #
751ca492 |
| 27-Aug-2021 |
Richard Zhu <hongxing.zhu@nxp.com> |
dt-bindings: PCI: imx6: convert the imx pcie controller to dtschema
Convert the fsl,imx6q-pcie.txt into a schema.
- ranges property should be grouped by region, with no functional
changes.
- only
dt-bindings: PCI: imx6: convert the imx pcie controller to dtschema
Convert the fsl,imx6q-pcie.txt into a schema.
- ranges property should be grouped by region, with no functional
changes.
- only one propert is allowed in the compatible string, remove
"snps,dw-pcie".
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Link: https://lore.kernel.org/r/1630046580-19282-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
show more ...
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