188f7f6bcSTeresa Remmet// SPDX-License-Identifier: GPL-2.0 288f7f6bcSTeresa Remmet/* 388f7f6bcSTeresa Remmet * Copyright (C) 2020 PHYTEC Messtechnik GmbH 488f7f6bcSTeresa Remmet * Author: Teresa Remmet <t.remmet@phytec.de> 588f7f6bcSTeresa Remmet */ 688f7f6bcSTeresa Remmet 788f7f6bcSTeresa Remmet#include <dt-bindings/net/ti-dp83867.h> 888f7f6bcSTeresa Remmet#include "imx8mp.dtsi" 988f7f6bcSTeresa Remmet 1088f7f6bcSTeresa Remmet/ { 1188f7f6bcSTeresa Remmet model = "PHYTEC phyCORE-i.MX8MP"; 1288f7f6bcSTeresa Remmet compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 1388f7f6bcSTeresa Remmet 1488f7f6bcSTeresa Remmet aliases { 1588f7f6bcSTeresa Remmet rtc0 = &rv3028; 1688f7f6bcSTeresa Remmet rtc1 = &snvs_rtc; 1788f7f6bcSTeresa Remmet }; 1888f7f6bcSTeresa Remmet 1988f7f6bcSTeresa Remmet memory@40000000 { 2088f7f6bcSTeresa Remmet device_type = "memory"; 2188f7f6bcSTeresa Remmet reg = <0x0 0x40000000 0 0x80000000>; 2288f7f6bcSTeresa Remmet }; 2388f7f6bcSTeresa Remmet}; 2488f7f6bcSTeresa Remmet 2588f7f6bcSTeresa Remmet&A53_0 { 2688f7f6bcSTeresa Remmet cpu-supply = <&buck2>; 2788f7f6bcSTeresa Remmet}; 2888f7f6bcSTeresa Remmet 2988f7f6bcSTeresa Remmet&A53_1 { 3088f7f6bcSTeresa Remmet cpu-supply = <&buck2>; 3188f7f6bcSTeresa Remmet}; 3288f7f6bcSTeresa Remmet 3388f7f6bcSTeresa Remmet&A53_2 { 3488f7f6bcSTeresa Remmet cpu-supply = <&buck2>; 3588f7f6bcSTeresa Remmet}; 3688f7f6bcSTeresa Remmet 3788f7f6bcSTeresa Remmet&A53_3 { 3888f7f6bcSTeresa Remmet cpu-supply = <&buck2>; 3988f7f6bcSTeresa Remmet}; 4088f7f6bcSTeresa Remmet 4188f7f6bcSTeresa Remmet/* ethernet 1 */ 4288f7f6bcSTeresa Remmet&fec { 4388f7f6bcSTeresa Remmet pinctrl-names = "default"; 4488f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_fec>; 4588f7f6bcSTeresa Remmet phy-handle = <ðphy1>; 462d3779ddSTeresa Remmet phy-mode = "rgmii-id"; 4788f7f6bcSTeresa Remmet fsl,magic-packet; 4888f7f6bcSTeresa Remmet status = "okay"; 4988f7f6bcSTeresa Remmet 5088f7f6bcSTeresa Remmet mdio { 5188f7f6bcSTeresa Remmet #address-cells = <1>; 5288f7f6bcSTeresa Remmet #size-cells = <0>; 5388f7f6bcSTeresa Remmet 5488f7f6bcSTeresa Remmet ethphy1: ethernet-phy@0 { 5588f7f6bcSTeresa Remmet compatible = "ethernet-phy-ieee802.3-c22"; 5688f7f6bcSTeresa Remmet reg = <0>; 572d3779ddSTeresa Remmet enet-phy-lane-no-swap; 582d3779ddSTeresa Remmet ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 592d3779ddSTeresa Remmet ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 602d3779ddSTeresa Remmet ti,min-output-impedance; 6188f7f6bcSTeresa Remmet ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 6288f7f6bcSTeresa Remmet ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 6388f7f6bcSTeresa Remmet }; 6488f7f6bcSTeresa Remmet }; 6588f7f6bcSTeresa Remmet}; 6688f7f6bcSTeresa Remmet 67a4f27c75SHeiko Schocher&flexspi { 68a4f27c75SHeiko Schocher pinctrl-names = "default"; 69a4f27c75SHeiko Schocher pinctrl-0 = <&pinctrl_flexspi0>; 70a4f27c75SHeiko Schocher status = "okay"; 71a4f27c75SHeiko Schocher 72a4f27c75SHeiko Schocher som_flash: flash@0 { 73a4f27c75SHeiko Schocher compatible = "jedec,spi-nor"; 74a4f27c75SHeiko Schocher reg = <0>; 75a4f27c75SHeiko Schocher spi-max-frequency = <80000000>; 76a4f27c75SHeiko Schocher spi-rx-bus-width = <4>; 772d3779ddSTeresa Remmet spi-tx-bus-width = <1>; 78a4f27c75SHeiko Schocher }; 79a4f27c75SHeiko Schocher}; 80a4f27c75SHeiko Schocher 8188f7f6bcSTeresa Remmet&i2c1 { 8288f7f6bcSTeresa Remmet clock-frequency = <400000>; 83412627f6STeresa Remmet pinctrl-names = "default", "gpio"; 8488f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_i2c1>; 8588f7f6bcSTeresa Remmet pinctrl-1 = <&pinctrl_i2c1_gpio>; 8688f7f6bcSTeresa Remmet scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 872d3779ddSTeresa Remmet sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 8888f7f6bcSTeresa Remmet status = "okay"; 8988f7f6bcSTeresa Remmet 9088f7f6bcSTeresa Remmet pmic: pmic@25 { 9188f7f6bcSTeresa Remmet compatible = "nxp,pca9450c"; 922d3779ddSTeresa Remmet reg = <0x25>; 932d3779ddSTeresa Remmet interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 942d3779ddSTeresa Remmet interrupt-parent = <&gpio4>; 9588f7f6bcSTeresa Remmet pinctrl-names = "default"; 9688f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_pmic>; 9788f7f6bcSTeresa Remmet 9888f7f6bcSTeresa Remmet regulators { 9988f7f6bcSTeresa Remmet buck1: BUCK1 { 10088f7f6bcSTeresa Remmet regulator-always-on; 1012d3779ddSTeresa Remmet regulator-boot-on; 102*6fe88df7STeresa Remmet regulator-max-microvolt = <1000000>; 103*6fe88df7STeresa Remmet regulator-min-microvolt = <805000>; 104c2d28a0cSTeresa Remmet regulator-name = "VDD_SOC (BUCK1)"; 10588f7f6bcSTeresa Remmet regulator-ramp-delay = <3125>; 10688f7f6bcSTeresa Remmet }; 10788f7f6bcSTeresa Remmet 10888f7f6bcSTeresa Remmet buck2: BUCK2 { 1098c0d1785STeresa Remmet nxp,dvs-run-voltage = <950000>; 1108c0d1785STeresa Remmet nxp,dvs-standby-voltage = <850000>; 1112d3779ddSTeresa Remmet regulator-always-on; 1122d3779ddSTeresa Remmet regulator-boot-on; 113*6fe88df7STeresa Remmet regulator-max-microvolt = <1050000>; 114*6fe88df7STeresa Remmet regulator-min-microvolt = <805000>; 115c2d28a0cSTeresa Remmet regulator-name = "VDD_ARM (BUCK2)"; 1162d3779ddSTeresa Remmet regulator-ramp-delay = <3125>; 11788f7f6bcSTeresa Remmet }; 11888f7f6bcSTeresa Remmet 11988f7f6bcSTeresa Remmet buck4: BUCK4 { 12088f7f6bcSTeresa Remmet regulator-always-on; 1212d3779ddSTeresa Remmet regulator-boot-on; 122*6fe88df7STeresa Remmet regulator-max-microvolt = <3300000>; 123*6fe88df7STeresa Remmet regulator-min-microvolt = <3300000>; 124c2d28a0cSTeresa Remmet regulator-name = "VDD_3V3 (BUCK4)"; 12588f7f6bcSTeresa Remmet }; 12688f7f6bcSTeresa Remmet 12788f7f6bcSTeresa Remmet buck5: BUCK5 { 12888f7f6bcSTeresa Remmet regulator-always-on; 1292d3779ddSTeresa Remmet regulator-boot-on; 130*6fe88df7STeresa Remmet regulator-max-microvolt = <1800000>; 131*6fe88df7STeresa Remmet regulator-min-microvolt = <1800000>; 132c2d28a0cSTeresa Remmet regulator-name = "VDD_1V8 (BUCK5)"; 13388f7f6bcSTeresa Remmet }; 13488f7f6bcSTeresa Remmet 13588f7f6bcSTeresa Remmet buck6: BUCK6 { 13688f7f6bcSTeresa Remmet regulator-always-on; 1372d3779ddSTeresa Remmet regulator-boot-on; 138*6fe88df7STeresa Remmet regulator-max-microvolt = <1155000>; 139*6fe88df7STeresa Remmet regulator-min-microvolt = <1045000>; 140c2d28a0cSTeresa Remmet regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; 14188f7f6bcSTeresa Remmet }; 14288f7f6bcSTeresa Remmet 14388f7f6bcSTeresa Remmet ldo1: LDO1 { 14488f7f6bcSTeresa Remmet regulator-always-on; 1452d3779ddSTeresa Remmet regulator-boot-on; 146*6fe88df7STeresa Remmet regulator-max-microvolt = <1950000>; 147*6fe88df7STeresa Remmet regulator-min-microvolt = <1710000>; 148c2d28a0cSTeresa Remmet regulator-name = "NVCC_SNVS_1V8 (LDO1)"; 14988f7f6bcSTeresa Remmet }; 15088f7f6bcSTeresa Remmet 15188f7f6bcSTeresa Remmet ldo3: LDO3 { 15288f7f6bcSTeresa Remmet regulator-always-on; 1532d3779ddSTeresa Remmet regulator-boot-on; 154*6fe88df7STeresa Remmet regulator-max-microvolt = <1800000>; 155*6fe88df7STeresa Remmet regulator-min-microvolt = <1800000>; 156c2d28a0cSTeresa Remmet regulator-name = "VDDA_1V8 (LDO3)"; 15788f7f6bcSTeresa Remmet }; 15888f7f6bcSTeresa Remmet 15988f7f6bcSTeresa Remmet ldo5: LDO5 { 160b00e3e03STeresa Remmet regulator-always-on; 1612d3779ddSTeresa Remmet regulator-boot-on; 1622d3779ddSTeresa Remmet regulator-max-microvolt = <3300000>; 1632d3779ddSTeresa Remmet regulator-min-microvolt = <1800000>; 164c2d28a0cSTeresa Remmet regulator-name = "NVCC_SD2 (LDO5)"; 16588f7f6bcSTeresa Remmet }; 16688f7f6bcSTeresa Remmet }; 16788f7f6bcSTeresa Remmet }; 16888f7f6bcSTeresa Remmet 16988f7f6bcSTeresa Remmet eeprom@51 { 17088f7f6bcSTeresa Remmet compatible = "atmel,24c32"; 17188f7f6bcSTeresa Remmet reg = <0x51>; 17288f7f6bcSTeresa Remmet pagesize = <32>; 17388f7f6bcSTeresa Remmet }; 17488f7f6bcSTeresa Remmet 17588f7f6bcSTeresa Remmet rv3028: rtc@52 { 17688f7f6bcSTeresa Remmet compatible = "microcrystal,rv3028"; 17788f7f6bcSTeresa Remmet reg = <0x52>; 17888f7f6bcSTeresa Remmet trickle-resistor-ohms = <3000>; 17988f7f6bcSTeresa Remmet }; 18088f7f6bcSTeresa Remmet}; 18188f7f6bcSTeresa Remmet 18288f7f6bcSTeresa Remmet/* eMMC */ 18388f7f6bcSTeresa Remmet&usdhc3 { 18459f5ae05SJonas Kuenstler assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 18559f5ae05SJonas Kuenstler assigned-clock-rates = <400000000>; 18688f7f6bcSTeresa Remmet pinctrl-names = "default", "state_100mhz", "state_200mhz"; 18788f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_usdhc3>; 18888f7f6bcSTeresa Remmet pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 18988f7f6bcSTeresa Remmet pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 19088f7f6bcSTeresa Remmet bus-width = <8>; 19188f7f6bcSTeresa Remmet non-removable; 19288f7f6bcSTeresa Remmet status = "okay"; 19388f7f6bcSTeresa Remmet}; 19488f7f6bcSTeresa Remmet 19588f7f6bcSTeresa Remmet&wdog1 { 19688f7f6bcSTeresa Remmet pinctrl-names = "default"; 19788f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_wdog>; 19888f7f6bcSTeresa Remmet fsl,ext-reset-output; 19988f7f6bcSTeresa Remmet status = "okay"; 20088f7f6bcSTeresa Remmet}; 20188f7f6bcSTeresa Remmet 20288f7f6bcSTeresa Remmet&iomuxc { 20388f7f6bcSTeresa Remmet pinctrl_fec: fecgrp { 20488f7f6bcSTeresa Remmet fsl,pins = < 205b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 206b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 207b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 208b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 209b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 210b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 211b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 21297c8800eSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 21397c8800eSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 21497c8800eSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 21597c8800eSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 21697c8800eSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 21797c8800eSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 218b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 21988f7f6bcSTeresa Remmet >; 22088f7f6bcSTeresa Remmet }; 22188f7f6bcSTeresa Remmet 222a4f27c75SHeiko Schocher pinctrl_flexspi0: flexspi0grp { 223a4f27c75SHeiko Schocher fsl,pins = < 224a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 225a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 226a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 227a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 228a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 229a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 230a4f27c75SHeiko Schocher >; 231a4f27c75SHeiko Schocher }; 232a4f27c75SHeiko Schocher 23388f7f6bcSTeresa Remmet pinctrl_i2c1: i2c1grp { 23488f7f6bcSTeresa Remmet fsl,pins = < 235b34f6681STeresa Remmet MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 236b34f6681STeresa Remmet MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 23788f7f6bcSTeresa Remmet >; 23888f7f6bcSTeresa Remmet }; 23988f7f6bcSTeresa Remmet 24088f7f6bcSTeresa Remmet pinctrl_i2c1_gpio: i2c1gpiogrp { 24188f7f6bcSTeresa Remmet fsl,pins = < 242b34f6681STeresa Remmet MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 243b34f6681STeresa Remmet MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 24488f7f6bcSTeresa Remmet >; 24588f7f6bcSTeresa Remmet }; 24688f7f6bcSTeresa Remmet 24788f7f6bcSTeresa Remmet pinctrl_pmic: pmicirqgrp { 24888f7f6bcSTeresa Remmet fsl,pins = < 249b34f6681STeresa Remmet MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 25088f7f6bcSTeresa Remmet >; 25188f7f6bcSTeresa Remmet }; 25288f7f6bcSTeresa Remmet 25388f7f6bcSTeresa Remmet pinctrl_usdhc3: usdhc3grp { 25488f7f6bcSTeresa Remmet fsl,pins = < 2552d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 2562d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 2572d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 2582d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 25988f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 26088f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 26188f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 26288f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 26388f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 2642d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 2652d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 26688f7f6bcSTeresa Remmet >; 26788f7f6bcSTeresa Remmet }; 26888f7f6bcSTeresa Remmet 26988f7f6bcSTeresa Remmet pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 27088f7f6bcSTeresa Remmet fsl,pins = < 2712d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 2722d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 2732d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 2742d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 27588f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 27688f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 27788f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 27888f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 27988f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 2802d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 2812d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 28288f7f6bcSTeresa Remmet >; 28388f7f6bcSTeresa Remmet }; 28488f7f6bcSTeresa Remmet 28588f7f6bcSTeresa Remmet pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 28688f7f6bcSTeresa Remmet fsl,pins = < 2872d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 2882d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 2892d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 2902d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 291c173a181STeresa Remmet MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 292c173a181STeresa Remmet MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 293c173a181STeresa Remmet MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 294c173a181STeresa Remmet MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 295c173a181STeresa Remmet MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 2962d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 2972d3779ddSTeresa Remmet MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 29888f7f6bcSTeresa Remmet >; 29988f7f6bcSTeresa Remmet }; 30088f7f6bcSTeresa Remmet 30188f7f6bcSTeresa Remmet pinctrl_wdog: wdoggrp { 30288f7f6bcSTeresa Remmet fsl,pins = < 3032aeded99STeresa Remmet MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 30488f7f6bcSTeresa Remmet >; 30588f7f6bcSTeresa Remmet }; 30688f7f6bcSTeresa Remmet}; 307