1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/net/qca-ar803x.h>
9#include "imx8mp.dtsi"
10
11/ {
12	model = "Data Modul i.MX8M Plus eDM SBC";
13	compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
14
15	aliases {
16		rtc0 = &rtc;
17		rtc1 = &snvs_rtc;
18	};
19
20	chosen {
21		stdout-path = &uart3;
22	};
23
24	memory@40000000 {
25		device_type = "memory";
26		/* There are 1/2/4 GiB options, adjusted by bootloader. */
27		reg = <0x0 0x40000000 0 0x40000000>;
28	};
29
30	backlight: backlight {
31		compatible = "pwm-backlight";
32		pinctrl-names = "default";
33		pinctrl-0 = <&pinctrl_panel_backlight>;
34		brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
35		default-brightness-level = <7>;
36		enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
37		pwms = <&pwm1 0 5000000 0>;
38		/* Disabled by default, unless display board plugged in. */
39		status = "disabled";
40	};
41
42	clk_xtal25: clock-xtal25 {
43		compatible = "fixed-clock";
44		#clock-cells = <0>;
45		clock-frequency = <25000000>;
46	};
47
48	panel: panel {
49		/* Compatible string is filled in by panel board DT Overlay. */
50		backlight = <&backlight>;
51		power-supply = <&reg_panel_vcc>;
52		/* Disabled by default, unless display board plugged in. */
53		status = "disabled";
54	};
55
56	reg_panel_vcc: regulator-panel-vcc {
57		compatible = "regulator-fixed";
58		pinctrl-names = "default";
59		pinctrl-0 = <&pinctrl_panel_vcc_reg>;
60		regulator-min-microvolt = <5000000>;
61		regulator-max-microvolt = <5000000>;
62		regulator-name = "PANEL_VCC";
63		/* GPIO flags are ignored, enable-active-high applies. */
64		gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
65		enable-active-high;
66		/* Disabled by default, unless display board plugged in. */
67		status = "disabled";
68	};
69
70	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
71		compatible = "regulator-fixed";
72		pinctrl-names = "default";
73		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
74		regulator-max-microvolt = <3300000>;
75		regulator-min-microvolt = <3300000>;
76		regulator-name = "VDD_3V3_SD";
77		/* GPIO flags are ignored, enable-active-high applies. */
78		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */
79		enable-active-high;
80		off-on-delay-us = <12000>;
81		startup-delay-us = <100>;
82		vin-supply = <&buck4>;
83	};
84
85	watchdog { /* TPS3813 */
86		compatible = "linux,wdt-gpio";
87		pinctrl-names = "default";
88		pinctrl-0 = <&pinctrl_watchdog_gpio>;
89		always-running;
90		gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
91		hw_algo = "level";
92		/* Reset triggers in 2..3 seconds */
93		hw_margin_ms = <1500>;
94		/* Disabled by default */
95		status = "disabled";
96	};
97};
98
99&A53_0 {
100	cpu-supply = <&buck2>;
101};
102
103&A53_1 {
104	cpu-supply = <&buck2>;
105};
106
107&A53_2 {
108	cpu-supply = <&buck2>;
109};
110
111&A53_3 {
112	cpu-supply = <&buck2>;
113};
114
115&ecspi1 {
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_ecspi1>;
118	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
119	status = "okay";
120
121	flash@0 {	/* W25Q128JVEI */
122		compatible = "jedec,spi-nor";
123		reg = <0>;
124		spi-max-frequency = <40000000>;
125		spi-tx-bus-width = <1>;
126		spi-rx-bus-width = <1>;
127	};
128};
129
130&ecspi2 {	/* Feature connector SPI */
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_ecspi2>;
133	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
134	/* Disabled by default, unless feature board plugged in. */
135	status = "disabled";
136};
137
138&ecspi3 {	/* Display connector SPI */
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_ecspi3>;
141	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
142	/* Disabled by default, unless display board plugged in. */
143	status = "disabled";
144};
145
146&eqos {	/* First ethernet */
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_eqos>;
149	phy-handle = <&phy_eqos>;
150	phy-mode = "rgmii-id";
151	status = "okay";
152
153	mdio {
154		compatible = "snps,dwmac-mdio";
155		#address-cells = <1>;
156		#size-cells = <0>;
157
158		/* Atheros AR8031 PHY */
159		phy_eqos: ethernet-phy@0 {
160			compatible = "ethernet-phy-ieee802.3-c22";
161			reg = <0>;
162			/*
163			 * Dedicated ENET_WOL# signal is unused, the PHY
164			 * can wake the SoC up via INT signal as well.
165			 */
166			interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
167			reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
168			reset-assert-us = <10000>;
169			reset-deassert-us = <10000>;
170			qca,keep-pll-enabled;
171			vddio-supply = <&vddio_eqos>;
172
173			vddio_eqos: vddio-regulator {
174				regulator-name = "VDDIO_EQOS";
175				regulator-min-microvolt = <1800000>;
176				regulator-max-microvolt = <1800000>;
177			};
178
179			vddh_eqos: vddh-regulator {
180				regulator-name = "VDDH_EQOS";
181			};
182		};
183	};
184};
185
186&fec {	/* Second ethernet */
187	pinctrl-names = "default";
188	pinctrl-0 = <&pinctrl_fec>;
189	phy-handle = <&phy_fec>;
190	phy-mode = "rgmii-id";
191	fsl,magic-packet;
192	status = "okay";
193
194	mdio {
195		#address-cells = <1>;
196		#size-cells = <0>;
197
198		/* Atheros AR8031 PHY */
199		phy_fec: ethernet-phy@0 {
200			compatible = "ethernet-phy-ieee802.3-c22";
201			reg = <0>;
202			/*
203			 * Dedicated ENET_WOL# signal is unused, the PHY
204			 * can wake the SoC up via INT signal as well.
205			 */
206			interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>;
207			reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
208			reset-assert-us = <10000>;
209			reset-deassert-us = <10000>;
210			qca,keep-pll-enabled;
211			vddio-supply = <&vddio_fec>;
212
213			vddio_fec: vddio-regulator {
214				regulator-name = "VDDIO_FEC";
215				regulator-min-microvolt = <1800000>;
216				regulator-max-microvolt = <1800000>;
217			};
218
219			vddh_fec: vddh-regulator {
220				regulator-name = "VDDH_FEC";
221			};
222		};
223	};
224};
225
226&flexcan1 {
227	pinctrl-names = "default";
228	pinctrl-0 = <&pinctrl_flexcan1>;
229	status = "okay";
230};
231
232&gpio1 {
233	gpio-line-names =
234		"", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#",
235		"", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03",
236		"GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#",
237		"", "", "", "ENET_RST#",
238		"", "", "", "", "", "", "", "",
239		"", "", "", "", "", "", "", "";
240};
241
242&gpio2 {
243	gpio-line-names =
244		"", "", "ENET2_INT#", "", "", "", "", "",
245		"WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#",
246		"", "", "", "",
247		"", "", "", "SD2_RESET#", "", "", "", "",
248		"", "", "", "", "", "", "", "";
249};
250
251&gpio3 {
252	gpio-line-names =
253		"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
254		"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
255		"CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "",
256		"", "", "EEPROM_WP_1V8#", "", "", "", "", "",
257		"MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#",
258		"", "M2_W_DISABLE1_1V8#",
259		"M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3",
260		"", "", "", "";
261};
262
263&gpio4 {
264	gpio-line-names =
265		"DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "",
266		"", "", "", "", "", "", "", "",
267		"", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#",
268		"", "DIS_USB_DN1", "DIS_USB_DN2", "",
269		"", "", "", "", "", "", "", "";
270};
271
272&gpio5 {
273	gpio-line-names =
274		"", "", "", "", "", "WDOG_EN", "", "",
275		"", "SPI1_CS#", "", "",
276		"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
277		"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
278		"", "", "", "",
279		"", "SPI3_CS#", "", "", "", "", "", "";
280};
281
282&i2c1 {
283	clock-frequency = <100000>;
284	pinctrl-names = "default", "gpio";
285	pinctrl-0 = <&pinctrl_i2c1>;
286	pinctrl-1 = <&pinctrl_i2c1_gpio>;
287	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
288	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
289	status = "okay";
290
291	usb-hub@2c {
292		compatible = "microchip,usb2514bi";
293		reg = <0x2c>;
294		pinctrl-names = "default";
295		pinctrl-0 = <&pinctrl_usb_hub>;
296		individual-port-switching;
297		reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
298		self-powered;
299	};
300
301	eeprom: eeprom@50 {
302		compatible = "atmel,24c32";
303		reg = <0x50>;
304		pagesize = <32>;
305	};
306
307	rtc: rtc@68 {
308		compatible = "st,m41t62";
309		reg = <0x68>;
310		pinctrl-names = "default";
311		pinctrl-0 = <&pinctrl_rtc>;
312		interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
313	};
314
315	pcieclk: clk@6a {
316		compatible = "renesas,9fgv0241";
317		reg = <0x6a>;
318		clocks = <&clk_xtal25>;
319		#clock-cells = <1>;
320	};
321};
322
323&i2c2 {
324	clock-frequency = <100000>;
325	pinctrl-names = "default", "gpio";
326	pinctrl-0 = <&pinctrl_i2c2>;
327	pinctrl-1 = <&pinctrl_i2c2_gpio>;
328	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
329	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
330	status = "okay";
331};
332
333&i2c3 {
334	clock-frequency = <100000>;
335	pinctrl-names = "default", "gpio";
336	pinctrl-0 = <&pinctrl_i2c3>;
337	pinctrl-1 = <&pinctrl_i2c3_gpio>;
338	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
339	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
340	status = "okay";
341
342	pmic: pmic@25 {
343		compatible = "nxp,pca9450c";
344		reg = <0x25>;
345		pinctrl-names = "default";
346		pinctrl-0 = <&pinctrl_pmic>;
347		interrupt-parent = <&gpio1>;
348		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
349
350		/*
351		 * i.MX 8M Plus Data Sheet for Consumer Products
352		 * 3.1.4 Operating ranges
353		 * MIMX8ML8CVNKZAB
354		 */
355		regulators {
356			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
357				regulator-min-microvolt = <850000>;
358				regulator-max-microvolt = <1000000>;
359				regulator-ramp-delay = <3125>;
360				regulator-always-on;
361				regulator-boot-on;
362			};
363
364			buck2: BUCK2 {	/* VDD_ARM */
365				regulator-min-microvolt = <850000>;
366				regulator-max-microvolt = <1000000>;
367				regulator-ramp-delay = <3125>;
368				regulator-always-on;
369				regulator-boot-on;
370			};
371
372			buck4: BUCK4 {	/* VDD_3V3 */
373				regulator-min-microvolt = <3300000>;
374				regulator-max-microvolt = <3300000>;
375				regulator-always-on;
376				regulator-boot-on;
377			};
378
379			buck5: BUCK5 {	/* VDD_1V8 */
380				regulator-min-microvolt = <1800000>;
381				regulator-max-microvolt = <1800000>;
382				regulator-always-on;
383				regulator-boot-on;
384			};
385
386			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
387				regulator-min-microvolt = <1100000>;
388				regulator-max-microvolt = <1100000>;
389				regulator-always-on;
390				regulator-boot-on;
391			};
392
393			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
394				regulator-min-microvolt = <1800000>;
395				regulator-max-microvolt = <1800000>;
396				regulator-always-on;
397				regulator-boot-on;
398			};
399
400			ldo3: LDO3 {	/* VDDA_1V8 */
401				regulator-min-microvolt = <1800000>;
402				regulator-max-microvolt = <1800000>;
403				regulator-always-on;
404				regulator-boot-on;
405			};
406
407			ldo4: LDO4 {	/* PMIC_LDO4 */
408				regulator-min-microvolt = <3300000>;
409				regulator-max-microvolt = <3300000>;
410			};
411
412			ldo5: LDO5 {	/* NVCC_SD2 */
413				regulator-min-microvolt = <1800000>;
414				regulator-max-microvolt = <3300000>;
415			};
416		};
417	};
418};
419
420&i2c5 {	/* HDMI EDID bus */
421	clock-frequency = <100000>;
422	pinctrl-names = "default", "gpio";
423	pinctrl-0 = <&pinctrl_i2c5>;
424	pinctrl-1 = <&pinctrl_i2c5_gpio>;
425	scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
426	sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
427	status = "okay";
428};
429
430&pwm1 {
431	pinctrl-names = "default";
432	pinctrl-0 = <&pinctrl_panel_pwm>;
433	/* Disabled by default, unless display board plugged in. */
434	status = "disabled";
435};
436
437/* SD slot */
438&usdhc2 {
439	pinctrl-names = "default", "state_100mhz", "state_200mhz";
440	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
441	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
442	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
443	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
444	vmmc-supply = <&reg_usdhc2_vmmc>;
445	bus-width = <4>;
446	status = "okay";
447};
448
449/* eMMC */
450&usdhc3 {
451	pinctrl-names = "default", "state_100mhz", "state_200mhz";
452	pinctrl-0 = <&pinctrl_usdhc3>;
453	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
454	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
455	vmmc-supply = <&buck4>;
456	vqmmc-supply = <&buck5>;
457	bus-width = <8>;
458	no-sd;
459	no-sdio;
460	non-removable;
461	status = "okay";
462};
463
464&uart1 {	/* RS485 */
465	pinctrl-names = "default";
466	pinctrl-0 = <&pinctrl_uart1>;
467	uart-has-rtscts;
468	status = "disabled";	/* Optional */
469};
470
471&uart2 {
472	pinctrl-names = "default";
473	pinctrl-0 = <&pinctrl_uart2>;
474	uart-has-rtscts;
475	status = "okay";
476};
477
478&uart3 {	/* A53 Debug */
479	pinctrl-names = "default";
480	pinctrl-0 = <&pinctrl_uart3>;
481	status = "okay";
482};
483
484&uart4 {
485	pinctrl-names = "default";
486	pinctrl-0 = <&pinctrl_uart4>;
487	status = "disabled";
488};
489
490&usb3_phy0 {
491	status = "okay";
492};
493
494&usb3_0 {
495	fsl,over-current-active-low;
496	status = "okay";
497};
498
499&usb_dwc3_0 {	/* Lower plug direct */
500	pinctrl-names = "default";
501	pinctrl-0 = <&pinctrl_usb1>;
502	dr_mode = "host";
503	status = "okay";
504};
505
506&usb3_phy1 {
507	status = "okay";
508};
509
510&usb3_1 {
511	status = "okay";
512};
513
514&usb_dwc3_1 {	/* Upper plug via HUB */
515	dr_mode = "host";
516	status = "okay";
517};
518
519&wdog1 {
520	status = "okay";
521};
522
523/* IOMUXC node should be at the end of DT to improve readability. */
524&iomuxc {
525	pinctrl-names = "default";
526	pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
527		    <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
528		    <&pinctrl_panel_expansion>;
529
530	pinctrl_ecspi1: ecspi1-grp {
531		fsl,pins = <
532			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x44
533			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x44
534			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x44
535			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40
536		>;
537	};
538
539	pinctrl_ecspi2: ecspi2-grp {
540		fsl,pins = <
541			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44
542			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44
543			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44
544			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40
545		>;
546	};
547
548	pinctrl_ecspi3: ecspi3-grp {
549		fsl,pins = <
550			MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK		0x44
551			MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI		0x44
552			MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO		0x44
553			MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25		0x40
554		>;
555	};
556
557	pinctrl_eqos: eqos-grp {
558		fsl,pins = <
559			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
560			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
561			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
562			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
563			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
564			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
565			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
566			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
567			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
568			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
569			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
570			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
571			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
572			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
573			/* ENET_RST# */
574			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x6
575			/* ENET_INT# */
576			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x40000090
577		>;
578	};
579
580	pinctrl_fec: fec-grp {
581		fsl,pins = <
582			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
583			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
584			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
585			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
586			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
587			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
588			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
589			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
590			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
591			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
592			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
593			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
594			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
595			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
596			/* ENET2_RST# */
597			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x6
598			/* ENET2_INT# */
599			MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02		0x40000090
600		>;
601	};
602
603	pinctrl_flexcan1: flexcan1-grp {
604		fsl,pins = <
605			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
606			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
607		>;
608	};
609
610	pinctrl_hog_feature: hog-feature-grp {
611		fsl,pins = <
612			/* GPIO5_IO03 */
613			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x40000006
614			/* GPIO5_IO04 */
615			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x40000006
616
617			/* CAN_INT# */
618			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x40000090
619		>;
620	};
621
622	pinctrl_hog_panel: hog-panel-grp {
623		fsl,pins = <
624			/* GRAPHICS_GPIO0_1V8 */
625			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07		0x26
626		>;
627	};
628
629	pinctrl_hog_misc: hog-misc-grp {
630		fsl,pins = <
631			/* ENET_WOL# -- shared by both PHYs */
632			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x40000090
633
634			/* PG_V_IN_VAR# */
635			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01		0x40000000
636			/* CSI2_PD_1V8 */
637			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08		0x0
638			/* CSI2_RESET_1V8# */
639			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09		0x0
640
641			/* DIS_USB_DN1 */
642			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x0
643			/* DIS_USB_DN2 */
644			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x0
645
646			/* EEPROM_WP_1V8# */
647			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x100
648			/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
649			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x0
650			/* GRAPHICS_PRSNT_1V8# */
651			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x40000000
652
653			/* CLK_CCM_CLKO1_3V3 */
654			MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1		0x10
655		>;
656	};
657
658	pinctrl_hog_sbc: hog-sbc-grp {
659		fsl,pins = <
660			/* MEMCFG[0..2] straps */
661			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x40000140
662			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x40000140
663			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x40000140
664		>;
665	};
666
667	pinctrl_i2c1: i2c1-grp {
668		fsl,pins = <
669			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x40000084
670			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x40000084
671		>;
672	};
673
674	pinctrl_i2c1_gpio: i2c1-gpio-grp {
675		fsl,pins = <
676			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x84
677			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x84
678		>;
679	};
680
681	pinctrl_i2c2: i2c2-grp {
682		fsl,pins = <
683			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x40000084
684			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x40000084
685		>;
686	};
687
688	pinctrl_i2c2_gpio: i2c2-gpio-grp {
689		fsl,pins = <
690			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x84
691			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x84
692		>;
693	};
694
695	pinctrl_i2c3: i2c3-grp {
696		fsl,pins = <
697			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084
698			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084
699		>;
700	};
701
702	pinctrl_i2c3_gpio: i2c3-gpio-grp {
703		fsl,pins = <
704			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84
705			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84
706		>;
707	};
708
709	pinctrl_i2c5: i2c5-grp {
710		fsl,pins = <
711			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084
712			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084
713		>;
714	};
715
716	pinctrl_i2c5_gpio: i2c5-gpio-grp {
717		fsl,pins = <
718			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84
719			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84
720		>;
721	};
722
723	pinctrl_panel_backlight: panel-backlight-grp {
724		fsl,pins = <
725			/* BL_ENABLE_1V8 */
726			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00		0x104
727		>;
728	};
729
730	pinctrl_panel_expansion: panel-expansion-grp {
731		fsl,pins = <
732			/* DSI_RESET_1V8# */
733			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x2
734			/* DSI_IRQ_1V8# */
735			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000090
736		>;
737	};
738
739	pinctrl_panel_pwm: panel-pwm-grp {
740		fsl,pins = <
741			/* BL_PWM_3V3 */
742			MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT			0x12
743		>;
744	};
745
746	pinctrl_panel_vcc_reg: panel-vcc-grp {
747		fsl,pins = <
748			/* TFT_ENABLE_1V8 */
749			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06		0x104
750		>;
751	};
752
753	pinctrl_pcie0: pcie-grp {
754		fsl,pins = <
755			/* M2_PCIE_RST# */
756			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2
757			/* M2_W_DISABLE1_1V8# */
758			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x2
759			/* M2_W_DISABLE2_1V8# */
760			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x2
761			/* CLK_M2_32K768 */
762			MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1		0x14
763			/* M2_PCIE_WAKE# */
764			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x40000140
765			/* M2_PCIE_CLKREQ# */
766			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B		0x61
767		>;
768	};
769
770	pinctrl_pdm: pdm-grp {
771		fsl,pins = <
772			/* PDM_SEL */
773			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x0
774			MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK		0x0
775			MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00	0x0
776		>;
777	};
778
779	pinctrl_pmic: pmic-grp {
780		fsl,pins = <
781			/* PMIC_nINT */
782			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090
783		>;
784	};
785
786	pinctrl_rtc: rtc-grp {
787		fsl,pins = <
788			/* RTC_IRQ# */
789			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x40000090
790		>;
791	};
792
793	pinctrl_sai1: sai1-grp {
794		fsl,pins = <
795			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC	0xd6
796			MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00	0xd6
797			MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK	0xd6
798			MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK	0xd6
799			MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00	0xd6
800		>;
801	};
802
803	pinctrl_sai2: sai2-grp {
804		fsl,pins = <
805			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6
806			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6
807			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6
808			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK	0xd6
809		>;
810	};
811
812	pinctrl_sai3: sai3-grp {
813		fsl,pins = <
814			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
815			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
816			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
817			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6
818			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
819		>;
820	};
821
822	pinctrl_uart1: uart1-grp {
823		fsl,pins = <
824			MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX		0x49
825			MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX		0x49
826			MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS		0x49
827			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
828		>;
829	};
830
831	pinctrl_uart2: uart2-grp {
832		fsl,pins = <
833			MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX		0x49
834			MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX		0x49
835			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49
836			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49
837		>;
838	};
839
840	pinctrl_uart3: uart3-grp {
841		fsl,pins = <
842			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49
843			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49
844		>;
845	};
846
847	pinctrl_uart4: uart4-grp {
848		fsl,pins = <
849			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
850			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
851		>;
852	};
853
854	pinctrl_usdhc2: usdhc2-grp {
855		fsl,pins = <
856			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
857			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
858			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
859			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
860			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
861			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
862			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
863		>;
864	};
865
866	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
867		fsl,pins = <
868			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
869			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
870			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
871			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
872			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
873			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
874			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
875		>;
876	};
877
878	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
879		fsl,pins = <
880			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
881			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
882			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
883			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
884			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
885			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
886			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
887		>;
888	};
889
890	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
891		fsl,pins = <
892			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20
893		>;
894	};
895
896	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
897		fsl,pins = <
898			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080
899		>;
900	};
901
902	pinctrl_usdhc3: usdhc3-grp {
903		fsl,pins = <
904			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
905			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
906			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
907			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
908			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
909			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
910			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
911			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
912			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
913			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
914			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
915			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
916		>;
917	};
918
919	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
920		fsl,pins = <
921			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
922			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
923			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
924			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
925			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
926			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
927			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
928			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
929			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
930			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
931			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
932			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
933		>;
934	};
935
936	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
937		fsl,pins = <
938			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
939			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
940			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
941			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
942			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
943			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
944			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
945			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
946			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
947			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
948			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
949			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
950		>;
951	};
952
953	pinctrl_usb_hub: usb-hub-grp {
954		fsl,pins = <
955			/* USBHUB_RESET# */
956			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x4
957		>;
958	};
959
960	pinctrl_usb1: usb1-grp {
961		fsl,pins = <
962			MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR		0x6
963			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x80
964		>;
965	};
966
967	pinctrl_watchdog_gpio: watchdog-gpio-grp {
968		fsl,pins = <
969			/* WDOG_B# */
970			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0x26
971			/* WDOG_EN -- ungate WDT RESET# signal propagation */
972			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x6
973			/* WDOG_KICK# / WDI */
974			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x26
975		>;
976	};
977};
978